This is an RFC series that aims to implement a driver for the BIST
(Built-In Self Test) module for K3 devices. The BIST driver must ideally
support triggering of BIST tests, both PBIST (Memory BIST) and LBIST
(Logic BIST) on a core. Both tests are destructive in nature. Please see
links [1] and [2] for further information regarding the two.
At boot up, BIST is executed by hardware for the MCU domain
automatically as part of HW POST. So BIST has been checked only for the
MCU domain, and it makes sense to include our driver for BIST at the MCU
R5 SPL stage. The driver can trigger BIST runs for the rest of the cores
before loading and running any firmware on the cores.
The general procedure for triggering BIST on a core is:
1. Power on the core under test
2. Trigger the BIST test
3. Reset the core under test
This series, triggers PBIST tests on the MAIN_R5_2_x cores.
This is marked as RFC for a couple of WIP reasons:
- the core under test is confirmed to be accessible (powered on)
before running the test, and unaccessible after running the
test by connecting the debugger to the core, however the
firmware calls that check if a core is running or not at A72
U-Boot stage responds as the core is still running. Due to
this, before loading or running firmware, an explicit 'stop'
needs to be issued by the remoteproc framework (which does not
work at the earlier R5 stage as the DM firmware is not up
yet). Please see the boot logs to understand. This is under
debug.
- the driver currently implements all three PBIST tests (PBIST,
PBIST failure insertion and PBIST ROM); LBIST is WIP but will
be more or less similar to how PBIST has been implemented
Would appreciate reviews/comments on how this driver is modelled.
Boot logs:
https://gist.github.com/nehamalcom/63e94dbfc8a9b9fcaba6f45210e20cea
[1]
https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/pbist.html#introduction
[2]
https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/lbist.html#introduction
Neha Malcom Francis (6):
arm: mach-k3: j784s4: Add clk and power support for MAIN_R5_2_x PBIST
arm: dts: k3-j784s4-main: Add PBIST_14 node
arm: dts: k3-j784s4-main: Add clock and power domains for MAIN_R5_2_x
drivers: misc: k3_bist: Add K3 BIST driver
arm: mach-k3: j784s4_init: Trigger BIST
configs: j784s4_evm_r5_defconfig: Enable BIST
arch/arm/mach-k3/j784s4/j784s4_init.c | 11 +
arch/arm/mach-k3/r5/j784s4/clk-data.c | 13 +
arch/arm/mach-k3/r5/j784s4/dev-data.c | 7 +
configs/j784s4_evm_r5_defconfig | 2 +
drivers/misc/Kconfig | 8 +
drivers/misc/Makefile | 1 +
drivers/misc/k3_bist.c | 507 ++++++++++++++++
drivers/misc/k3_bist_static_data.h | 551 ++++++++++++++++++
dts/upstream/src/arm64/ti/k3-j784s4-main.dtsi | 19 +
9 files changed, 1119 insertions(+)
create mode 100644 drivers/misc/k3_bist.c
create mode 100644 drivers/misc/k3_bist_static_data.h
--
2.34.1
