Trigger BIST on MAIN_R5_2_x cores from R5 SPL on J784S4.

Signed-off-by: Neha Malcom Francis <n-fran...@ti.com>
---
 arch/arm/mach-k3/j784s4/j784s4_init.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c 
b/arch/arm/mach-k3/j784s4/j784s4_init.c
index 07b5d7d7504..993d24a9447 100644
--- a/arch/arm/mach-k3/j784s4/j784s4_init.c
+++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
@@ -233,9 +233,20 @@ void k3_mem_init(void)
 
 void board_init_f(ulong dummy)
 {
+       struct udevice *dev;
+       int ret;
+
        k3_spl_init();
        k3_mem_init();
 
+       if (IS_ENABLED(CONFIG_CPU_V7R) && IS_ENABLED(CONFIG_K3_BIST)) {
+               ret = uclass_get_device_by_driver(UCLASS_MISC,
+                                                 DM_DRIVER_GET(k3_bist),
+                                                 &dev);
+               if (ret)
+                       printf("Failed to run BIST: %d\n", ret);
+       }
+
        if (IS_ENABLED(CONFIG_CPU_V7R))
                setup_navss_nb();
 
-- 
2.34.1

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