On 6/26/19 12:39 PM, Melin Tomas wrote: > > On 6/26/19 1:26 PM, Marek Vasut wrote: >> On 6/26/19 12:12 PM, Melin Tomas wrote: >>> On 6/26/19 12:46 PM, Marek Vasut wrote: >>> >>>> On 6/26/19 7:30 AM, Melin Tomas wrote: >>>>> On 6/25/19 6:15 PM, Marek Vasut wrote: >>>>> >>>>>> On 6/25/19 3:30 PM, Melin Tomas wrote: >>>>>>> Prior to starting a new transfer, conditionally wait for bus to not >>>>>>> be busy. >>>>>>> >>>>>>> Reinitialise controller as otherwise operation is not stable. >>>>>>> For reference, see linux kernel commit: 9656eeebf3f1 ("i2c: Revert >>>>>>> "i2c: xiic: Do not reset controller before every transfer"") >>>>>>> >>>>>>> Signed-off-by: Tomas Melin <tomas.me...@vaisala.com> >>>>>>> --- >>>>>>> Changes in v2: >>>>>>> - Change variable declaration order >>>>>>> - Change timeout to 3ms >>>>>> Why 3mS ? >>>>> That is value used also in kernel driver. >>>> But why 3mS , why not e.g. 5mS ? >>> Quoting from comment: "for instance if previous transfer was terminated >>> due to TX error it might be that the bus is on it's way to become >>> available give it at most 3 ms to wake" >> So where did that 3 mS figure come from ? Is it from a datasheet ? Or >> the HDL ? Or is that some arbitrary number ? > > This driver is based on the kernel driver, and has the same structure as > that.
So what, Linux kernel has bugs too. > As such, it's probably a good idea to keep the same delay values here as > in the original driver unless good reason to use something else. > > As what goes for the original reasoning for 3ms, the commit history does > not mention that so I cannot comment. So would you be so kind and research this ? -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot