mru...@silveredge-gs.com wrote:
> Hi Martin,
>
> > Be advised that bad configurations of kernel and/or FPGA (or device tree\
> > info) can lead to boot loops which are pretty annoying to auto-fix.
> >
> > \--M
>
> \:-) You caught me daydreaming about automating the tedious debug I’m about
> to s
Hello Mike,
After short look at current linux-xlnx - it seems that there are not that many
changes needed for DPU to work. The driver is in one C file + C header:\
linux-xlnx/drivers/misc/xlnx_dpu.c\
linux-xlnx/drivers/misc/xlnx_dpu.h
Look at their histories. Initial addition of this driver is i
Replace the part with setting u-boot variables:
setenv jtagboot 'run netboot'\
setenv nfsroot '/nfsroot/x410’\
setenv tftproot ''\
saveenv
with this (the same variables that for ZCU111 I included in u-boot code
https://github.com/ptrkrysik/meta-ettus/commit/bddb7a9fa1a119866cddb0ea0a6706275970bc
Hello Mike,
One thing that sped up development for me regarding device-tree was ability to
reload it quickly after changes. The quickest option to load device-tree for
FPGA code is to modify related device-tree overlay, compile it manually and
reload it without restarting the device. To compile
Hello Mike,
When I did the port the most cumbersome part of it was device-tree (i.e. in
terms of troubles-per-character). Probably the one reason was that I didn’t
know all the conventions that are used there. Or maybe that some conventions
were a bit illusory and each driver had its own. So wh
Hello all,
I know the topic of triggering of transmission and reception has been recurring
here on the list over and over. But I haven’t found the answer that is good for
my case among the previous threads .
The context: I'm using USRP X410 and I’m transmitting a pulsed radar waveform.
I’m abl
Hello Maria,
If you need to run the loopback in GNU Radio - there are few hacks that are
needed. This example (author of it is Martin Braun) captures all of them and it
works with recent UHD:\
https://github.com/gnuradio/gnuradio/blob/main/gr-uhd/examples/grc/rfnoc_radio_loopback.grc
I’m using
Hello,
I ported USRP X410 code to ZCU111. As the NI/Ettus kernel didn’t work straight
away (i.e. because of device-tree and bootloader issues) I started from booting
with a linux-xlnx kernel that I had from Petalinux together with device-tree
for ZCU111.
I was able to use that kernel to some p
Hello Mike,
I don’t know what your preference regarding setup is, but for me it was crucial
to be able to make changes to the rootfs and kernel quickly and to be able to
remotely reset the device.
This was especially important when dealing with kernel and bootloader. As I
didn’t have much expe
Hello guys,
A bit in the topic of the ‘make+FPGA’ rant. I find the NI/Ettus make workflow
very usable. Have anybody (other than me) though about adapting it to usage
outside of UHD. Or maybe even someone tried to use UHD’s FPGA build system this
way?
Probably there are some other solution/hack
Hi Mike,
I can see that one thing have changed since I did that patching. At the time
most recent linux-xlnx was based on linux 5.10 and USRP X410 used 5.15.
Now the situation is different: most recent linux-xlnx is 6.6 and USRP still
uses the same kernel.
Of course you don’t have to rely on m
Hi,
Fruits aside, that was a valid question. Cause of bad performance when
combining DPDK with GNU Radio is a topic that needs to be addressed.
My hypothesis regarding the cause was:
DPDK needs few processor cores for itself only. GNU Radio runs a lot of thread
(one thread per block +) and it
Piotr Krysik wrote:
> Hello all,
>
> Has anybody tried to use DPDK with USRP X410?
>
> If yes - can you share what was maximal sample rate for a single channel
> that you were able to stream over 10G or 100G Ethernet connection
> without loss and what was your setup (hardware and software)?
I’ve
per...@o2.pl wrote:
> Hi,
>
> Fruits aside, that was a valid question. Cause of bad performance when
> combining DPDK with GNU Radio is a topic that needs to be addressed.
>
> My hypothesis regarding the cause was:
>
> DPDK needs few processor cores for itself only. GNU Radio runs a lot of
> thr
Marcus D. Leech wrote:
> On 2022-09-06 06:56, per...@o2.pl wrote:
>
> > Hi,
> >
> > Fruits aside, that was a valid question. Cause of bad performance when
> > combining DPDK with GNU Radio is a topic that needs to be addressed.
> >
> > My hypothesis regarding the cause was:
> >
> > DPDK needs few
Hi,
I can only confirm that I see the same result: 24MHz is working, starting from
about 24.5MHz there’s a lot of underruns.
My CPU: AMD Ryzen Threadripper 2990WX, 128GB RAM, motherboard Asus X399.
Best Regards,\
Piotr Krysik
___
USRP-users mailing li
per...@o2.pl wrote:
> Hi,
>
> I can only confirm that I see the same result: 24MHz is working, starting
> from about 24.5MHz there’s a lot of underruns.
>
> My CPU: AMD Ryzen Threadripper 2990WX, 128GB RAM, motherboard Asus X399.
… and the system is Ubuntu 20.04 with UHD 4.2.0.1.
___
Hello,
I would guess this question is independent of RFNoC.
Anyway even if you encrypt the bitstream you are obligated by LGPL-3 to give
user the source.
Unless you paid National dudes, who hold the copy-left, for the de-GPLed
version…
Best Regards,\
Piotr Krysik
_
per...@o2.pl wrote:
> per...@o2.pl wrote:
>
> > Hi,
> >
> > I can only confirm that I see the same result: 24MHz is working, starting
> > from about 24.5MHz there’s a lot of underruns.
> >
> > My CPU: AMD Ryzen Threadripper 2990WX, 128GB RAM, motherboard Asus X399.
>
> … and the system is Ubuntu
mamuk...@gmail.com wrote:
> Hi Piotr,
>
> \
> In this thread:
> https://lists.ettus.com/empathy/thread/JWF3VHGY3YUT62B6CDCPZ5R5PF7AUV7D?hash=MVUXQUQBPY7DS7PEZMWMYFVPFZN26YDF#MVUXQUQBPY7DS7PEZMWMYFVPFZN26YDF\
> Martin said that it could be possible to encrypt a netlist with RFNoC, so
> that’s why
Johannes Demel wrote:
> Hi all,
>
> thanks for your suggestions.
>
> A few more details:
>
> * Ryzen 5900X CPU
> * UHD reports USB 3. With USB2 it would probably fail above \~8MSps.
> * Ubuntu 22.04 with GCC 11.2, Python3.10
>
> I tried 2TX streams alone at 30.72MSps. works. check.
> I tried 2RX s
Hello,
I’ve seen on X310 that the supply power of GPSDO is controlled by FPGA pin.
Maybe there is something similar on E320.
BTW. on X310 that pin isn’t used, at least not for anything good. It changes
its state for a moment every time someone loads FPGA bitstream over PCIe
interface. Taking i
Ha!
It’s there on E320 and you can control it with device argument:
enable_gps | Enable/disable power to the GPSDO.
| N3xx, E320| enable_gps=0
Here in the table at the bottom:
https://files.ettus.com/manual/page_configuration.html
Bes
Marcus D. Leech wrote:
> On 2022-09-08 04:54, Aiden Morrison via USRP-users wrote:
>
> > Hello,
> >
> > I am attempting to do synchronized multi-site reception using USRP
> > N210 radios. Our first attempt was to make use of 2x radios with ettus
> > GPSDO modules installed, feeding the radios with
per...@o2.pl wrote:
> Ha!
>
> It’s there on E320 and you can control it with device argument:
>
> enable_gps | Enable/disable power to the GPSDO.
> | N3xx, E320| enable_gps=0
>
> Here in the table at the bottom:
>
> https://files.ettus.co
Piotr Krysik wrote:
> W dniu 05.05.2015 o 20:36, Martin Braun via USRP-users pisze:
>
> > On 04.05.2015 12:51, Piotr Krysik via USRP-users wrote:
> >
> > > Hi Martin,
> > >
> > > Do you maybe know what is the source of the problem?
> > >
> > > I remember that for example USRP N200 has a mechanism
David Raeman wrote:
> > In case you try turning off GPSDO on E320 please share info if it helps.
>
> Hi Piotr,
>
> I was able to disable the power rail for the GPSDO and confirmed it resolves
> this issue. So the problem is correlated with GPSDO activity in some way,
> even though its TCXO net i
Hello,
I just got the same error as you Meni. The reason was I had remainings of old
installation of DPDK, so I was mixing two versions.
As I wanted to use DPDK installed from packages I had to remove all traces of
DPDK from /usr/local directory.
The most important were headers (files with nam
Hello,
It seems that I have to answer my own question. Currently I succeeded to get
245.76MSamp/s in benchmark_rate for single channel with DPDK over single 10Gbit
link for an RFSoC device similar to USRP X410.
My setup:
* UHD 4.3, Ubuntu 20.04, DPDK 19.11 installed from packages
* command: b
Marcus D. Leech wrote:
> On 2022-09-16 16:25, per...@o2.pl wrote:
>
> > Hello,
> >
> > It seems that I have to answer my own question. Currently I succeeded
> > to get 245.76MSamp/s in benchmark_rate for single channel with DPDK
> > over single 10Gbit link for an RFSoC device similar to USRP X410.
Hello,
Thank you for the outstanding effort put by you and other employees of NI into
development of this free/open source software package.
Could you also share information when meta-ettus repository will be updated to
4.3 version?
Best Regards,\
Piotr Krysik
_
Hi all,
As promised in one of earlier posts I’ve written something about installation
of UHD with DPDK support.
It is not a full tutorial. It’s more an extension of what was written in
currently existing tutorials and mailing-list posts (like this tutorial:
https://files.ettus.com/manual/page_
Hello Berkay,
I tried it with signal recorder. I remember that without additional effort the
result was very disappointing.
I needed to assign blocks (with use of function *set_processor_affinity)* to
CPU cores other than the ones used for DPDK. Then it started to work better
than without DPDK
per...@o2.pl wrote:
> Hello,
>
> It seems that I have to answer my own question. Currently I succeeded to get
> 245.76MSamp/s in benchmark_rate for single channel with DPDK over single
> 10Gbit link for an RFSoC device similar to USRP X410.
>
> My setup:
>
> * UHD 4.3, Ubuntu 20.04, DPDK 19.11 i
Hello Brian,
Yes, it’s LMK04832 chip that generates clock on X410 and it is managed by the
file that you found.
I don’t have USRP X410 but I’m trying to achieve something similar on ZCU111
running ported X410 code.
I don’t know the answer regarding ZBX as I haven’t analyzed that. ZCU111
doesn
Regarding ZBX, it is important what will be final IF frequency between ADC/DACs
and ZBX and\
how close it is to the Nyquist rate for different requested frequencies.
You can try to analyze rx and tx tune-maps in zbx_constants.hpp in order to
find that out.
Best Regards,\
Piotr Krysik
__
Hello,
There might be some changes needed in the source code. I’m not sure what
exactly (maybe prc_clock_map should be changed), but it seems the configuration
for 100MHz clock multiply (3e9 sample rate) is still present in
x4xx_sample_pll.py and x4xx_reference_pll.py.
I can try build 100MHz v
Hello,
I recently experimented with adding new master clock definitions for X411 (my
port of X410 code to ZCU111).
Here is a commit that does that:
https://github.com/ptrkrysik/uhd/commit/719257702b788703e24fa8595d190c70114f5011
But the clocking chips on ZCU111 are different so from you perspe
Hello,
I meant x4xx_clk_mgr.py not
[zcu111_clk_mgr.py](https://github.com/ptrkrysik/uhd/commit/719257702b788703e24fa8595d190c70114f5011#diff-d91773ec3db6663fcee00c00022faff9981ec5902f6ae807f09f9519903fe276
"mpm/python/usrp_mpm/periph_manager/zcu111_clk_mgr.py"). The latter is
zcu111-specific\
i
Hello,
Streaming over multiple SFP+ links works for X411 currently:
https://github.com/ptrkrysik/uhd/
Best Regards,\
Piotr Krysik
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Hello,
I can see difference that could be associated with having two rx streamers
instead of one.
I have following situation:
* computer with 2x Intel Xeon Silver 4214R @ 2.40GHz,
* streaming of two 256MS/s channels through two SFP+ links using DPDK,
* both channels are stored to a single ram
Hi Wade,
After applying your trick I get data flowing to the PC!
The version of UHD that I used was 4.3.
A quick test shown that the received values are all zeros \
\- without any signal at the input and without setting proper carrier
frequency.\
I need to dig into that. But having any samples
Brian Padalino wrote:
> I am building some experimental/development FPGAs for an X410 and I am
> looking at loading them temporarily for a quick runtime test without
> committing to overwriting default images.
>
> With the X310 I am able to achieve this with a JTAG connection. With the
> X410, be
Hi,
After sending signal to the device and setting a proper carrier frequency (1GHz\
in this case) I can confirm that it works. To summarize I attach the working\
python script and screenshot of a figure that is drawn by the script.
Thank you Rob for the idea. It should be very useful for testing
jmalo...@umass.edu wrote:
> Hello,
>
> I have run into an issue when trying to synthesize the “gain” RFNoC as
> described in the tutorial here
> https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0
>
> I get an error that the module cmplx mul is locked. I found that in the
> verilog file
Hello,
Has anybody tried to use QSFP28 network adapter from intel with USRP X410 and
not Mellanox/Nvidia that is sold by NI for use with X410?
Intel cards have some advantages over Mellanox. One of them is configurability
of the QSFP28 port to act as four SFP+ or SFP28 ports. But I didn’t see
Hello,
Answering my own question: these brochures are closest to answering what I need
to know:
https://kb.ettus.com/images/f/f8/Open_Architecture_For_Radar_and_EW_Research_v1.0.pdf
www.ni.com/content/dam/web/pdfs/oarer_solution_brochure.pdf
They lists Intel E810-CQDA2 network adapter as a one
Hello,
If you succeed to run X410 together with Intel QSFP+ or QSFP28 card please let
everyone know.\
I couldn’t find information if anybody did that.
Wade Fife pointed out that someone tried with QSFP28 network adapter from Intel
but had problems:\
https://lists.ettus.com/empathy/thread/IA2YCI
Helo,
The most compact system that I use for recording with device similar to USRP
X410 (X411 based on ZCU111 eval board) is Dream Machines RX3080 laptop that has
8 core desktop CPU: 11th Gen Intel(R) Core(TM) i7-11700K. The laptop has 64GB
of RAM. As a network adapter I’m using Intel network a
Hello all,
Did anybody use USRP X410 with optical transceivers and optical fiber instead
of QSFP28 cable?
If yes - could you share model of those optical transceivers?
Best Regards,\
Piotr Krysik
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There supposed to be some list of adapters that could work with X410 here:
https://kb.ettus.com/X410#100_Gigabit_Ethernet
There is this sentence in “Guidance on SFP+ Adapters for Fiber Connectivity on
NI Ettus USRP X410“ section:
“Here are is a list of known-good cables and adapters.“
But ther
Hello Marcus,
The page was edited yesterday. A link to a list was added and now it’s clear
what it references to.
The list doesn’t include any QSFP28 optical modules (just 3m copper cable) so
the original question to the community is still valid.
Best Regards,\
Piotr Krysik
___
Hello Michelle,
If you can use burst transmission then UHD’s GPIO control interface might be ok
(you can use ATR for that).
If you need to have good control over phase difference between the pulses then
burst transmision adds additional problems and it’s easier to transmit signal
constantly wi
Hello,
The undefined **RFNOC_EDGE_TBL_FILE** macro is a typical error when you try to
build a Vivado project generated for X410.
The reason is that the macro is not passed correctly when synthesizing the
Vivado project. My workaround was to use synth_design command generated by UHD
X410 Makefi
Hello Wade,
The key is that Ryan tried to run synthesis again via Vivado gui.\
>From my experience this won’t work because some build parameters (like the
>mentioned macro definition) are passed together with synthesis command
>(synth_design).\
If there is another way to make it work other than
Wade Fife wrote:
> The MPM software on your device is older than the FPGA you're trying to
> use. Because you're using master, they haven't published updated
> filesystems with the new MPM yet, but there will be a release candidate
> very soon for UHD 4.5 you could try.
>
> Wade
>
> On Tue, Aug 22
Hello,
I used a yml file that is attached to the first message in this thread. That
YML used to work with UHD 4.3.
Wade’s version has some additional parts in descriptions of radios:\
ctrl_clock: _device_.rfnoc_ctrl\
timebase_clock: _device_.radio
and changes in clk_domains (names of clocks fro
Hello all,
RxTx loopback is a feature that was missing(/hard to do) in RFNoC before at
least 4.0.
Currently it works and there are even nice examples showing how set it up, so
one doesn’t have to figure this out. There are examples both in pure UHD
(https://github.com/EttusResearch/uhd/blob/ma
Hello Philipp,
Many thanks for creating an example how to make a grc for gain RFNoC block from
the rfnoc-example.
It works and it saved me some time.
Maybe this can be distributed somewhere (with gr-uhd?) or at least shown on
some wiki, so it could make life easier for more people in the absen
Hello,
I think I figured out what is wrong. It starts from the fact that
‘rfnoc_radio_loopback‘ example doesn’t change the decimation in the ‘DDC’ no
matter what rate is selected. This is because ‘rate‘ parameter is applied to
‘Radio‘ RFNoC block. In the end the sample rate of the stream at the
Hello all,
I found the reason of the problem and a solution that works for sample rate
lower than master clock rate (245.76MHz by default for X410).
So the root cause of the issue is that clock used for processing in the
‘rfnoc_block_gain’ is ‘rfnoc_chdr’ clock (this is set in ‘gain.yml’). This
Sorry for repetition in the last post. I suppose my two previous posts went to
moderation and there was no one to accept them during the Sunday?
I was able to connect ‘ce’ clock correctly. But changing the clock to the one
that has chance of making the ‘gain.yml’ work with decimation=1 (in ‘DDC’
Ok. I know what was stopping the RFNoC flowgraph after correction of the clock.
I was setting SPP (samples-per-packet) to a value that was somehow wrong for
this case. After removing that command-line parameter, the loopback through
‘Gain’ block started to work.
I’m posting my changed ‘Gain’ bl
Hello Martin,
Somehow I missed your reply.
In the meantime I’ve started from implementing what you described in the first
point.
If anyone is interested - it appeared that ‘keep_one_in_n‘ was a very good
starting point. I left the last state\
machine that is responsible for forming output pack
Hello All,
I’ve got an update regarding synchronization inside of FPGA between Tx and Rx
after overflows.
I’ve checked that with measurements and there was no synchronization loss
between replay block working on Tx side and our RFNoC block that selects
samples on the Rx side, which is inserted
Hello,
I didn’t make RFNoC block - just some custom module that was connected to
‘gpio_out_fabric_a’ of ‘x4xx_core_common_i’ in ‘x4xx_core.v‘:
https://github.com/ptrkrysik/uhd/commit/a6275494b173187b11205fe33b1fc937d477e9b5
That logic took LSB from imaginary part of sample and sent it to a GPIO
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