Hello all, I found the reason of the problem and a solution that works for sample rate lower than master clock rate (245.76MHz by default for X410).
So the root cause of the issue is that clock used for processing in the ‘rfnoc_block_gain’ is ‘rfnoc_chdr’ clock (this is set in ‘gain.yml’). This clock has 200MHz by default for X410.\ Taking into account that gain block processes one sample per clock cycle, rate of ‘rfnoc_chdr’ is too small to process whole stream of samples coming at the output of DDC block with decimation equal to 1. Moreover in the ‘[rfnoc_radio_loopback](https://github.com/EttusResearch/uhd/blob/master/host/examples/rfnoc_radio_loopback.cpp#L123)’ example ‘rate’ parameter is applied directly to radio rfnoc block and not to DDC. So no matter what is set there the decimation is always 1. To make it work it was necessary to change the decimation to higher value by setting a proper rate with use of the set_output_rate function of the DDC block controller. However I would like to make the example work even when there is no decimation. Therefore I tried to switch it to ‘ce’ which has rate 266.66(6)Mhz AFAIK by changing ‘control’ and ‘data’ clock domains in ‘gain.yml’ to ‘ce’. I changed also ‘noc_shell_gain.v’ and ‘rfnoc_block_gain.v’ by partially mimicking what I’ve seen in ‘moving_avg’ example. But probably I did something wrong as the design doesn’t pass timing check. So the question is how to switch ‘rfnoc_block_gain’ example to use ‘ce’ clock instead of ‘rfnoc_chdr‘ and limit possibility of a mistake? Best Regards,\ Piotr Krysik
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