Hello, I’ve seen on X310 that the supply power of GPSDO is controlled by FPGA pin. Maybe there is something similar on E320.
BTW. on X310 that pin isn’t used, at least not for anything good. It changes its state for a moment every time someone loads FPGA bitstream over PCIe interface. Taking into account that for every run of an application working over PCIe FPGA bitstream is reloaded, on each application start GPSDO is being power cycled and it has to wait for a lock for about 10 minutes. This makes GPSDO + PCIe practically useless combination. I reported the issue over a year ago but NI folks didn’t bother to respond: https://lists.ettus.com/empathy/thread/Q3DY5SEKXMQ33W6MOTU5LTUS7LMC3DH5?hash=Q3DY5SEKXMQ33W6MOTU5LTUS7LMC3DH5#Q3DY5SEKXMQ33W6MOTU5LTUS7LMC3DH5 Best Regards,\ Piotr Krysik David Raeman wrote: > This is very helpful, thanks for the response Piotr! I was starting to > speculate that maybe there is some cross-talk in the clocking front-end > switch (U55), enough to quasi-periodically perturb the PLL. I don't believe > UHD turns off the GPSDO's TCXO when the external clock is selected, so they'd > both be coming into the switch ports. This is complete speculation, but I > don't see many avenues for how the internal and external clocking paths > differ. > > Even though the E320's GPSDO cannot be removed, I can experiment with > explicitly powering it down. Thanks for the suggestion!
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