Hello, I didn’t make RFNoC block - just some custom module that was connected to ‘gpio_out_fabric_a’ of ‘x4xx_core_common_i’ in ‘x4xx_core.v‘:
https://github.com/ptrkrysik/uhd/commit/a6275494b173187b11205fe33b1fc937d477e9b5 That logic took LSB from imaginary part of sample and sent it to a GPIO line (which had to be set to **USER_APP** mode - https://files.ettus.com/manual/page_x400_gpio_api.html). I’ve been looking how to do that from RFNoC and it looked that I would have to manually edit automatically generated verilog files to connect the GPIO there (not very entertaining when you have to do that on each change of the yaml flowgraph). However, the documentation seemed to suggest also possibility of connecting verilog’s wires in the yaml files. I would imagine that this would work this way: create some input for RFNoC block with unique name and connect it to some wire that would be connected to i.e. ‘user_app_in_a’. After that in the generated verilog those would be connected together. That would be much better solution. But I never tried it. Does anyone have experience with this? Or was I wrong getting impression it might be possible? Best Regards,\ Piotr Krysik
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