Hello Mike,
It’s good that you have experience with tftpboot, because the paths in
my description are a bit wrong. I meant to put everything in /tftpboot
directory for simplicity but then written /tftpboot/x410 - like I have
it. So this is a mistake and ‘/tftpboot/x410’ should be replaced by
ompatible ones. So you'll be able to build the kernel with any
manual modifications that you make.
Best Regards,
Piotr Krysik
W dniu 10.10.2024 o 18:41, mruane--- via USRP-users pisze:
Hi Piotr,
I’m really glad you mentioned xlnx_dpu.c and xlnx_dpu.h. I found those
a few days ago (in th
W dniu 11.10.2024 o 15:19, Martin Braun pisze:
On Fri, Oct 11, 2024 at 6:13 AM Piotr Krysik wrote:
Regarding ‘kas’ command - that works well with the ‘zeus’ branch of
meta-ettus (used up to UHD 4.6). But when I switched to more recent
‘kirkstone’ branch - it stopped. Probably
reloading FPGA code when PCIe is used, without
changing UHD source?
--
Best Regards,
Piotr Krysik
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runs of the device?
Best Regards,
Piotr Krysik
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Hello all,
Has anybody tried to use DPDK with USRP X410?
If yes - can you share what was maximal sample rate for a single channel
that you were able to stream over 10G or 100G Ethernet connection
without loss and what was your setup (hardware and software)?
--
Best Regards,
Piotr Krysik
get constant losses of packets for streaming rates above ~25MS/s (for
10Gb link). Probably I still didn't try hard enough ;).
Best Regards,
Piotr Krysik
W dniu 28.07.2022 o 14:05, meni.d...@sabra-microsystems.com pisze:
Hi
I use UHD version 4.2 and x410.
So far, I have been using DP
0
Best Regards,
Piotr Krysik
W dniu 16.06.2022 o 13:09, Chang, Kaixin pisze:
Dear all,
I have a DPDK initiation problem
I installed DPDK19.11 with apt install and install UHD4.2 from source
and in the uhd.conf file I wrote the dpdk driver path as
dpdk-driver=/usr/lib/x86_64-linux-gnu
th
DR
SDRAM controller module,
2. I removed implementation of one of Ethernet ports (in order to get
quicker builds in Vivado) but its end-point was left in the RFNoC graph.
So it was probed during initialization but there was nothing that could
respond.
Best Regards,
Piotr Krysik
W dniu 06.09.
device.
Best Regards,
Piotr Krysik
W dniu 02.09.2022 o 17:21, David Raeman pisze:
Hi all,
I'm working on a project that involves modeling an incoming signal's
phase as a stochastic process, and I'm seeing a weird phase artifact
on the E320. It looks like a slow periodic phase
t packets. And that's all. Only
first interface receives samples.
Best Regards,
Piotr Krysik
W dniu 15.06.2022 o 17:17, Tillson, Bob (US) via USRP-users pisze:
So I am on the x4_200 image and am wondering what the “correct” way to
setup the transport is.
I currently have a single qsfp
fferent clock rate
('radio' clock)
but without success.
--
Best Regards,
Piotr Krysik
#!/usr/bin/python3
import uhd
import numpy as np
master_clock_rate = 256e6
fft_size = 256
graph = uhd.rfnoc.RfnocGraph("addr=192.168.10.2,master_clock_rate=256e6")
sa = uhd.usrp.StreamArgs(&q
any ideas how to solve the issue other than returning the
device?
--
Best Regards,
Piotr Krysik
W dniu 19.05.2023 o 15:41, Arjan Feta via USRP-users pisze:
Hi Wade,
Coincidentally I just measured the output voltage of the power supply
and found that the three of them wobble around 8 to 9 v
Hello,
For X410 the network adapter which works under DPDK driver control can't
be used to control the device (it can't carry RPC calls to MPM daemon
working on the device). You need a separate Ethernet connection for
mgmt_addr. You can use 1Gbit Ethernet link for that.
Best Rega
ables with following command:
source /opt/oecore-sdk/environment-setup-aarch64-oe-linux
Best Regards,
Piotr Krysik
W dniu 3.01.2025 o 00:27, Marcus D. Leech pisze:
On 02/01/2025 13:56, Sakthivel Velumani wrote:
Hi Marcus,
Thanks for the pointers. I am looking to offload all the DSP work to
the R
dilv
Here is the result seen on an oscilloscope connected to RF-A RF2 and
GPIO pin number 3 (configured to switch to "1" when transmitting) of a
USRP X310: http://imgur.com/a/hHO5I
The yellow line is GPIO pin and the blue line is signal coming out of
the RF port.
Best R
of them as there are
many valid tasks that require both GPSDOs and good quality of signal
signal phase measurement. I still have to check if the same thing
happens without Octoclock-G.)
(in the next episode: slow start of transmission in USRP B210 :) )
--
Best Regards,
Pi
happen to have board mounted GPSDOs in all
USRPs B210 that we have, but in this example they were not used for
synchronization.
--
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W dniu 21.09.2017 o 19:16, Piotr Krysik via USRP-users pisze:
> W dniu 21.09.2017 o 17:19, mle...@ripnet.com pisze:
>> You talk about board-mounted GPSDOs in each of your B210s, but then
>> talk about using an Octoclock-G.
>>
>> In the Octoclock-G example, you are exp
W dniu 21.09.2017 o 21:06, Marcus D. Leech via USRP-users pisze:
> On 09/21/2017 02:27 PM, Piotr Krysik via USRP-users wrote:
>>
>> --
>> Piotr Krysik
>>
>>
>> Also take into account that I'm not comparing phase signals observed by
>> two differ
nges with time. When I will know more I will
describe it in a new thread on the mailing list.
Best Regards,
Piotr Krysik
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it faster (100x faster definitely
would make burst api in B210 much more usable).
(UHD used for the test was 3.9.2, carrier frequency of the signal was
940MHz)
--
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Piotr Krysik
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http://
amplifier. It might mean for example that every time there is
start of transmission ad9361 chip is restarted. If yes it might be worth
to fix this as UHD's burst mode might not be the only victim of this
approach.
Best Regards,
Piotr Krysik
W dniu 24.09.2017 o 05:56, Dario Fertonani pisze:
Hi all,
For comparison: screenshot of much more "civilized" behavior of USRP
X310 in the same situation.
Best Regards,
Piotr Krysik
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ork fine as well.
> Kent Torell
So you might be right here Kent that it was the path to the ground in the
attenuator that
changed how the output behaves. It is funny thought that the problem
only appears when RX2 port on the same side of B210 is also used :).
--
Best Re
W dniu 27.09.2017 o 07:06, Piotr Krysik via USRP-users pisze:
> Hi all,
>
> I narrowed down when the issue occurs.
>
> When using separate sides of B210 for transmitting (i.e. TX/RX port on
> RF A side) and receiving (i.e. RX2 port on RF B side) everything is fine and
> B21
W dniu 06.10.2017 o 21:33, Piotr Krysik via USRP-users pisze:
> Hello everyone,
>
> I synchronized two USRPs B210 with use of Octoclock-G and the attached
> gnuradio-companion flowgraph.
>
> I've connected signal generator generating sinusoid to both devices (it
> was o
fference. Even for transmit gain 0 the problem persists.
I have a feeling that the answer to the question might be easier to find
if we know what is state of TX/RX switches before start of burst and
after it.
Best Regards,
Piotr Krysik
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W dniu 06.10.2017 o 23:22, Marcus D. Leech via USRP-users pisze:
> On 10/06/2017 03:47 PM, Piotr Krysik via USRP-users wrote:
>> W dniu 06.10.2017 o 21:33, Piotr Krysik via USRP-users pisze:
>>> Hello everyone,
>>>
>>> I synchronized two USRPs B210 with
W dniu 09.10.2017 o 09:36, Piotr Krysik via USRP-users pisze:
> One thing that helped was replacing one of the USRP B210 in the pair
> with another one.
Hi,
I checked everything again and I found out that after replacing one of
my 10MHz ref SMA cable the phase difference between any d
W dniu 09.10.2017 o 10:46, Piotr Krysik via USRP-users pisze:
> W dniu 09.10.2017 o 09:36, Piotr Krysik via USRP-users pisze:
>> One thing that helped was replacing one of the USRP B210 in the pair
>> with another one.
> Hi,
>
> I checked everything again and I found out
generator as a laboratory equipment.
Best Regards,
Piotr Krysik
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RFNOC UHD (3.9.6) everything works fine.
What is a bit strange is that txrx_loopback_to_file UHD example works
fine for all versions of UHD.
Is anybody here able to run GNU Radio flow-graphs with simultaneous tx
and rx on X310 with RFNOC UHD and without underflows?
Best Regards,
Piotr K
W dniu 22.10.2017 o 12:04, Piotr Krysik via USRP-users pisze:
> Hi all,
>
> I'm prepared a basic GNU Radio flow-graph that does simultaneous
> transmission and reception (see the attachment). For USRP X310 and RFNOC
> UHD (version above 3.10.x) soon after starting the flow-gr
ow what is
causing this and if it can be corrected with a firmware change (I'm not
actively looking for the cause currently).
Best Regards,
Piotr Krysik
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W dniu 13.11.2017 o 11:36, Piotr Krysik via USRP-users pisze:
> Dear list,
>
> Little update on transmitting bursts and simultaneous receiving with
> USRP B210. When I connect anything that has some path between TX/RX SMA
> port's body and inner female sleeve contact (like 3d
at time offsets were observed, issue of
synchronizing B210s is still open and not solved.
***
--
Best Regards,
Piotr Krysik
W dniu 25.10.2017 o 08:59, Hideyuki Matsunaga via USRP-users pisz
dniu 23.01.2018 o 19:11, Martin Braun via USRP-users pisze:
> On Thu, Jan 18, 2018 at 10:34:14AM +0100, Piotr Krysik via USRP-users wrote:
>> Hi Hideyuki,
>>
>> Our students were working (with my help) on synchronizing two USRPs B210
>> with use of Octoclock-G.
>&g
W dniu 22.02.2018 o 23:37, Marcus D. Leech via USRP-users pisze:
> On 02/22/2018 09:15 AM, Piotr Krysik via USRP-users wrote:
>> Hi all,
>>
>> There was a thread on this topic started by Hideyuki Matsunaga that
>> didn't resolve this question.
>>
>> I w
W dniu 24.02.2018 o 23:10, Marcus D. Leech via USRP-users pisze:
> On 02/24/2018 04:27 PM, Piotr Krysik via USRP-users wrote:
>> Hi Marcus,
>>
>> Ad.A I doubted it as the time reported by both USRPs at the end of
>> synchronization function is about ~0.005 s. Anyway
W dniu 25.02.2018 o 11:16, Piotr Krysik via USRP-users pisze:
> W dniu 24.02.2018 o 23:10, Marcus D. Leech via USRP-users pisze:
>>
>> What if you use the time-stamps on the streams to time-align, and THEN
>> cross-correlate?
>>
>> Remember that multi-usrp do
W dniu 25.02.2018 o 20:08, Marcus D. Leech via USRP-users pisze:
> OK, so (and apologies if this was in your previous data) what is the
> average magnitude of the time discrepancy?
Usually it was about few hundreds us (random). I will try to perform
more measurements.
_
W dniu 26.02.2018 o 11:29, Piotr Krysik via USRP-users pisze:
> W dniu 25.02.2018 o 20:08, Marcus D. Leech via USRP-users pisze:
>> OK, so (and apologies if this was in your previous data) what is the
>> average magnitude of the time discrepancy?
> Usually it was about few h
W dniu 26.02.2018 o 12:43, Piotr Krysik via USRP-users pisze:
> W dniu 26.02.2018 o 11:29, Piotr Krysik via USRP-users pisze:
>> W dniu 25.02.2018 o 20:08, Marcus D. Leech via USRP-users pisze:
>>> OK, so (and apologies if this was in your previous data) what is the
>>&g
W dniu 26.02.2018 o 17:22, Marcus D. Leech via USRP-users pisze:
> On 02/26/2018 09:16 AM, Piotr Krysik via USRP-users wrote:
>> W dniu 26.02.2018 o 12:43, Piotr Krysik via USRP-users pisze:
>>> W dniu 26.02.2018 o 11:29, Piotr Krysik via USRP-users pisze:
>>>> W dni
Hi Hideyuki,
For the solution look at the end of "Is it possible to time synchronize
multiple USRPs B210?" thread.
I attached there a working example for two USRPs B210.
--
Best Regards,
Piotr Krysik
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W dniu 26.02.2018 o 19:44, Marcus D. Leech via USRP-users pisze:
> On 02/26/2018 01:36 PM, Piotr Krysik via USRP-users wrote:
>>
>> It's hard for me to understand why only one of the devices changes the
>> master clock rate at that moment. This seems a bit arbitrary. It w
3. If not - does it make sense to try to reuse UHD transports for the
described purpose? Maybe there exists something more universal or maybe
it's better to do it from scratch?
--
Best Regards,
Piotr Krysik
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U
Hi Keith,
If I manage to make it anything more than just a cool idea, the code
definitely will be available publicly.
Best Regards,
Piotr Krysik
W dniu 08.11.2018 o 17:18, Keith k pisze:
> Hello Piotr
>
> I can't answer your question, but I'm wondering if you plan to make
chain and there are switches on UBX/SBX/WBX/etc that
select to which of these ports this Rx chain is connected.
As Fabian has written there are TwinRX daughter cards, each with two Rx
chains, that you can use on a USRP X310 to have 4 receivers.
Best Regards,
Piotr Krysik
W dniu 13.11.2018 o
y_uncal
===
The calibration factor factor 'c' will be true for some particular
frequency range (how wide depends on the frequency response of the
receiver) and at some range of input signal power. It depends also on
temperature and many other variables.
Best Regards,
Piotr Krysi
n't seem to have this positive
effect.
--
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Piotr Krysik
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lock" block. I don't have N310 and I know that reality can be
a bit far from expectations (i.e. look at my "What makes sense and what
doesn't in the way carrier frequency is set for TwinRX currently?" post).
But maybe the daughterboards can be configured to use that referenc
se timed commands to set the frequencies on Rx and Tx side
synchronously (if you use UBX or SBX daughter-boards).
Best Regards,
Piotr Krysik
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Hi Dominik
W dniu 18.03.2019 o 10:49, Patscheider, Dominik pisze:
> Hi Piotr Krysik,
>
> I wanted to achieve an stepped OFDM Radar.
> To increase the baseband for the radar, I´m splitting the subcarrier and
> transmit them on four center frequencies.
> Thus it sends the f
you are able to
send posts to the mailing-list.
I can even see your post from two days ago (without its subject however).
--
Best Regards,
Piotr Krysik
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it.
So it seems the strange behavior of phase in signal coming from TwinRXes
might be a result of a bug that Nate was informing about.
--
Best Regards,
Piotr Krysik
W dniu 13.03.2019 o 14:48, Piotr Krysik via USRP-users pisze:
> Hello everyone,
>
> TwinRXes requires special treatment when
ld be best to
know: where these phase jumps for different frequencies come from?
Best Regards,
Piotr Krysik
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W dniu 03.04.2019 o 10:34, Piotr Krysik via USRP-users pisze:
> Hi all,
>
> I'm trying to do calibration of phase offsets between TwinRX channels.
>
> Configuration of X310 is following: two TwinRX'es, all sharing LOs from
> fist channel of the second TwinRX.
>
ug was exactly? GNU Radio didn't configure
LO-Sharing the way it was specified?
--
Best Regards,
Piotr Krysik
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is,
> as all LOs are driven from a common 200 MHz reference clock.
>
Do you mean TwinRXes might have similar initial phase reset capability
that UBXes and SBXes have?
--
Best Regards,
Piotr Krysik
> Best regards,
> Fabian
>
> Am 03.04.2019 um 12:05 schrieb Piotr Krysik via USR
To answer my own question:
https://github.com/EttusResearch/uhd/blob/master/CHANGELOG#L226
it seems the answer is yes.
--
Piotr Krysik
W dniu 03.04.2019 o 12:34, Piotr Krysik via USRP-users pisze:
> Hi,
>
> W dniu 03.04.2019 o 12:15, Fabian Schwartau via USRP-users pisze:
>> (
causing the issue described in the
first post of this thread?
--
Best Regards,
Piotr Krysik
W dniu 03.04.2019 o 12:15, Fabian Schwartau via USRP-users pisze:
> Hi,
>
> yes, the result for multiple measurements (start ups of the system) at
> a single frequency was different by multiples
If you are interested I can post it somewhere.
What seems different from situation here is that for us it seemed the
effect wasn't depending on frequency (but I didn't do any extensive
tests and might not remember).
--
Best Regards,
Piotr Krysik
W dniu 07.04.2019 o 03:00, Freedman, Michae
com/s/xfpwro8wybog4f1yo1l6yh665tg4sx0r
First you run:
./record.sh
then:
./show_figures.m
(you need to have octave installed for the second script).
Best Regards,
Piotr Krysik
W dniu 08.04.2019 o 18:30, Michael R. Freedman pisze:
> That would be wonderful if I could get your scripts to run.
>
>
> Thanks a b
diagram of
TwinRX there doesn't seem to be any circuit that might do such changes
of the LO phase. Maybe something in the FPGA. I'm puzzled...
Best Regards,
Piotr Krysik
W dniu 04.04.2019 o 23:00, Rigney, Kevin E via USRP-users pisze:
> Pitor:
>
> We've seen a similar issue
Hi Nicola,
I just had exactly the same issue with UHD 3.14.0.0-72. Upgrading to
full 3.14 release of UHD (top of UHD-3.14 branch) solved the issue for me.
Best Regards,
Piotr Krysik
W dniu 04.02.2019 o 14:42, Michailow, Nicola via USRP-users pisze:
>
> Hi,
>
>
>
> I am t
e and not break AD9361 or ADF4001 or any other chip on B210?
2. If not - do you know what other circuit modifications might be needed?
3. Does anyone have experience with adjusting VCTCXO frequency though
AD9361 DAC (this is probably question to B210 designer)?
Best Regards,
Piotr K
ed to the FPGA, intended for
controlling VCTCXO. I need to learn how to control it.
--
Best Regards,
Piotr Krysik
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just this one but I suppose
the issue might be common to motherboards that have the same components
(i.e. PCIe controller or bridge) as this one. I'm attaching the result
of lspci.
Kailash, can you attach yours (and anyone who's got the same issue)?
Maybe we'll find a common elem
e bridge sold by Broadcom. I don't know yet if it has anything to do
with USRP connection.
Best Regards,
Piotr Krysik
W dniu 23.07.2019 o 11:26, Piotr Krysik via USRP-users pisze:
> Hi all,
>
> I have the same issue. I've checked everything in different computer
> (disk with p
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