sers@lists.ettus.com
Subject: Re: [USRP-users] USRP-users help needed
Hi Joseph,
to avoid confusion, I'll directly comment within your text:
On Thu, 2018-03-01 at 16:03 +, Stern, Joseph via USRP-users wrote:
I wanted to gain a general understanding of the process,
specific to our B200mini
Hi Joseph,
to avoid confusion, I'll directly comment within your text:
On Thu, 2018-03-01 at 16:03 +, Stern, Joseph via USRP-users wrote:
> I wanted to gain a general understanding of the process,
> specific to our B200mini hardware, so my approach understandably
> seems like the Y and not the
lists.ettus.com]
Sent: Wednesday, February 28, 2018 5:37 PM
To: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] USRP-users help needed
On 02/28/2018 12:06 PM, Stern, Joseph via USRP-users wrote:
I have a couple specific questions I am hoping someone can answer, after this
FYI:
I finally fou
---
*From:* USRP-users [usrp-users-boun...@lists.ettus.com] on behalf of
Stern, Joseph via USRP-users [usrp-users@lists.ettus.com]
*Sent:* Wednesday, February 28, 2018 8:28 AM
*To:* usrp-users@lists.ettus.com
*Subject:* Re: [USRP-users] USRP-users help needed
Thank you all for your help. I hav
f of Stern,
Joseph via USRP-users [usrp-users@lists.ettus.com]
Sent: Wednesday, February 28, 2018 8:28 AM
To: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] USRP-users help needed
Thank you all for your help. I have been going through both the FPGA and
host-side driver code for the B200mi
ubject: Re: [USRP-users] USRP-users help needed
On 02/26/2018 12:07 PM, Stern, Joseph via USRP-users wrote:
Dear USRP users:
We have been trying to understand the low-level details of the USRP
architecture (namely, for the B200mini); there seems very little explicit
insight provided on the
Hello Joe,
The source code for both the driver and FPGA HDL are hosted on GitHub. Here
are links to them:
https://github.com/EttusResearch/uhd
https://github.com/EttusResearch/fpga
The manual has a short section about sample rate options:
http://files.ettus.com/manual/page_general.html#general_sa
On 02/26/2018 12:07 PM, Stern, Joseph via USRP-users wrote:
Dear USRP users:
We have been trying to understand the low-level details of the
USRP architecture (namely, for the B200mini); there seems very little
explicit insight provided on the Ettus web site into how decimation is
perform
Dear Joe,
All the FPGA Verilog code is available in the Github Repo:
https://github.com/EttusResearch/fpga I believe the B200mini falls within
the USRP3 category.
And about the decimation itself, after a quick search through the repo
folders I found a DSP block that seems to indicate decimation i
Dear USRP users:
We have been trying to understand the low-level details of the USRP
architecture (namely, for the B200mini); there seems very little explicit
insight provided on the Ettus web site into how decimation is performed in the
FPGA (and commanded from the driver side). I also
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