Hello,
I didn’t make RFNoC block - just some custom module that was connected to
‘gpio_out_fabric_a’ of ‘x4xx_core_common_i’ in ‘x4xx_core.v‘:
https://github.com/ptrkrysik/uhd/commit/a6275494b173187b11205fe33b1fc937d477e9b5
That logic took LSB from imaginary part of sample and sent it to a GPIO
Hi Alex,
I know that Ettus Research is aware of this and it's being looked at as a
possible feature. In the current version of UHD, you still have to make
manual changes to the FPGA to access the GPIO from RFNoC. The changes
aren't particularly difficult, but it can be intimidating if you're not
f
I'm working on the same thing, so yes this would be super useful.
Does Ettus Research have any update on that GitHub issue #666?
Here's the link again:
https://github.com/EttusResearch/uhd/issues/666
Sincerely,
Alex-M-Humberstone
PhD Student
Klipsch School of Electrical Engineering
New Mexico S
Hi,
this is currently not possible without changing the UHD core manually
and re-routing those GPIO lines in the Verilog core code. Some years ago
I opened a feature request, it contains some hints on what others tried
and what would be required. Unfortunately, I never got an answer.
Would b
