I'm working on the same thing, so yes this would be super useful. Does Ettus Research have any update on that GitHub issue #666?
Here's the link again: https://github.com/EttusResearch/uhd/issues/666 Sincerely, Alex-M-Humberstone PhD Student Klipsch School of Electrical Engineering New Mexico State University (NMSU) Las Cruces, New Mexico, 88003 alex.m.humberst...@gmail.com https://ece.nmsu.edu/ On Mon, 3 Feb 2025 at 02:15, Philipp Niedermayer <p.niederma...@gsi.de> wrote: > Hi, > > this is currently not possible without changing the UHD core manually > and re-routing those GPIO lines in the Verilog core code. Some years ago > I opened a feature request, it contains some hints on what others tried > and what would be required. Unfortunately, I never got an answer. > > Would be wonderful if you could support that by voting on the issue and > express your interest there. Or if you manage to get it working, share > your solution with a PR. > > Here is the link: https://github.com/EttusResearch/uhd/issues/666 > > Best regards > Philipp > > > Am 3.2.25 um 9:00 schrieb meni.d...@sabra-microsystems.com: > > > > Hello, > > > > I need to establish direct routing between the USRP X410's front panel > > GPIO pins and custom RFNoC blocks. > > > > Specifically, I want to read the GPIO signals directly into my RFNoC > > block. > > > > Does anyone have experience implementing such direct GPIO-to-RFNoC > > connection on the X410? > > > > Any examples or technical documentation would be helpful. > > > > Thanks > > > > > > _______________________________________________ > > USRP-users mailing list -- usrp-users@lists.ettus.com > > To unsubscribe send an email to usrp-users-le...@lists.ettus.com > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
_______________________________________________ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
