After removing the lines you mentioned it seems it is now able to return
successfully…
`sudo uhd_find_devices --args
"addr=192.168.10.2,second_addr=192.168.20.2,mgmt_addr=192.168.1.184,use_dpdk=1"`
`[INFO] [UHD] linux; GNU C++ version 9.4.0; Boost_107100; DPDK_19.11;
UHD_4.5.0.HEAD-0-g471af98f
Hello,
I am currently getting the following error when I try to run dpdk…
`net_mlx5: port 1 empty mbuf pool`
`net_mlx5: port 1 Rx queue allocation failed: Cannot allocate memory`
I am wondering if anyone has gotten a similar issue and how they fixed it. I
double checked my uhd.conf and made su
Hello,
I am wondering if it is possible to allow another host device to start a
session with an x410 after it already has a session with a different host
device. In other words, multiple devices sharing one USRP device at the same
time.
I know it is possible to “hijack” a session to perform so
Increasing the ring buffer size does not seem to help either, or at least does
not clear up the issue entirely, but I will keep the buffer size at its maximum
(8192) for now. Same goes setting governing to “performance”
I forgot to add in my previous email that occasionally, (this does not alway
Hello,
I currently have an application where I am burst receiving(about 80 micro per
milli second) with the ettus X410 at the full sample rate across 4 channels. I
am getting occasional issues where data is dropped (terminal messages show “D”
error). I have been able to get DPDK to work but tha
I was able to get the replay block to fully record by sending a small number of
samples at a time with rest in between. Now, I can’t get the radio block to
receive (no green led indication), but for now I am going to assume that is
probably a separate issue.
_
It seems like the issue has come back, which is a bit strange.
Is there a way natively in the UHD software to send samples to the replay block
without dpdk then recieve samples with dpdk? If so, how? In my application the
replay and radio block plays continuously.
___
I tried removing the RJ_45 port as the mgmt_addr and that seemed to do the
trick.
So now, I have 1 QSFP port used for mgmt and data, and the other QSFP port just
for data.
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Hello,
I currently have a custom CG_400 image where I utilize the replay block. When I
run my application without dpdk on, data is successfully written to the DRAM
and played back. However, if I use the same image and same application, but I
turn on DPDK, the application stalls while data is be
I should have updated this chain a bit ago. But I managed to solve the issue a
few days ago.
I managed to get it to work and there is a few things that went wrong that when
I fixed the problem was solved…
It is mentioned in the tutorials that the “uhd.conf” file needs to specify
exactly the am
Hello,
I am currently trying to use DPDK, however, there is an error I currently am
unable to resolve.
`./benchmark_rate --rx_rate 245.76e6 --rx_channels 0 --tx_rate 245.76e6
--tx_channels 0 --args "addr=192.168.10.2,use_dpdk=1"`
`[INFO] [UHD] linux; GNU C++ version 9.4.0; Boost_107100; DPDK_1
After reading through the documentation again, I learned I should only specify
the NIC ports used in the UHD arguments in my conf file, I believe this was
able to resolve some of my issues, it still does not successfully begin the
benchmarking. For example, if I specify 1 management_address/mgm
I tried the command without use_dpdk=1, and it worked fine(aside from the
underflows and dropped samples) - if that is what you mean by side-step.
If I specify the type/product(and set use_dpdk=1), I still get errors.
`./benchmark_rate --rx_rate 491.52e6 --rx_channels 0 --tx_rate 491.52e6
--tx_
In the past when I collected data from the x410 without DPDK, it would work
just fine to use solely 1 network port.
I tried using the management address now, but I still get errors, but it is
slightly different. Notably there is not a “no chdr_connection available” error.
`./benchmark_rate --rx
Hello,
I am currently attempting to benchmark the x410 with the Mellanox ConnectX-5
PCi Card over QSFP with the CG_400 image currently loaded on the x410. I am
currently using a 13th gen intel i9-13900KS on the host machine. I currently
have a QSFP cable connected between the Mellanox card and
Hello,
After trying to change the bitstream image from CG to X4 using
uhd_image_loader, I was met with the following error, and then the x410 got
caught in a bootloop…
`[ERROR] [UHD] An unexpected exception was caught in a task loop.The task loop
will now exit, things may not work.rpc::timeout
The boot loop occured again after trying to load a new image
I tried following the same steps as before. But even after reflashing, I still
get caught in a boot loop.
I want to power cycle the device, but before I unplugged the power supply, I
noticed LED 1 to be solid green, which I believe me
I managed to figure out how to ssh over RJ-45 and QSFP overnight, there was an
issue with networking on my host device.
Last night, The RJ-45 and QSFP has solid green LED light. I am still not sure
why the addresses of QSFP are not defaulting to the addresses listed in their
respective network
I can not ping the non-working device even, either through RJ-45 or the SFP
port. To be clear, everything I am doing to network into the non-working device
is through console JTAG. Before this problem started, I was able to ssh into
the processing system(Embedded linux) through either RJ-45 port
I do have access to two x410s. The bitstream I tried to upload on this
currently none working device was CG bitstream, when prior to this it was an X4
bitstream. Im obviously hesitant to try something similar on the working device
right now, but my current guess right now is that ssh is not star
Previously I was unable to log into linux due to the boot loop. However, after
reflashing the eMMC with the
filesystem(https://kb.ettus.com/USRP_X410/X440_Getting_Started_Guide#Flashing_the_eMMC)
I am able to now log into linux, but only through Console JTAG
I can NOT however, log in via SFP or
I was eventually able to resolve the “\[FAILED\] Failed to start File System
Check on Root Device.” using fsck tools.
I still am not able to ssh into the x410 however. The addresses to not
automatically change to the default values(i.e sfp0 = 192.168.10.2), and
manually changing them does not a
After reflashing the eMMC, boot is no longer on loop, and I am able to log in
via Console JTAG. However, I cant seem to ssh into the device of ethernet or
SFP.
I get the following error in boot…
\[FAILED\] Failed to start File System Check on Root Device.
See 'systemctl status systemd-fsck-roo
Hello,
I recently tried to update the x410 FPGA over SSH. However, I was met with a
strange error, and now when I try to log into the x410, even over console JTAG,
I am unable to. It appears the x410 is caught in a reboot loop.
Below is the message I got when trying to update the x410.
\[ERROR
Using the following steps you mentioned helped display logs.\
`systemctl stop usrp-hwd`\
`usrp_hwd.py -vv`
However, I am a bit confused about the configuration files. I was not able to
find an mpm.conf file for the x410. The closest thing I found seems to be the
usrp-hwd.conf file, but adding th
I am changing the variable host side(i.e through adding the variable in
bashrc). I am assuming this would propagate the variable to the MPM as well.
If the MPM logs use a separate variable, what should I do to adjust its
logs(adding similar environment variables to the x410 did not work)?
Thank
Hello,
I am currently trying to change the UHD logging settings, however, it seems
that when I adjust my environment variables, the new environment variable does
not propagate to all logs, specifically, it seems it does not change the log
level on the MPM side.
For example, if I adjust the log
Hello,
I am currently working on trying to print the calibration coefficients of the
RFDC after calibration of the x410. Similar to calling get_cal_coefs from the
mpm_shell.
My plan is to hijack the MPM shell within my current acquisition script, then
execute the get_cal_coefs function. Howeve
Thanks for the insight. I was under the impression that the MPM was completely
host-side.
So if I am understanding correctly, When the radio block is instantiated, the
x410 calls the host side for the RFDC initialization?
And additionally, and I am not sure if this is the “right” way to think a
\
Hello,\
My application requires that I edit the RFDC applications, however, I am
confused about how the UHD C++ API interfaces with the RFDC on the RFSoC.\
It appears when I make the RFNoC graph, the namespace x400_radio_control_impl
is called, which starts the process of programming the RFDC a
We have contacted them now. Then are much less than 3 years old.
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Hello,
That was my initial guess, but now the problem has “upgraded” from red LEDs to
LEDs that are off. I was talking with my lab group and they said they had the
red LED state in the field before, but giving the power connector a gentle
wiggle, it turned green and they were able to use the x4
Hello,
My x410 has a red power button led. The docs say this is a “power error” state,
but it does not describe what to do further. Does anyone know how to recover
the device.
Thanks
Joe
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Hello,
I am currently trying to double the sample rate of the RFDC, whilst getting rid
of Q data. Presumably, this allows me to have a very similar architecture to
the X4_400 image, and thus would not have to change the master clock rate or
increase the CHDR width above 128 bits.
It seems the
Hello,
I am currently trying to update the FPGA on the ettus, but I am getting the
following error
mirsl102b@mirsl102b-Legion-T7-34IMZ5:\~/workarea/august_bitstreams/sep5$
uhd_image_loader --args type=x4xx,mgmt_addr=192.168.10.2,fpga=X4_200
`[INFO] [UHD] linux; GNU C++ version 9.4.0; Boost_10
Thanks for the link.
Another question, does one QSFP port alone support 100 Gb streaming, and if so,
when I compile the x410, does that just entail using the x410_CG_400 option
alone for compiling or are there other considerations?
Thanks
Joe
___
USR
Hello,
We are shopping around for a new host computer to stream data off an x410 with
100 Gb/s. We could not find any PC recommendations on the x410 website. Does
anybody here have any prebuilt recommendations or bought parts separately. Any
recommendations is much appreciated
Thanks,
Joe
___
Hello,
I have an application where I need my logic within the FPGA to access the gps
time. According to the spec sheet, the x410 has a gps module built in. I would
like to get gps time from it, but it is unclear where I can get it from.
I assume the gps time is stored in radio_time inside the
I was reading the metadata to check for a overflow (similar to the examples).
Is there a way to check specifically what block is giving an overflow? I only
know how to check if there is an overflow.
I was able to increase the overall data rate without overflow by increasing
PYLD_FIFO_SIZE of th
Increasing PYLD_FIFO_SIZE does in fact allow me to increase the burst size
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I assume it occurs between my custom block and the SFP. Is there a way to tell
exactly which block it occurs at using the software?
At a high level, my current network goes… ADC -> Radio -> CHDR_crossbar ->
Custom Block -> Rx_streamer
My custom block has its s_axis_tready signal hooked up to th
For my application, I am not collecting samples continuously. The radio block
is commanded to stream continuously, but I have a custom block downstream which
“gates” samples in bursts that pass through. I am able to at least stream data
without any overflows as long as the number of samples the
Yes, the YAML file is set to 128 chdr_width. I am using v4.4.0.0
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Hello,
I am currently running into buffer overflows with the x410 where I am unable to
stream for data rates larger than \~0.32 Gb/s when the CHDR_W is 128. However,
if I stream using a CHDR_W of 64, I am able to push the data rate much
higher(at least 3.2 Gb/s). I compiled a custom image using
Hello,
When I maximize the Gain on the my board, but keep the input into the receive
at 14 dBm, I “saturate” my ADC, however, I get huge peaks(greater than the
frequency I am transmitting at) in other parts of my frequency spectrum, which
I believe to be an artifact of the LO leakage. When I ke
Hello,
I am curious about the maximum voltage that can be applied to the x4xx Antenna
receive port. On the X410 Getting Started guide, it says
“Never apply more than +14 dBm continuous <=3GHz, +17 dBm continuous >3GHz, or
+20dBm more than 5 minutes >3GHz of power into any RF input.”
And
“Alwa
In my experience, getting UHD to run on Ubuntu 22 is a huge hassle. If you can,
I recommend downgrading to 20.04(but no lower) and it should install fairly
easily.
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Hello,
I am currently working on receiving for a 500 Mhz sampling rate with a custom
block on the x410. However, I am unsure how to address the larger CHDR width,
which does not seem to be handled in the example blocks provided.
To create my custom block, I started with the example provided “Ke
It ended up being the case that the project was being built with wrong file,
and the ACK wire was set exclusively to 0.
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Hello,
I am currently trying to build an image with a 500 Mhz sampling rate with a
custom block. However, I get the following error.
`[ERROR] [RFNOC::GRAPH] Caught exception while initializing graph: RfnocError:
OpTimeout: Control operation timed out waiting for ACK.`
I do “tamper” with the ch
I have tried the changes I made above(both with the srcport clock set to
radio_2x and just radio on the custom block “trigger”). Transmission from the
Replay block to the Radio block seems to work fine. However, receiving from the
Radio block to my custom trigger block gives an overflow.
It see
Hello,
I am looking to increase my custom image from a sampling rate of 250 to 500
MS/S. I am looking to get some clarification on a few things.
Looking through the verilog, it appears both the 200 and 400 images have the
same master clock rate of 250 MHz, but with the 400 image there are twice
Correcting the MEM_DATA_W of the replay block from 128 to 64 ended up doing the
trick. Very strange that running with vs without the —GUI flag with the
rfnoc_image_builder command changed the result, but regardless I can open the
GUI and save the project now with a functioning transmit.
I also
I had customized RFDC IP block in the past, but I have re-installed UHD since
to try and resolve this transmit issue. I had just compiled it with the default
settings, except for my custom yml file and custom block. The only difference
is when I run with vs without the GUI option, without transm
If I use the same yml file I pasted above, I am able to generate an image that
properly transmits. However, if I use the same yml file, but when I use the
rfnoc_image_builder but with a GUI option, the transmit fails to work. I do not
edit anything in the GUI, I just tested the bitstream create
Yes, I tried to using that example as well but still nothing transmits(no light
indicator either).
I just compiled the default image(x410_200_rfnoc_image_core.yml) on my end and
still things work just fine also. My custom yml is more similar to the
x410_400_128_rfnoc_image_core.yml, so I am goi
Hello,
I did run the default image and everything worked fine. I pasted my YML file
below. Currently, the software I wrote builds a graph between the replay block
and the radio block, I don’t want anything else. I do have a custom block, but
I do not need it for transmit. I tested it on the def
Hello,
I am currently running a custom image, however, I am having trouble
transmitting data from the replay block to the TX antenna.
When I created my project, I used a similar RFNOC structure to the one found in
“x410_400_128_rfnoc_image.yml” - I use the same connections for my radio blocks
Hello,
I am currently working with the x410. I am curious about part of the output of
uhd_usrp-probe —tree. Particularly, these properties…
/blocks/0/Radio#0/dboard/rx_frontends/0/LO1/enabled
/blocks/0/Radio#0/dboard/rx_frontends/0/LO1/test_mode
I dont recall seeing documentation on this, and
Apologies, using the radio_control did in fact list a GPIO bank, it is just
listed as “GPIO”, not “GPIO0” or “GPIOA”
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Hello,
I tried using set_gpio_attr using both multi_usrp and radio_control…
When I use uhd::usrp::multi_usrp, I get an error trying to make a multi_usrp
object
```
[ERROR] [RFNOC::GRAPH] Caught exception while initializing graph: RuntimeError:
Cannot create! Property already exists at: /blocks
Hello,
I currently have an application that needs to take GPIO as an input. I added
the GPIO wire using Vivado to my custom RFNOC application. How do I set a GPIO
pin as an input in the uhd software? Do I also need to build a custom
application for this?
I saw a function usrp.set_gpio_src with
This is the output of uhd_usrp_probe
/
| Device: N300-Series Device
| _
|/
| | Mboard: ni-n3xx-3255102
| | dboard_0_pid: 338
| | dboard_0_serial: 3252A17
| | dboard_1_pid: 338
| | dboard_1_serial: 325
Hello,
\
I currently have a custom RFNOC module. When I try to initialize my block
however, I am unable to find it. I get an error that seems to match up with the
block id I set on my module, but it still seems that it cannot be found. This
is the error that is shown…
`[WARNING] [RFNOC::BLOCK_
Hello,
I have an application where I collect timed bursts of samples every period of
time for an amount of time. For example, Every millisecond, collect samples for
100 microseconds.
I’ve used GPIO and other synchronization methods successfully before, but I am
wondering if its possible using
What adapters do you recommend?
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I am using this
[card](https://www.amazon.com/10Gtek-X540-T2-Converged-Network-Adapter/dp/B01HMGWOU8?th=1),
which as the intel x540 controller. The lights on the ethernet card do light
up, but the lights of the SFP port on the N321 does not. I verified it works
when working with the 10/100/1000
Currently, I am using 192.168.20.2(as if trying to stream from port SFP1
instead of SFP0) however, switching to either port and using either
192.168.10.2 or 192.168.20.2 did not result in any change. I am unable to ping
through those addresses and I ensured that the MTU is set to 9000.
When I u
I am able to succesfully use the device, I just cant use the 10Gbe, which I
need.
When I run uhd_usrp_probe, I confirm that I am using version 4.4.0.0
>
>
> \[INFO\] \[UHD\] linux; GNU C++ version 9.4.0; Boost_107100;
> UHD_4.4.0.HEAD-0-g5fac246b
>
> \[INFO\] \[MPMD\] Initializing 1 device(s)
I still get the same error after using
"addr=192.168.10.2,mgmt_addr=192.168.1.151"
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uhd_usrp_probe --args addr=192.168.1.151 successfully probes the n321
uhd_usrp_probe --args addr=192.168.20.2(or192.168.10.2) does not successfully
probe the n321
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Hello,
I currently have an issue trying to stream packets through the SFP ports.
Currently, when I ssh into the Ettus N321 and use ifconfig, I get the following
output
> eth0 Link encap:Ethernet HWaddr 00:80:2F:35:25:BE
>
> inet addr:192.168.1.151 Bcast:192.168.1.255 Mask:25
Hello,
I am currently working with the X410(X4_400 image) using other the 1Gbe
ethernet only(for now) and an image that uses the following RFNOC graph
Active connections:
\* 0/Radio#0:0-->0/KeepOneInN#0:0
\* 0/KeepOneInN#0:0-->RxStreamer#0:0.
Regardless of any value of N I use(even when the m
I have noticed after further troubleshooting that my antenna light actually
appears to blink periodically. And I also seem to be getting overflow errors,
even though my data rate is quite small(\~5e6 samples per second,
32bits/sample, over ethernet).
When I use the same data rate with the defau
I am currently using C++. For now, the custom image I am using for the RX chain
is Radio -> KeepOneInN -> KeepOneInN -> Rxstreamer, which are all included in
the UHD 4.4.0, whilst still having the same issue. Specifically, here is the
output when I print active connections
```
* 0/Radio#0:0-->0
Hello,
I have currently using my own custom RFNOC image. It appears that samples are
being collected from the ADC, however, when I connect an input through the
antenna, my data samples to not change at all. It seems the data I receive
corresponds to when I change the frequency on my local oscil
Nothing interesting, I am currently just “toying around” to understand the
device(and sdrs) better, and the lowest the closest available signal generator
I have goes to 100 khz. I was using 3 Mhz before but I figured if the API was
telling me that it was able to be tuned lower than why not try r
When the frequency is called back, it gives back that it is set to 100 Khz. The
lowest it goes is 5 hz.
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Hello,
I am currently trying to recover a signal(sine wave) that goes into my RX2 path
on the Ettus N321/N320. However, I am having trouble recovering the signal.
My current set up is using a separate signal generator that is fed into the RX
port of the Ettus. I run the example rx_samples_to_f
Hello,
When I run the rfnoc_image_builder, I receive the following error
`Traceback (most recent call last):`
` File "/usr/local/bin/rfnoc_image_builder", line 29, in `
`from uhd.imgbuilder import image_builder`
` File "/usr/local/lib/python3.8/site-packages/uhd/__init__.py", line 10, i
Hello,
I am a little confused about the naming regarding the TX/RX ports on the Ettus
N321/N320. If I specify a channel(i.e channel 0) for receive, does that mean
RX2 will be active, or will TX/RX port be actively receiving? And if TX/RX can
recieve, does that mean the N320/N321 has up to 4 RX
Hello,
I am currently looking to see what the highest possible sampling rate is for
the ettus N321/N320. I see that the highest master clock rate is 250e6 Mhz,
However, on the product website(https://www.ettus.com/all-products/usrp-n321/),
it says that it can collect up to an instantaneous band
i found that I needed to create a timekeeper, within the mb_controller. i.e
`uhd::rfnoc::mb_controller::timekeeper::sptr tk =
graph->get_mb_controller(0)->get_timekeeper(0);`
This seems to do the trick. Im now getting a late error, but it is probably
another kind of issue.
_
Hello,
I am currently getting the following error, but I am lost as to how to work
around it…
`[ERROR] [RPC] Someone tried to claim this device again (From: 192.168.10.1)`
`[WARNING] [MPM.RPCServer] Someone tried to claim this device again (From:
192.168.10.1)`
It appears the problem comes fr
Hello,
I have a question regarding one of the uhd api examples.
In “test_timed_commands.cpp”, there is a comment that says the following for rx
streaming…
`// use a timed command to start a stream at a specific time`
`// this is not the right way start streaming at time x,`
`// but it should
With the HG image, things seem to be working fine. I can benchmark, and i can
collect samples at not only the full rate(25e6 MS/S), but at a higher rate than
the XG image, which is strange.
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I believe so. When I use uhd_usrp_probe, I get
`[INFO] [UHD] linux; GNU C++ version 9.4.0; Boost_107100;
UHD_4.3.0.HEAD-0-g1f8fd345`
`[INFO] [MPMD] Initializing 1 device(s) in parallel with args:
mgmt_addr=192.168.1.151,type=n3xx,product=n320,serial=3255102,name=ni-n3xx-3255102,fpga=XG,claimed=
Hello,
I still run into the same issue, even after I have changed to parameters.
`/usr/local/lib/uhd/examples/benchmark_rate --args
"type=n3xx,mgmt_addr=192.168.1.151,addr=192.168.10.2,master_clock_rate=200e6"
--duration 60--channels 0--rx_rate 31.25e6--rx_subdev "A:0"
--
Hello,
I am currently trying to run benchmark_rate, however, I am getting an error
when I do.
`/usr/local/lib/uhd/examples/benchmark_rate --args
"type=n3xx,mgmt_addr=192.168.1.151,addr=192.168.10.2,master_clock_rate=245.76e6"
--duration 60--channels "0,1,2,3"--rx_rate 30.72e6
Hello,
I have an application where I collect I burst of samples from Rx ports, and
stream the samples into my host computer. I would like to also store the
timestamps from the packages onto the host computer, as well as store from
which RX port the signal arrived so I may separate the data in d
Hello,
I am currently trying to figure out how to use the testbench. I am currently
using rfnoc-gain and rfnoc-keep_one_in_n as reference.
When I run my testbench, my code hangs on the line that write to the register
of the block
`write_reg(port, dut.REG_MODE, mode);`
where write_reg is the f
I am currently trying to trace through the makefiles to see what is wrong, but
it seems it can not find any sources unless explicitly told. I could go through
the process of manually including every file needed, however, I feel like this
would be inefficient in the long run, so I am still trying
I found explicitly including the verilog in the testbench using “\`include”
worked. However, I found it to be the case that for any module that is needed,
even if it was “added” by the builder.
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Hello,
I am currently trying to design my own OOT module, yet when I run ‘make
testbenches’ I get the following error…
`ERROR: [VRFC 10-2063] Module not found while processing
module instance
[/workarea/uhd/OOTs/rfnoc-trigger/fpga/rfnoc_block_trigger/rfnoc_block_trigger_tb.sv:123]`
`ERROR:
Hello,
I am trying to develop an RFNoC application that starts collecting samples when
a trigger rises. However, I am unsure how to route the TrigIn/PPS under the
RFNoC utility. For example, I found the radio RFNoC is used to interface with
the TX/RX.
Thanks,
Joe
_
Hello,
I have run into an issue when trying to synthesize the “gain” RFNoC as
described in the tutorial here
https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0
I get an error that the module cmplx mul is locked. I found that in the verilog
file “rfnoc_block_gain.v”, the module is inst
Thanks, Following up on this, if I then use fc32, or fc64, how does the format
change.
Also, does there exist documentation on the default set of file formats?
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This was the full line ./rfnoc_rx_to_file --freq 2.4e3 --rate 1e6 --duration 3,
so my guess is by default it is using sc16. However, I would like to know the
format of the bitstream itself(i.e what bits are associated with I,Q,etc along
the bitstream).
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Hello,
I am currently following instructions for RFNoC here
https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0.
I get a file when running the executable rfnoc_rx_to_file, called
usrp_samples.dat. However, I am lost as to how I am supposed to parse this
file. Is there any instructions o
Running “make xsim” worked there for me, I think I understand this much better
now. I believe running the simulations for RFNoC blocks will suffice for me,
but I was curious if there was a top level simulation.
Thanks,
Joe
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