Hi All,
I'm using UHD 4.2 to play around with RFNOC4. I successfully added an FFT block
to the XG image of an X300, no static connections. uhd_usrp_probe returns as
expected. I use the attached code to test it out.
When I commit the graph I get the following error:
Traceback (most recent call la
One more thought. If the FPGA version that you built with dynamic linking,
you should be able to create an RFNoC Graph as follows:
tx_streamer => multiDDC => rx_streamer(s)
This way you can eliminate the radio from the equation and test in a very
similar fashion to the way it is tested in a testb
Oops. Ignore what I said. I now realize you stated you were getting an
Overflow which of course you would never get if streaming hadn't started.
Rob
On Mon, Sep 12, 2022 at 6:32 PM Rob Kossler wrote:
> Are you sure that the radio is even streaming? The typical method for
> starting streaming is
Are you sure that the radio is even streaming? The typical method for
starting streaming is to tell the rx_streamer to start streaming. Then, in
UHD-land, the rx_streamer ctrl tells the next upstring block to start
streaming such that this streaming command propagates up the chain until
the radio
Yes, of course. But I don't get 1 sample from the ddc's, even with just one
channel of a 2:1 decimated channel connected to the rx streamer.
On Mon, 12 Sept 2022 at 22:13, Jonathon Pendlum
wrote:
> The aggregate output rate of the 5 streams could require more bandwidth
> than the 10 GigE interfa
The aggregate output rate of the 5 streams could require more bandwidth
than the 10 GigE interface can sustain. What are the exact output rates?
On Mon, Sep 12, 2022 at 3:53 PM Kevin Williams wrote:
> Those rates vary from a 2:1 decimation down to other rates.
>
> The host has 10 Gbe interfaces
Those rates vary from a 2:1 decimation down to other rates.
The host has 10 Gbe interfaces to the USRP.
I get samples if i connect the radio to the rx streamer, just nothing from
the ddc's.
On Mon, 12 Sept 2022 at 21:48, Jonathon Pendlum
wrote:
> Hi Kevin,
>
> What are the sample rates for the
Hi Kevin,
What are the sample rates for the 5 outputs? What connection are you using
to your host PC, 1 GigE or 10 GigE?
Jonathon
On Mon, Sep 12, 2022 at 3:38 PM Kevin Williams wrote:
> Hi Jonathon,
>
> I've got an x310. The flowgraph is a simple radio->multiddc->(to 5x
> outputs). I've tried
Hi Jonathon,
I've got an x310. The flowgraph is a simple radio->multiddc->(to 5x
outputs). I've tried both static and dynamic routing from the radio block.
I.e. the static route version:
|/
| | Static connections on this device:
| |
| | * 0/Radio#0:0==>0/multiddc#0:0
| | * 0
Hello Kevin,
What device are you using and what does your flowgraph look like? What
sample rate are you running at? If your block is running at the radio
sample rate (e.g. 200 MSPS on a X310), your block will need to process one
input sample every clock cycle on average.
Jonathon
On Mon, Sep 12,
OK, thanks. I was hoping that you were on to something. Thanks.
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On 2022-09-12 12:46, ja...@gardettoengineering.com wrote:
Marcus D. Leech wrote:
Sample-rate is an inherent property of a /stream/ as I recall,
rather than a /session/. Are you creating a new stream across
sample-rate changes, or applying the rate change to an existing
stream
Marcus D. Leech wrote:
> Sample-rate is an inherent property of a *stream* as I recall, rather
> than a *session*. Are you creating a new stream
> across sample-rate changes, or applying the rate change to an
> existing stream?
That is an interesting comment. I am not stopping and starting a
On 2022-09-12 10:58, ja...@gardettoengineering.com wrote:
Thanks Marcus.
I agree, there is no way this is design-intent. My gut says it is some
sort of clock situation on the FPGA, but I am not sure what.
Unfortunately, the only ones who can probably weigh in on this would
be some of the Ett
Thanks Marcus.
I agree, there is no way this is design-intent. My gut says it is some sort of
clock situation on the FPGA, but I am not sure what. Unfortunately, the only
ones who can probably weigh in on this would be some of the Ettus FPGA
designers, and I am guessing that they don’t see to
Hi All,
I've got an IP core that is causing an "ERROR_CODE_OVERFLOW" when used in
an RFNoC project.
The core responds correctly when simulated outside the RFNoC environment.
(I can see correct output, the AXI streaming signalling, back-pressure when
required, etc.)
I'm not sure how to go about d
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