Hello Kevin,
What device are you using and what does your flowgraph look like? What
sample rate are you running at? If your block is running at the radio
sample rate (e.g. 200 MSPS on a X310), your block will need to process one
input sample every clock cycle on average.
Jonathon
On Mon, Sep 12, 2022 at 9:09 AM Kevin Williams <zs1...@gmail.com> wrote:
> Hi All,
>
> I've got an IP core that is causing an "ERROR_CODE_OVERFLOW" when used in
> an RFNoC project.
>
> The core responds correctly when simulated outside the RFNoC environment.
> (I can see correct output, the AXI streaming signalling, back-pressure when
> required, etc.)
>
> I'm not sure how to go about debugging this, and am not yet familiar
> enough with RFNoC to know what to ask.
>
> I have been thinking it was the core not being reset or clocked correctly,
> but this is how it gets instantiated:
>
> multiddc multiddc_i (
> // - Using different clocks for the IP core and the AXI interface.
> The IPCore_Clk and AXILite_ACLK must be
> // synchronous and connected to the same clock source. The
> IPCore_RESETN and AXILite_ARESETN must be
> // connected to the same reset source. See Synchronization of
> Global Reset Signal to IP Core Clock Domain.
> .IPCORE_CLK (axis_data_clk),
> .IPCORE_RESETN (~axis_data_rst),
>
> .AXI4_Lite_ACLK (axis_data_clk),
> .AXI4_Lite_ARESETN (~axis_data_rst),
>
> The core YAML file describes the clock as:
>
> data:
> fpga_iface: axis_chdr
> clk_domain: ce
>
> In the project YAML file:
>
> clk_domains:
> - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport:
> radio }
> - { srcblk: _device_, srcport: ce, dstblk: multiddc0, dstport: ce }
>
> Is there something that might be an obvious first place to check?
>
> Many thanks, Kevin
>
> --
> Kevin Williams
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