On 2022-09-12 10:58, ja...@gardettoengineering.com wrote:
Thanks Marcus.
I agree, there is no way this is design-intent. My gut says it is some
sort of clock situation on the FPGA, but I am not sure what.
Unfortunately, the only ones who can probably weigh in on this would
be some of the Ettus FPGA designers, and I am guessing that they don’t
see too many people changing the sample rate on the fly, and this is
an unseen before bug.
Sample-rate is an inherent property of a *stream* as I recall, rather
than a *session*. Are you creating a new stream
across sample-rate changes, or applying the rate change to an
existing stream?
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