Hi Philip,
> From: U-Boot On Behalf Of Bernard, Philip
> Sent: Thursday, February 23, 2023 9:21 AM
> To: u-boot@lists.denx.de
> Subject: Boot from 64-bit memory address?
>
> Hi,
>
> Is it possible to boot from a DRAM memory address beyond the 32-bit boundary?
> I'm trying to configure a new RISC
on/qemu-riscv/Kconfig | 5 +
> 1 file changed, 5 insertions(+)
Reviewed-by: Rick Chen
tion/qemu-riscv/qemu-riscv.c | 24
> include/configs/qemu-riscv.h| 10 --
> 2 files changed, 34 deletions(-)
Reviewed-by: Rick Chen
e/configs/qemu-riscv.h| 2 +-
> 4 files changed, 16 insertions(+), 1 deletion(-)
Reviewed-by: Rick Chen
> configs/sifive_unmatched_defconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rick Chen
a few
> places need an additional header instead.
>
> Signed-off-by: Tom Rini
> ---
> Cc: Rick Chen
> Cc: Leo
> ---
Reviewed-by: Rick Chen
arch/riscv/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rick Chen
HI all,
> On Mon, 5 Sep 2022 11:30:38 -0400
> Sean Anderson wrote:
>
> > On 9/5/22 3:47 AM, Nikita Shubin wrote:
> > > Hi Rick!
> > >
> > > On Mon, 5 Sep 2022 14:22:41 +0800
> > > Rick Chen wrote:
> > >
> > >> Hi,
> >
> From: Nikita Shubin
> Sent: Friday, September 02, 2022 4:48 PM
> To: u-boot@lists.denx.de
> Cc: li...@yadro.com; Sean Anderson ; Rick Chen
> ; Nikita Shubin ; Rick Jian-Zhi
> Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; Simon Glass ; Bin Meng
> ; Ilias Apalodimas
rint out the version number of the SBI implementation.
> Choose the correct output format for RustSBI.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> cmd/riscv/sbi.c | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rick Chen
ling 'Get SBI specification version' fails, write an error message and
> return CMD_RET_FAILURE.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> cmd/riscv/sbi.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
Reviewed-by: Rick Chen
he same short texts for the legacy extensions as the
> SBI specification 1.0.0.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> cmd/riscv/sbi.c | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
Reviewed-by: Rick Chen
l'
> arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
>
> Signed-off-by: Alexandre Ghiti
> Reviewed-by: Bin Meng
> Tested-by: Heinrich Schuchardt
> Tested-by: Heiko Stuebner
> Tested-by: Christian Stewart
> ---
> v3:
> no change
> ---
> arch/riscv/Makefile | 11 ++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
Reviewed-by: Rick Chen
drop riscv toolchain-alias
> v3:
> new patch
> ---
> tools/docker/Dockerfile | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
buildman: differentiate between riscv32, riscv64
>
> riscv32 needs a different toolchain than riscv64
>
> Signed-off-by: Heinrich Schuchardt
> ---
> v4:
> no change
> v3:
> new patch
> ---
> tools/buildman/boards.py | 11 +++
> 1 file changed, 11 insertions(+)
Reviewed-by: Rick Chen
Hi Nikita,
> From: Nikita Shubin
> Sent: Wednesday, August 31, 2022 3:25 PM
> To: u-boot@lists.denx.de
> Cc: li...@yadro.com; Nikita Shubin ; Rick Jian-Zhi
> Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; Simon Glass ; Bin Meng
> ; Heinrich Schuchardt ; Ilias
> Apalodimas ; Alexandru Gagniuc
> ; Andr
; #include
> #include
>
> -#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
> +#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 2) /* 250 ms */
Reviewed-by: Rick Chen
Hi,
When I free-run a SMP system, I once hit a failure case where some
harts didn't boot to the kernel shell successfully.
However it can't be duplicated anymore even if I try many times.
But when I set a break during debugging with GDB, it can trigger the
failure case each time.
I think the mech
have special IO access instructions just like
> + ARM;
> * all IO is memory mapped.
> * Note that these are defined to perform little endian accesses
> * only. Their primary purpose is to access PCI and ISA peripherals.
Reviewed-by: Rick Chen
e end address hence load its address directly
> into register 't2' for optimization.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/cpu/start.S | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Rick Chen
type so don't bother reloading it.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/cpu/start.S | 1 -
> 1 file changed, 1 deletion(-)
Reviewed-by: Rick Chen
v.inc | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Rick Chen
LF image that was mapped by
> previous mmap().
>
> Signed-off-by: Bin Meng
> ---
>
> tools/prelink-riscv.c | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Rick Chen
rgument of prelink-riscv
>
> The argv[2] is never used in prelink-riscv. Drop it.
>
> Signed-off-by: Bin Meng
> ---
>
> Makefile | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
debug.
>
> Add a new property to make this explicit.
>
> The existing 'RISC-V' is now taken to mean 32-bit.
>
> Signed-off-by: Simon Glass
> ---
>
> boot/image.c| 3 ++-
> include/image.h | 3 ++-
> 2 files changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Rick Chen
Allow U-Boot to load 32 or 64 bits RISC-V Kernel Image
distinguishly. It helps to avoid someone maybe make a mistake
to run 32-bit U-Boot to load 64-bit kernel.
Signed-off-by: Rick Chen
---
The patchset is based on Simon's patch:
riscv: Add a 64-bit image type
---
---
arch/riscv/include/
> From: Bin Meng
> Sent: Thursday, March 30, 2023 12:20 PM
> To: u-boot@lists.denx.de
> Cc: Andrew Scull ; Leo Yu-Chi Liang(梁育齊)
> ; Rick Jian-Zhi Chen(陳建志) ; Simon
> Glass
> Subject: [PATCH 7/8] riscv: spl: Remove relocation sections
>
> U-Boot SPL is not relocable. Drop these relocation secti
Hi Simon,
> Hi Rick,
>
> On Mon, 10 Apr 2023 at 01:26, Rick Chen wrote:
> >
> > Allow U-Boot to load 32 or 64 bits RISC-V Kernel Image
> > distinguishly. It helps to avoid someone maybe make a mistake
> > to run 32-bit U-Boot to load 64-bit kernel.
---+
> ++ ==> | hart N-1 stack|
> | hart 1 stack |++
> ++| ..|
> | ..|| malloc_base |
> ++++
> | hart N-1 stack|| GD|
> +++----+
> |||
ion should generate a breakpoint exception.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> cmd/riscv/exception.c | 10 ++
> doc/usage/exception.rst | 3 +++
> 2 files changed, 13 insertions(+)
Reviewed-by: Rick Chen
Hi Green,
> From: Green Wan [mailto:green@sifive.com]
> Sent: Monday, April 12, 2021 10:33 AM
> To: Sean Anderson
> Cc: Rick Chen; Rick Jian-Zhi Chen(陳建志); Bin Meng; U-Boot Mailing List; Paul
> Walmsley; Pragnesh Patel; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊);
>
Hi Green,
> From: Green Wan [mailto:green@sifive.com]
> Sent: Tuesday, March 30, 2021 1:27 PM
> Cc: Green Wan; Rick Jian-Zhi Chen(陳建志); Paul Walmsley; Pragnesh Patel; Sean
> Anderson; Bin Meng; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊); Brad
> Kim; u-boot@lists.denx.de
> Subject: [RFC
Hi Sean
> On 4/12/21 10:39 PM, Rick Chen wrote:
> > Hi Green,
> >
> >> From: Green Wan [mailto:green@sifive.com]
> >> Sent: Monday, April 12, 2021 10:33 AM
> >> To: Sean Anderson
> >> Cc: Rick Chen; Rick Jian-Zhi Chen(陳建志); Bin Meng; U-Boo
Hi Sean,
> On 4/13/21 12:12 AM, Rick Chen wrote:
> > Hi Sean
> >
> >> On 4/12/21 10:39 PM, Rick Chen wrote:
> >>> Hi Green,
> >>>
> >>>> From: Green Wan [mailto:green@sifive.com]
> >>>> Sent: Monday, April 12, 2021
> From: Green Wan [mailto:green@sifive.com]
> Sent: Tuesday, April 13, 2021 5:32 PM
> Cc: Green Wan; Rick Jian-Zhi Chen(陳建志); Paul Walmsley; Pragnesh Patel; Sean
> Anderson; Bin Meng; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊); Brad
> Kim; open list
> Subject: [RFC PATCH v5 1/2] arch: ri
Hi Green,
> From: Green Wan [mailto:green@sifive.com]
> Sent: Tuesday, April 13, 2021 5:32 PM
> Cc: Green Wan; Sean Anderson; Bin Meng; Rick Jian-Zhi Chen(陳建志); Paul
> Walmsley; Pragnesh Patel; Bin Meng; Simon Glass; Atish Patra; Leo Yu-Chi
> Liang(梁育齊); Brad Kim; open list
> Subject: [RFC P
esn't make sense.
Maybe you can combine with the dts relative files in [PATCH v6 6/7]
into one patch and name as :
riscv: dts: ...
LGTM.
Other than that,
Reviewed-by: Rick Chen
> dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += m
Hi Green
> On Thu, Apr 15, 2021 at 1:25 PM Rick Chen wrote:
> >
> > Hi Green,
> >
> > > From: Green Wan [mailto:green@sifive.com]
> > > Sent: Thursday, April 08, 2021 9:40 PM
> > > Cc: bmeng...@gmail.com; Green Wan; Greentime Hu; Rick Jian-Zhi
is M-mode check can be remove, it is a repeat confirmation in
harts_early_init() of arch/riscv/cpu/fu740/spl.c
Other than that,
Reviewed-by: Rick Chen
> + /*
> +* Configure proprietary settings and customized CRSs of harts
> +*/
> +call_harts_early_init:
> +
n.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf
>
> Signed-off-by: Green Wan
> Reviewed-by: Sean Anderson
> Reviewed-by: Bin Meng
> ---
> arch/riscv/cpu/fu740/spl.c | 15 +++
> 1 file changed, 15 insertions(+)
Reviewed-by: Rick Chen
10 --
> 1 file changed, 8 insertions(+), 2 deletions(-)
Reviewed-by: Rick Chen
Hi Green,
I did not sign the Reviewed-by for this patch "board: sifive: add
HiFive Unmatched board support" from v1 to v6.
But it just has been tagged in [v7,7/8] board: sifive: add HiFive
Unmatched board support by yourself.
[v6,6/7] board: sifive: add HiFive Unmatched board support
https://pat
Hi Green,
> Hi Rick,
>
> Thanks for quick response. See my reply below.
>
> On Mon, May 3, 2021 at 10:34 AM Rick Chen wrote:
> >
> > Hi Green,
> >
> >
> > I did not sign the Reviewed-by for this patch "board: sifive: add
> > HiFive Unmatche
rch/riscv/include/asm/arch-fu740/reset.h | 13 ++
> arch/riscv/include/asm/arch-fu740/spl.h | 14 ++
> arch/riscv/lib/sifive_clint.c | 1 -
Refer to comments about [PATCH v7 1/8].
https://www.mail-archive.com/u-boot@lists.denx.de/msg405522.html
Hope same code base can be effective re-use in the future.
Reviewed-by: Rick Chen
uot;riscv: Move all fdt fixups together")
> Signed-off-by: Sean Anderson
> ---
> I have not actually tested this (nor observed the original failure). But this
> seemed buggy from inspection.
>
> arch/riscv/lib/fdt_fixup.c | 11 +++
> 1 file changed, 7 insertions(+)
Hi Bin,
> From: Bin Meng
> Sent: Monday, May 10, 2021 2:58 PM
> To: Simon Glass ; Rick Jian-Zhi Chen(陳建志)
> ; u-boot@lists.denx.de
> Subject: [PATCH v4 00/13] riscv: Switch to use binman to generate u-boot.itb
>
> This series updates binman to handle creation of u-boot.itb image for RISC-V
> bo
Hi Bin
> Hi Bin,
>
> > From: Bin Meng
> > Sent: Monday, May 10, 2021 2:58 PM
> > To: Simon Glass ; Rick Jian-Zhi Chen(陳建志)
> > ; u-boot@lists.denx.de
> > Subject: [PATCH v4 00/13] riscv: Switch to use binman to generate u-boot.itb
> >
> > This series updates binman to handle creation of u-boot.i
chuchardt
> ---
> configs/sifive_unmatched_defconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rick Chen
; Add include skeleton.
> ---
> arch/riscv/include/asm/acpi_table.h | 11 +++
> 1 file changed, 11 insertions(+)
Reviewed-by: Rick Chen
> Hi Rick,
>
> On Wed, 19 Apr 2023 at 00:56, Rick Chen wrote:
> >
> > Hi Simon,
> >
> > > Hi Rick,
> > >
> > > On Mon, 10 Apr 2023 at 01:26, Rick Chen wrote:
> > > >
> > > > Allow U-Boot to load 32 or 64 bits RIS
Hi Tom
> On Fri, Dec 09, 2022 at 08:48:37AM -0500, Sean Anderson wrote:
> > On 12/7/22 01:23, Rick Chen wrote:
> > > In RISC-V, it only provide normal mode booting currently.
> > > To speed up the booting process, here provide SPL_OPENSBI_OS_BOOT
> > > to ach
> On 12/7/22 01:23, Rick Chen wrote:
> > In RISC-V, it only provide normal mode booting currently.
> > To speed up the booting process, here provide SPL_OPENSBI_OS_BOOT
> > to achieve this feature which will be call Fast-Boot mode. By
>
> Can you name this something
Hi Sean,
> On 12/12/22 10:03, Tom Rini wrote:
> > On Mon, Dec 12, 2022 at 02:45:10PM +0800, Rick Chen wrote:
> >> Hi Tom
> >>
> >>> On Fri, Dec 09, 2022 at 08:48:37AM -0500, Sean Anderson wrote:
> >>>> On 12/7/22 01:23, Rick Chen wrote:
Hi Tom
> On Mon, Dec 12, 2022 at 02:45:10PM +0800, Rick Chen wrote:
> > Hi Tom
> >
> > > On Fri, Dec 09, 2022 at 08:48:37AM -0500, Sean Anderson wrote:
> > > > On 12/7/22 01:23, Rick Chen wrote:
> > > > > In RISC-V, it only provide normal mode b
> On Mon, Dec 12, 2022 at 03:49:10PM +0800, Rick Chen wrote:
> > > On 12/7/22 01:23, Rick Chen wrote:
> > > > In RISC-V, it only provide normal mode booting currently.
> > > > To speed up the booting process, here provide SPL_OPENSBI_OS_BOOT
> > > >
Hi Tom,
> On Tue, Dec 13, 2022 at 10:06:50AM +0800, Rick Chen wrote:
> > > On Mon, Dec 12, 2022 at 03:49:10PM +0800, Rick Chen wrote:
> > > > > On 12/7/22 01:23, Rick Chen wrote:
> > > > > > In RISC-V, it only provide normal mode booting currently
Hi Tom,
> On Wed, Dec 14, 2022 at 08:49:03AM +0800, Rick Chen wrote:
> > Hi Tom,
> >
> > > On Tue, Dec 13, 2022 at 10:06:50AM +0800, Rick Chen wrote:
> > > > > On Mon, Dec 12, 2022 at 03:49:10PM +0800, Rick Chen wrote:
> > > > > > > On 1
> On 12/13/22 11:24, Tom Rini wrote:
> > On Tue, Dec 13, 2022 at 08:42:47AM +0800, Rick Chen wrote:
> >> Hi Sean,
> >>
> >>> On 12/12/22 10:03, Tom Rini wrote:
> >>>> On Mon, Dec 12, 2022 at 02:45:10PM +0800, Rick Chen wrote:
> >>>&
Change openSBI load address from 0x100 to 0x0 and it
will start to run at 0x0 directly without relocation.
Signed-off-by: Rick Chen
---
board/AndesTech/ax25-ae350/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/AndesTech/ax25-ae350/Kconfig
b/board
CCTL operations are available to Supervisor/User-mode
software under the control of the mcache_ctl.CCTL_SUEN
control bit. Enable it to support Superviosr(and User)
CCTL operations.
Signed-off-by: Rick Chen
---
arch/riscv/cpu/ax25/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a
Hi Bin
> On Wed, Dec 21, 2022 at 11:00 AM Rick Chen wrote:
> >
> > CCTL operations are available to Supervisor/User-mode
> > software under the control of the mcache_ctl.CCTL_SUEN
> > control bit. Enable it to support Superviosr(and User)
>
> typo: Supervi
Hi Bin,
> On Wed, Dec 21, 2022 at 10:29 AM Rick Chen wrote:
> >
> > Change openSBI load address from 0x100 to 0x0 and it
>
> nits: OpenSBI
OK, will fix it.
>
> > will start to run at 0x0 directly without relocation.
> >
> > Signed-off-by: Rick Che
| 23
> arch/riscv/cpu/jh7110/dram.c | 38 +
> arch/riscv/cpu/jh7110/spl.c | 56 +++
> .../include/asm/arch-jh7110/jh7110-regs.h | 20 +++
> arch/riscv/include/asm/arch-jh7110/spl.h | 13 +++++
> 6 files changed, 160 insertions(+)
Reviewed-by: Rick Chen
d-off-by: Rick Chen
---
arch/riscv/lib/memcpy.S | 2 ++
arch/riscv/lib/spl.c| 16
2 files changed, 18 insertions(+)
diff --git a/arch/riscv/lib/memcpy.S b/arch/riscv/lib/memcpy.S
index 00672c19ad..9884077c93 100644
--- a/arch/riscv/lib/memcpy.S
+++ b/arch/riscv/lib/mem
> On Thu, Dec 22, 2022 at 1:23 PM Rick Chen wrote:
> >
> > Hi Bin,
> >
> > > On Wed, Dec 21, 2022 at 10:29 AM Rick Chen wrote:
> > > >
> > > > Change openSBI load address from 0x100 to 0x0 and it
> > >
> > > nits: Ope
> On Thu, Dec 22, 2022 at 4:07 PM Rick Chen wrote:
> >
> > > On Thu, Dec 22, 2022 at 1:23 PM Rick Chen wrote:
> > > >
> > > > Hi Bin,
> > > >
> > > > > On Wed, Dec 21, 2022 at 10:29 AM Rick Chen wrote:
> > &
Hi Samuel,
Samuel Holland 於 2022年12月28日 週三 上午10:47寫道：
>
> On 12/22/22 01:21, Rick Chen wrote:
> > When fit image boots from ram, the payload will
> > be prepared in the address of SPL_LOAD_FIT_ADDRESS.
> > In spl fit generic flow, it will malloc another
> > mem
> On 12/27/22 21:22, Rick Chen wrote:
> > Hi Samuel,
> >
> > Samuel Holland 於 2022年12月28日 週三 上午10:47寫道：
> >>
> >> On 12/22/22 01:21, Rick Chen wrote:
> >>> When fit image boots from ram, the payload will
> >>> be prepared in the add
CCTL operations are available to Supervisor/User-mode
software under the control of the mcache_ctl.CCTL_SUEN
control bit. Enable it to support Supervisor(and User)
CCTL operations.
Signed-off-by: Rick Chen
---
Changes in v2
- fix typo
- correct aligment
---
arch/riscv/cpu/ax25/cpu.c | 18
details can refer to commit cb052d771200
("riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+")
Signed-off-by: Rick Chen
---
Changes in v2
- fix typo
- describe why is this change a must have
---
board/AndesTech/ax25-ae350/Kconfig | 2 +-
1 file changed, 1 insertion(+),
d-off-by: Rick Chen
---
Changes in v2
- Move spl.c to board level instead of arch level
---
arch/riscv/cpu/ax25/Makefile | 1 +
arch/riscv/cpu/ax25/spl.c| 31 +++
arch/riscv/lib/memcpy.S | 2 ++
3 files changed, 34 insertions(+)
create mode 100644 arch/risc
Hi Samuel
> On 1/3/23 02:18, Rick Chen wrote:
> > Original openSBI (without FW_PIC) will relocate itselt
>
> typo: itself
OK, I will fix it.
>
> > from 0x100 to 0x0. After openSBI added FW_PIC codes,
> > it will not relocate any more and alaways run at 0x10
> Hi Rick,
>
> On 1/3/23 02:20, Rick Chen wrote:
> > When fit image boots from ram, the payload will
> > be prepared in the address of SPL_LOAD_FIT_ADDRESS.
> > In spl fit generic flow, it will malloc another
> > memory address and copy whole fit image to this
declare the
board_spl_fit_buffer_addr() to replace the original one.
The larger image size (eq: Kernel Image 10~20MB), it
can save more booting time.
Signed-off-by: Rick Chen
---
Changes in v3
- fix aligment
- refine board_spl_fit_buffer_addr
---
arch/riscv/cpu/ax25/Makefile | 1 +
arch/riscv/cpu
Add src and dst address checking, if they
are the same address, just return and don't
copy data anymore.
Signed-off-by: Rick Chen
---
Changes in v3
- new patch: separate from [1/2]
---
arch/riscv/lib/memcpy.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/lib/memcpy.S b
details can refer to commit cb052d771200
("riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+")
Signed-off-by: Rick Chen
Reviewed-by: Samuel Holland
---
Changes in v3
- fix typos
---
board/AndesTech/ax25-ae350/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
details can refer to commit cb052d771200
("riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+")
Signed-off-by: Rick Chen
Reviewed-by: Samuel Holland
Reviewed-by: Bin Meng
---
Changes in v4
- fix openSBI typo
---
board/AndesTech/ax25-ae350/Kconfig | 2 +-
1 file changed, 1 inser
> On Wed, Jan 4, 2023 at 10:08 AM Rick Chen wrote:
> >
> > Original openSBI (without FW_PIC) will relocate itself
>
> nits: OpenSBI
>
> > from 0x100 to 0x0. After openSBI added FW_PIC codes,
>
> ditto
OK, will fix it.
>
> > it will not
3xx) or realized using a WDT (e.g. ag101).
>
> Remove this left-over implementation in preparation for the removal of
> the `addr` parameter in the entire tree.
>
> Cc: Rick Chen
> Signed-off-by: Harald Seiler
> ---
> arch/nds32/cpu/n1213/start.S | 22 ---
nges)
>
> board/sipeed/maix/Kconfig | 16 ++
> configs/sipeed_maix_bitm_defconfig | 11 +
> doc/board/sipeed/maix.rst | 319 -
> include/configs/sipeed-maix.h | 7 +-
> 4 files changed, 301 insertions(+), 52 deletions(-)
Reviewed-by: Rick Chen
will make gd->dm_root = NULL and gd->timer = NULL, so
> timer_get_us() -> get_ticks() -> dm_timer_init() will lead to an
> indefinite recursion.
>
> So select TIMER_EARLY when tracing got enabled.
>
> Signed-off-by: Pragnesh Patel
> ---
>
> Changes in v2:
> - new patch
>
> lib/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rick Chen
-
> drivers/timer/sifive_clint_timer.c | 21 -
> include/configs/ax25-ae350.h | 5 +
> include/configs/qemu-riscv.h | 5 +
> include/configs/sifive-fu540.h | 5 +
> 6 files changed, 75 insertions(+), 3 deletions(-)
Reviewed-by: Rick Chen
Rini
> Subject: [PATCH] doc: qemu-riscv: Fix opensbi build instructions
>
> Latest opensbi uses generic platform for Qemu. Update the build
> instructions.
>
> Signed-off-by: Atish Patra
> ---
> doc/board/emulation/qemu-riscv.rst | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
s. If the DMA API only uses 32/64-bit
> addresses, dma_addr_t need only be 32/64 bits wide.
>
> Signed-off-by: Padmarao Begari
> Reviewed-by: Anup Patel
> Reviewed-by: Bin Meng
> ---
> arch/riscv/Kconfig | 4
> arch/riscv/include/asm/types.h | 4
> 2 files changed, 8 insertions(+)
>
Reviewed-by: Rick Chen
; > drivers/timer/andes_plmt_timer.c | 21 -
> > drivers/timer/riscv_timer.c| 21 -
> > drivers/timer/sifive_clint_timer.c | 21 -
> > include/configs/ax25-ae350.h | 5 +
> > include/configs/qemu-riscv.h
Hi Joe
> From: Padmarao Begari [mailto:padmarao.beg...@microchip.com]
> Sent: Tuesday, December 22, 2020 9:12 PM
> To: u-boot@lists.denx.de; bmeng...@gmail.com; Rick Jian-Zhi Chen(陳建志);
> anup.pa...@wdc.com; lukas.a...@aisec.fraunhofer.de; joe.hershber...@ni.com;
> lu...@denx.de; atish.pa...@wdc
Hi Pragnesh
> On Tue, Jan 5, 2021 at 7:12 AM Sean Anderson wrote:
> >
> > On 1/4/21 8:37 PM, Rick Chen wrote:
> > > Hi Pragnesh
> > >
> > >>> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
> > >>> Sent: Tuesday, Decemb
gnesh Patel
> ---
>
> Changes in v3:
> - Add IS_ENABLED(CONFIG_TIMER_EARLY) for timer_early_get_rate()
> and timer_early_get_count() functions.
Reviewed-by: Rick Chen
Hi Padmarao
> From: Padmarao Begari [mailto:padmarao.beg...@microchip.com]
> Sent: Tuesday, December 22, 2020 9:12 PM
> To: u-boot@lists.denx.de; bmeng...@gmail.com; Rick Jian-Zhi Chen(陳建志);
> anup.pa...@wdc.com; lukas.a...@aisec.fraunhofer.de; joe.hershber...@ni.com;
> lu...@denx.de; atish.pa..
> > This is mostly useful in tracing.
> >
> > Signed-off-by: Pragnesh Patel
> > ---
> >
> > Changes in v3:
> > - Add IS_ENABLED(CONFIG_TIMER_EARLY) for timer_early_get_rate()
> > and timer_early_get_count() functions.
>
> Reviewed-by: Rick C
Hi Tom
> This patch adds the necessary configs and docs for FPIOA and GPIO support
> on the K210.
>
> The board does not boot unless CONSOLE_LOGLEVEL is set to a non-default
> value . It also boots when the tree is dirty (and CONSOLE_LOGLEVEL is not
> changed). It also boots when changes are made
540/cache.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Rick Chen
t;info.size is of type 'size_t' but the length modifier is l.
> Fix this by casting priv->info.size. Note 'z' cannot be used as
> the modifier as SPL does not support that.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/ram/sifive/fu540_ddr.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Rick Chen
Hi Sean
> On 8/18/20 11:48 PM, Rick Chen wrote:
> > Hi Tom
> >
> >> This patch adds the necessary configs and docs for FPIOA and GPIO support
> >> on the K210.
> >>
> >> The board does not boot unless CONSOLE_LOGLEVEL is set to a non-default
>
Hi Sean
> Hi Sean
>
> > On 8/18/20 11:48 PM, Rick Chen wrote:
> > > Hi Tom
> > >
> > >> This patch adds the necessary configs and docs for FPIOA and GPIO support
> > >> on the K210.
> > >>
> > >> The board does not boo
/riscv/include/asm/sbi.h | 2 +
> arch/riscv/lib/sbi.c | 36
> cmd/Kconfig | 6 +++
> cmd/riscv/Makefile | 1 +
> cmd/riscv/sbi.c | 82
> 5 files changed, 127 insertions(+)
> create mode 100644 cmd/riscv/sbi.c
Reviewed-by: Rick Chen
Tested-by: Rick Chen
Pragnesh Patel
> ---
> cmd/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
ory() new parameter
>
> ---
>
> (no changes since v1)
>
> arch/riscv/lib/fdt_fixup.c | 2 +-
> include/fdtdec.h | 5 +++--
> lib/fdtdec.c | 10 --
> lib/optee/optee.c | 2 +-
> test/dm/fdtdec.c | 6 +++---
> 5 files changed, 16 insertions(+), 9 deletions(-)
Acked-by: Rick Chen
Hi Sean
> On 8/20/20 4:47 AM, Rick Chen wrote:
> > Hi Sean
> >
> >> Hi Sean
> >>
> >>> On 8/18/20 11:48 PM, Rick Chen wrote:
> >>>> Hi Tom
> >>>>
> >>>>> This patch adds the necessary configs and docs for
| 2 +-
> arch/riscv/lib/sifive_clint.c | 2 +-
> arch/riscv/lib/timer.c| 50 +++
> drivers/timer/riscv_timer.c | 2 +-
> 5 files changed, 54 insertions(+), 3 deletions(-)
> create mode 100644 arch/riscv/lib/timer.c
>
> --
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