> From: Heinrich Schuchardt <heinrich.schucha...@canonical.com> > Sent: Sunday, October 02, 2022 10:21 AM > To: Tom Rini <tr...@konsulko.com>; Leo Yu-Chi Liang(梁育齊) > <ycli...@andestech.com>; Rick Jian-Zhi Chen(陳建志) <r...@andestech.com>; Simon > Glass <s...@chromium.org> > Cc: u-boot@lists.denx.de; Alexandre Ghiti <alexandre.gh...@canonical.com>; > Aurelien Jarno <aurel...@aurel32.net>; Bin Meng <bmeng...@gmail.com>; > Heinrich Schuchardt <heinrich.schucha...@canonical.com>; Heiko Stuebner > <he...@sntech.de>; Christian Stewart <christ...@paral.in> > Subject: [PATCH v3 3/3] riscv: Fix build against binutils 2.38 > > From: Alexandre Ghiti <alexandre.gh...@canonical.com> > > The following description is copied from the equivalent patch for the Linux > Kernel proposed by Aurelien Jarno: > > >From version 2.38, binutils default to ISA spec version 20191213. This > means that the csr read/write (csrr*/csrw*) instructions and fence.i > instruction has separated from the `I` extension, become two standalone > extensions: Zicsr and Zifencei. As the kernel uses those instruction, this > causes the following build failure: > > arch/riscv/cpu/mtrap.S: Assembler messages: > arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' > arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' > arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' > arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' > > Signed-off-by: Alexandre Ghiti <alexandre.gh...@canonical.com> > Reviewed-by: Bin Meng <bmeng...@gmail.com> > Tested-by: Heinrich Schuchardt <heinrich.schucha...@canonical.com> > Tested-by: Heiko Stuebner <he...@sntech.de> > Tested-by: Christian Stewart <christ...@paral.in> > --- > v3: > no change > --- > arch/riscv/Makefile | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-)
Reviewed-by: Rick Chen <r...@andestech.com>
