Describe the DDR vtt regulator on evm
This is a pending upstream kernel updates as of v6.3-rc6.
Signed-off-by: Nishanth Menon
---
Sent to kernel.org
https://lore.kernel.org/linux-devicetree/20230414073328.381336-1...@ti.com/
I skipped doing the regulator renaming etc, it is just churn
un
Add main_uart1 description in sk devicetree.
This is a pending upstream kernel updates as of v6.3-rc6.
Signed-off-by: Nishanth Menon
---
Sent to kernel.org
https://lore.kernel.org/linux-devicetree/20230414073328.381336-1...@ti.com/
arch/arm/dts/k3-am642-sk.dts | 13 +
1 file
Fix the pinmux pull polarity.
This is a pending upstream kernel updates as of v6.3-rc6.
Signed-off-by: Nishanth Menon
---
Sent to kernel.org
https://lore.kernel.org/linux-devicetree/20230414073328.381336-1...@ti.com/
arch/arm/dts/k3-am642-sk.dts | 16 +---
1 file changed, 9
Add main_uart1 description in evm devicetree.
This is a pending upstream kernel updates as of v6.3-rc6.
Signed-off-by: Nishanth Menon
---
Sent to kernel.org
https://lore.kernel.org/linux-devicetree/20230414073328.381336-1...@ti.com/
arch/arm/dts/k3-am642-evm.dts | 13 +
1 file
Drop the i2c and mux description, since we have it on main board dts.
Signed-off-by: Nishanth Menon
---
Again causes a bisect break at this point due to some weird dependency
with r5 which I could not cleanly resolve.
arch/arm/dts/k3-am642-evm-u-boot.dtsi | 15 ---
1 file changed
;main_mdio1_pins_default
> + &main_rgmii1_pins_default>;
Why not do this hack in board.dts and mark it due to MDIO limitation?
> + bootph-pre-ram;
> +
> + cpsw-phy-sel@04044 {
> + compatible = "ti,am64-phy-gmii-sel";
> + reg = <0x00 0x00104044 0x00 0x8>;
> + bootph-pre-ram;
> + };
> +};
> --
> 2.40.0
>
--
Regards,
Nishanth Menon
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sil.c | 2 +
> 12 files changed, 729 insertions(+), 6 deletions(-)
> create mode 100644 drivers/dma/ti/k3-psil-am62a.c
>
>
> base-commit: a25dcda452bf6a6de72764a8d990d72e5def643d
> --
> 2.40.0
>
--
Regards,
Nishanth Menon
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phy driver, drop
the api
* picked reviewed by for the rgmii
V2: https://lore.kernel.org/all/20230414042433.3436425-1...@ti.com/
V1: https://lore.kernel.org/all/20230413180713.2922524-1...@ti.com/
Nishanth Menon (3):
net: phy: dp83867: Explicitly check against sgmii
net: phy: Drop phy_interfac
by: Marek Behún
Signed-off-by: Nishanth Menon
---
Changes since V2:
* picked up reviewed-by
* s/was'nt/wasn't/g in commit message, minor rewording.
V2: https://lore.kernel.org/r/20230414042433.3436425-3...@ti.com
V1: https://lore.kernel.org/r/20230413180713.2922524-3...@ti.com
include/
very different that it makes no sense to
provide a helper wrapper in the hope of reuse for phy drivers.
Reported-by: Tom Rini
Suggested-by: Marek Vasut
Suggested-by: Marek Behún
Link: https://lore.kernel.org/all/20230414103852.38705065@dellmb/
Signed-off-by: Nishanth Menon
---
Changes Since v
/b82ac325-4818-8e72-054b-640268dbf...@mailbox.org/
Signed-off-by: Nishanth Menon
---
Changes since v2:
* New patch.
drivers/net/phy/dp83867.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index b861bf7cef36..7111e36aa0d0 100644
On 13:42-20230417, Roger Quadros wrote:
>
>
> On 14/04/2023 10:57, Nishanth Menon wrote:
> > Fix the pinmux pull polarity.
> >
> > This is a pending upstream kernel updates as of v6.3-rc6.
> >
> > Signed-off-by: Nishanth Menon
> > ---
> > Se
tag to upstream merge, things are'nt
really final and patches still have been dropped and/or modified (not
typically, but have happened)
b) the delay between a tag and final merge is just a few weeks
We should hold the master tag as baseline at least till things settle
down, prior to relaxing rules to what is reasonable.
--
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Nishanth Menon
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On 14:45-20230418, Manorit Chawdhry wrote:
> Hi Nishanth,
>
> On 14/04/23 13:27, Nishanth Menon wrote:
> > Use am642-sk.dts to represent the Board and selectively enable/override
> > the configurations necessary. And since am642-sk-u-boot.dtsi also needs
> > to setup co
t; + !strncmp(fdt_get_name(blob, subnode, &len), "l3cache", 7) ||
> + !strncmp(fdt_get_name(blob, subnode, &len), "tifs", 4)) {
I would probably move the tifs check above the l3cache check.
> fdt_del_node(blob, su
umar (1):
> configs: j721s2_evm_r5_defconfig: Increase malloc pool size in DRAM
>
Not sure what happened to your patches, but they are missing sequence
numbering and versioning info.
--
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Nishanth Menon
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, rate);
>
> -#ifdef CONFIG_K3_AVS0
> - k3_avs_notify_freq(clk->id, clk->data, rate);
> -#endif
> -
Why drop from here? we do have am64 and am65 that use ti-sci, correct?
> ret = cops->set_freq(sci, clk->id, clk->data, 0, rate, ULONG_MAX);
> if (ret) {
> dev_err(clk->dev, "%s: set_freq failed (%d)\n", __func__, ret);
> --
> 2.34.1
>
--
Regards,
Nishanth Menon
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5.1044560-4...@ti.com
That should take care of this in the kernel sync next time around.
But, for next:
Reviewed-by: Nishanth Menon
>
> > ---
> >
> > (no changes since v1)
> >
> > arch/arm/dts/k3-am625-sk-u-boot.dtsi | 8
> > 1 file changed,
xt revision queued by b4 also has the same problem. Not
> exactly sure what went wrong with b4 but would be careful next time.
> Thanks for pointing it out.
Please resubmit.
--
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Nishanth Menon
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F2 < F1), then Seq 1 is valid. But if V2 > V1 (F2 >
F1) Seq 2 is valid.
We seem to ignore this constraint. Can you explain this in the commit
message?
clk-sci.c seems to use Seq 2, vs this patch seems to take Seq 1.
> return new_rate;
> }
>
> --
> 2.34.1
>
--
Regards,
Nishanth Menon
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On 22:58-20230919, Kumar, Udit wrote:
> Hi Nishanth,
>
> On 9/19/2023 9:07 PM, Nishanth Menon wrote:
> > On 19:34-20230919, Udit Kumar wrote:
> > > AVS is enabled at R5 SPL stage, on few platforms like J721E
> > > and J7200 clk-k3 is used instead if clk-sci driver
nmuxes from r5 and -u-boot.dtsi files and
> include k3-j721s2-common-proc-board.dts for Linux fixes to propagate
> to U-boot.
>
Please fix your $subject arm: dts: k3-j721s2:
--
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Nishanth Menon
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nmuxes from r5 and -u-boot.dtsi files and
> include k3-am68-sk-base-board.dts for Linux fixes to propagate
> to U-boot.
>
Please fix your $subject: arm: dts: k3-am68: ...
--
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Nishanth Menon
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g ti_sci_clk_set_rate(struct clk *clk, ulong
> rate)
> return ret;
> }
>
> + if (set_avs_after_clock && IS_ENABLED(CONFIG_K3_AVS0))
> + k3_avs_notify_freq(clk->id, clk->data, rate);
> +
> return rate;
> }
>
> --
> 2.34.1
>
First look - it looks fine, but note: these are two different patches.
the clk-sci.c is a fix for an existing implementation and clk-k3.c is a
new feature addition. please don't mix the two.
--
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| 7 +++
> arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi | 14 ++
> 3 files changed, 28 insertions(+)
Get this as part of kernel dt sync.
--
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ents;
> - pinctrl-names = "default";
> - pinctrl-0 = <&main_mmc1_pins_default>;
> - clock-names = "clk_xin";
> - clocks = <&clk_200mhz>;
> - ti,driver-strength-ohm = <50>;
> + clock-frequency = <1920>;
- ret = ti_sci_cmd_get_revision(&info->handle);
> -
> INIT_LIST_HEAD(&info->dev_list);
>
> - return ret;
> + return 0;
> }
>
> /**
> --
> 2.34.1
>
--
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Nishanth Menon
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before using the timer, move clk_k3 driver
> probe before k3_sysfw_loader to ensure we have all necessary clocks set
> up before.
>
> Signed-off-by: Neha Malcom Francis
Reviewed-by: Nishanth Menon
> ---
> arch/arm/mach-k3/j721e_init.c | 24
> 1 f
On 16:09-20230922, Neha Malcom Francis wrote:
> U-Boot uses mcu_timer0 as the tick-timer, so add it to device list.
>
> Signed-off-by: Neha Malcom Francis
> Reviewed-by: Manorit Chawdhry
Reviewed-by: Nishanth Menon
[...]
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) /
uct udevice *dev,
> }
>
> spm->scfg = devfdt_get_addr_name(dev, "scfg");
> - if (spm->rt == FDT_ADDR_T_NONE) {
> + if (spm->scfg == FDT_ADDR_T_NONE) {
> dev_err(dev, "No reg property for Secure Cfg base\n");
>
50-800-800.dtsi
> new file mode 100644
> index 00..74693d12e1
> --- /dev/null
> +++ b/arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi
> @@ -0,0 +1,2190 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * This file was generated with the
> + * AM62x SysConfig DDR Subsy
gned {
> + filename = AM62_LP_SK_DTB;
> +};
> +
> +&spl_am625_sk_dtb {
> + filename = SPL_AM62_LP_SK_DTB;
> +};
> +
> +&am625_sk_dtb {
> + filename = AM62_LP_SK_DTB;
> +};
> +
> +#endif
> --
> 2.25.1
>
Squash this to the u-boot.dtsi ?
--
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pxe dhcp
> +boot=mmc
> +mmcdev=1
> +bootpart=1:2
> +bootdir=/boot
> +rd_spec=-
> +
> +splashfile=ti.gz
> +splashimage=0x8020
> +splashpos=m,m
> +splashsource=sf
Why dont we use the am62.env ? What is here to customize?
> --
> 2.25.1
>
--
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Nishanth Menon
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ff-by: Nitin Yadav
> ---
[...]
> +#include "k3-am625-sk-binman.dtsi"
Might be a good time to refactor and squash sk-binman.dtsi to
u-boot.dtsi ?
[...]
--
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ch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi
> create mode 100644 arch/arm/dts/k3-am62x-r5-sk-common.dtsi
> create mode 100644 arch/arm/dts/k3-am62x-sk-common-u-boot.dtsi
> create mode 100644 board/ti/am62x/am62x_lpsk_a53.config
> create mode 100644 board/ti/am62x/am62x_lpsk_r5.config
>
after=90c81f407dd4a7747385b10f9b8f732202c45cde+104&branch=next&qualified_name=refs%2Fheads%2Fnext
Can you send delta patches based off u-boot next?
--
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On 15:00-20230928, Nitin Yadav wrote:
> Hi,
>
> On 27/09/23 17:22, Nishanth Menon wrote:
> > On 13:51-20230927, Nitin Yadav wrote:
> >> The AM62x LP SK board is similar to the AM62x SK board,
> >> but has some significant changes that requires different
> >&
On 15:09-20230928, Nitin Yadav wrote:
>
>
> On 27/09/23 17:26, Nishanth Menon wrote:
> > On 13:51-20230927, Nitin Yadav wrote:
> >> Add k3-am62x-r5-sk-common to include nodes common for R5
> >> SPL from k3-am625-r5-sk for AM62x SoC based boards. Add
> >>
m node as pre-reloc after
relocation")
Reported-by: Roger Quadros
Signed-off-by: Nishanth Menon
---
Based on Roger's series:
https://lore.kernel.org/all/20230929134646.214781-1-rog...@kernel.org/
Based on:
next e29b932aa07f Merge branch
'2023-09-30-Kconfig-u
h-all;
> };
>
> &cpsw_port2 {
> diff --git a/arch/arm/dts/k3-am642-r5-evm.dts
> b/arch/arm/dts/k3-am642-r5-evm.dts
> index 73461f8f6c..696735d8e2 100644
> --- a/arch/arm/dts/k3-am642-r5-evm.dts
> +++ b/arch/arm/dts/k3-am642-r5-evm.dts
> @@ -40,6 +40,10 @@
> };
> };
>
> +&vtt_supply {
> + bootph-pre-ram;
> +};
> +
> &cbass_main {
> sysctrler: sysctrler {
> compatible = "ti,am654-system-controller";
> @@ -53,6 +57,10 @@
> bootph-pre-ram;
> };
>
> +&cbass_mcu {
> + bootph-pre-ram;
> +};
A bit superfluous, but ok - we just need this atm for esm.
> +
> &mcu_esm {
> bootph-pre-ram;
> };
> --
> 2.34.1
>
Reviewed-by: Nishanth Menon
--
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5-evm.dts
> b/arch/arm/dts/k3-am642-r5-evm.dts
> index 696735d8e2..64b3c3af63 100644
> --- a/arch/arm/dts/k3-am642-r5-evm.dts
> +++ b/arch/arm/dts/k3-am642-r5-evm.dts
> @@ -74,6 +74,14 @@
> ti,secure-host;
> };
>
> +&vtt_supply {
> + bootph-pre-ram;
> +};
> +
> +&memorycontroller {
> + vtt-supply = <&vtt_supply>;
> +};
> +
> &sdhci0 {
> clocks = <&clk_200mhz>;
> clock-names = "clk_xin";
> --
> 2.34.1
>
Reviewed-by: Nishanth Menon
--
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Nishanth Menon
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bootph-all;
> };
>
> &mdio1_pins_default {
> - bootph-pre-ram;
> + bootph-all;
> };
>
> &cpsw3g_phy1 {
> - bootph-pre-ram;
> + bootph-all;
> };
>
> &main_usb0_pins_default {
> - bootph-pre-ram;
> + bootph-all;
> };
>
> &serdes_ln_ctrl {
> @@ -141,25 +137,25 @@
> };
>
> &usbss0 {
> - bootph-pre-ram;
> + bootph-all;
> };
>
> &usb0 {
> - bootph-pre-ram;
> + bootph-all;
> };
>
> &serdes_wiz0 {
> - bootph-pre-ram;
> + bootph-all;
> };
>
> &serdes0_usb_link {
> - bootph-pre-ram;
> + bootph-all;
> };
>
> &serdes0 {
> - bootph-pre-ram;
> + bootph-all;
> };
>
> &serdes_refclk {
> - bootph-pre-ram;
> + bootph-all;
> };
> --
> 2.34.1
>
Reviewed-by: Nishanth Menon
--
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psw3g_phy1 {
> + bootph-all;
> +};
> +
> +&rgmii1_pins_default {
> + bootph-all;
> +};
> +
> +&rgmii2_pins_default {
> + bootph-all;
> +};
> +
> &cpsw3g {
> bootph-all;
>
> @@ -100,6 +132,10 @@
> };
> };
>
> +&phy_gmii_sel {
> + bootph-all;
> +};
> +
> &cpsw_port2 {
> bootph-all;
> };
> --
> 2.34.1
>
Reviewed-by: Nishanth Menon
--
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Nishanth Menon
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bootph-pre-ram;
> + bootph-all;
>
> partitions {
> - bootph-pre-ram;
> + bootph-all;
>
> partition@3fc {
> - bootph-pre-ram;
> + bootph-all;
> };
> };
> };
> };
>
> &cpsw3g {
> - bootph-pre-ram;
> + bootph-all;
> };
>
> &cpsw_port1 {
> - bootph-pre-ram;
> + bootph-all;
> };
>
> &cpsw_port2 {
> --
> 2.34.1
>
Reviewed-by: Nishanth Menon
--
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p;cpsw3g_phy0 {
> + bootph-all;
> +};
> +
> +&cpsw3g_phy1 {
> + bootph-all;
> +};
> +
> +&main_rgmii1_pins_default {
> + bootph-all;
> +};
> +
> +&main_rgmii2_pins_default {
> + bootph-all;
> +};
> +
> +&phy_gmii_sel {
> + bootph-all;
> +};
> +
> &cpsw3g {
> bootph-all;
> + ethernet-ports {
> + bootph-all;
> + };
> };
>
> &cpsw_port1 {
> --
> 2.34.1
>
Reviewed-by: Nishanth Menon
--
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ard/ti/k3.rst b/doc/board/ti/k3.rst
> index ec447358ac..60aacdac99 100644
> --- a/doc/board/ti/k3.rst
> +++ b/doc/board/ti/k3.rst
> @@ -35,6 +35,7 @@ K3 Based SoCs
> am65x_evm
> j7200_evm
> j721e_evm
> + j784s4_evm
>
> Boot Flow Overview
> --
> --
> 2.34.1
>
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am69-sk dts from linux kernel
error: sha1 information is lacking or useless (arch/arm/dts/Makefile).
error: could not build fake ancestor
Patch failed at 0010 arm: dts: Introduce am69-sk dts from linux kernel
hint: Use 'git am --show-current-patch=diff' to see the failed
ti/k3-j784s4-evm.dtb; fi;
What function is this doing? Why not leave it for defaults?
Just use include/env/ti/default_findfdt.env and be done with it?
> setenv fdtfile ${name_fdt}
> --
> 2.34.1
>
--
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c), usb pxe dhcp.
> +boot=mmc
> +mmcdev=1
> +dorprocboot=1
> +bootpart=1:2
> +bootdir=/boot
> +rd_spec=-
> +
> +rproc_fw_binaries= 2 /lib/firmware/j784s4-main-r5f0_0-fw 3
> /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5
> /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7
> /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9
> /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11
> /lib/firmware/j784s4-c71_3-fw
No clue what the above mess is.
> +
> +splashfile=ti.gz
> +splashimage=0x8200
> +splashpos=m,m
> +splashsource=mmc
You have splash screen support?
--
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Nishanth Menon
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"ti,am654-r5fss"},
> { .compatible = "ti,j721e-r5fss"},
> { .compatible = "ti,j7200-r5fss"},
> + { .compatible = "ti,j721s2-r5fss"},
> {}
> };
>
> --
> 2.34.1
>
--
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#define K3_SOC_ID(id, ID) \
> static inline bool soc_is_##id(void) \
> --
> 2.34.1
>
Reviewed-by: Nishanth Menon
--
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Nishanth Menon
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_DEVICE_UART:
> + return BOOT_DEVICE_UART;
> + case BACKUP_BOOT_DEVICE_ETHERNET:
> + return BOOT_DEVICE_ETHERNET;
> + case BACKUP_BOOT_DEVICE_MMC2:
> + {
> + u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
> + MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
> + if (port == 0x0)
> + return BOOT_DEVICE_MMC1;
> + return BOOT_DEVICE_MMC2;
> + }
> + case BACKUP_BOOT_DEVICE_SPI:
> + return BOOT_DEVICE_SPI;
> + case BACKUP_BOOT_DEVICE_I2C:
> + return BOOT_DEVICE_I2C;
> + }
> +
> + return BOOT_DEVICE_RAM;
> +}
> +
> +static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
> +{
> + u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
> + WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
> +
> + bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
> + BOOT_MODE_B_SHIFT;
> +
> + if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI ||
> + bootmode == BOOT_DEVICE_XSPI)
> + bootmode = BOOT_DEVICE_SPI;
> +
> + if (bootmode == BOOT_DEVICE_MMC2) {
> + u32 port = (main_devstat &
> + MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
> +MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
> + if (port == 0x0)
> + bootmode = BOOT_DEVICE_MMC1;
> + }
> +
> + return bootmode;
> +}
> +
> +u32 spl_spi_boot_bus(void)
> +{
> + u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
> + u32 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
> + u32 bootmode = ((wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
> + WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT) |
> + ((main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
> BOOT_MODE_B_SHIFT);
> +
> + return (bootmode == BOOT_DEVICE_QSPI) ? 1 : 0;
> +}
> +
> +u32 spl_boot_device(void)
> +{
> + u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
> + u32 main_devstat;
> +
> + if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
> + printf("ERROR: MCU only boot is not yet supported\n");
> + return BOOT_DEVICE_RAM;
> + }
> +
> + /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
> + main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
> +
> + if (bootindex == K3_PRIMARY_BOOTMODE)
> + return __get_primary_bootmedia(main_devstat, wkup_devstat);
> + else
> + return __get_backup_bootmedia(main_devstat);
> +}
> --
> 2.34.1
>
I think there is an opportunity to merge j721s2 and j784s4.. but i am
not expert on either of the chips to better comment.
--
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Nishanth Menon
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to make syncs easier in the future. unless there is a strong
reasoning on an alternate rationale, i'd rather not mess with the flow
in play already.
Personally though, I am miffed at a breaking change of this form :(
--
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Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693
gt; > NAK.
> >
> > Do this cleanup in the context of the new platform addition - when you
> > get it in the kernel first.
>
> I haven't planned to have a kernel dt for am62sip as there is only
> difference is DDR size which will be taken care by U-boot.
We can cross t
t;&dmsc>;
> ti,sci-proc-id = <32>;
> ti,sci-host-id = <10>;
> - bootph-pre-ram;
> + bootph-all;
> };
> dm_tifs: dm-tifs {
> @@ -41,7 +41,7 @@
> mbox-names = "rx", "tx"
ecure boot is done so that people don't end up
huh? the code seems to blindly call the remove_fwl_configs(cbass_hc_cfg0_fwls,
ARRAY_SIZE(cbass_hc_cfg0_fwls));
where is the distinction of HS vs GP here? This implementation looks
completely broken to me at least.. please correct what I missed he
oard/ti/am62x/am62x.env
> > +++ b/board/ti/am62x/am62x.env
> > @@ -8,7 +8,7 @@ args_all=setenv optargs ${optargs}
> > earlycon=ns16550a,mmio32,0x0280
> > ${mtdparts}
> > run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
> > -boot_targets=ti_mmc mmc0 mmc1 us
+ b/include/configs/am64x_evm.h
> @@ -10,8 +10,6 @@
> #define __CONFIG_AM642_EVM_H
>
> #include
Do we really need this?
> -#include
> -#include
> #include
OR this?
> #include
you dont need k3_dfu.h either. the env setup is already in
board/ti/am64x/am64x.env (
On 16:23-20231004, Roger Quadros wrote:
> ti_mmc is not a valid boot_target for standard boot flow so
> remove it. Prefer mmc1 (sd-card) over mmc0 (emmc).
>
> Signed-off-by: Roger Quadros
Reviewed-by: Nishanth Menon
> ---
> board/ti/am62x/am62x.env | 2 +-
> 1 file chang
w_binaries?, it is parsed by u-boot to find all
> the firmwares
> from filesystem for doing early boot of firmwares.
Does stdboot support this?
--
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Nishanth Menon
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egions are different for J784S4 from J721S2,
> and on the hardware side also, i.e. J784S4 has 4x8G DDR slots,
> so how can we bring it in same CONFIG as J721S2?
Is'nt that what device tree is for? what harm do we run into if
we define the common super set in the common file?
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t.dtsi as 'bootph-all'.
>
> [1] 9e644284ab812 ("dm: core: Report bootph-pre-ram/sram node as pre-reloc
> after relocation")
>
> Signed-off-by: Jan Kiszka
Reviewed-by: Nishanth Menon
> ---
> .../dts/k3-am65-iot2050-common-u-boot.dtsi| 44 +-
On 10:29-20231005, Manorit Chawdhry wrote:
> Hi Nishanth,
>
> On 07:24-20231004, Nishanth Menon wrote:
> > On 10:43-20231004, Manorit Chawdhry wrote:
> >
> > > These are required to remove the firewall configurations that are done
> > > by ROM, those are
On 06:18-20231005, Jan Kiszka wrote:
> On 04.10.23 14:15, Nishanth Menon wrote:
> > On 22:26-20231003, Jan Kiszka wrote:
> >> From: Jan Kiszka
> >>
> >> Since commit [1] A53 u-boot proper is broken. This is because nodes
> >> marked as 'bootph-
0mhz {
> - compatible = "fixed-clock";
> - #clock-cells = <0>;
> - clock-frequency = <2>;
> - bootph-pre-ram;
> + bootph-all;
Here and else where in the r5 file: why switch from pre-ram to bootph-all
? dont we need these prior to ddr initialization?
[...]
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Nishanth Menon
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2_EVM_H
>
> -#include
> -#include
> -#include
> -#include
> -#include
> -
> -/* DDR Configuration */
> -#define CFG_SYS_SDRAM_BASE1 0x88000
> -
> /* Now for the remaining common defines */
> #include
>
> --
> 2.34.1
>
Reviewed-by: Nishanth Menon
--
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Nishanth Menon
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om/u-boot/u-boot/commit/7e5b6f1cff846218b824a4d906e2831c15864a53
https://lore.kernel.org/all/3376a0eb-57f4-416a-b4b8-86cee769d...@siemens.com/
etc..
as a rule of thumb: u-boot.dtsi uses bootph-all; r5-xyz.dts uses booth-pre-ram
Where this failed completely is when A53 started using booth-pre-ram in
wh
On 12:36-20231005, Tom Rini wrote:
> On Thu, Oct 05, 2023 at 09:19:48AM -0500, Andrew Davis wrote:
> > On 10/4/23 8:54 AM, Nishanth Menon wrote:
> > > On 08:48-20231004, Andrew Davis wrote:
> > > > On 10/4/23 8:23 AM, Roger Quadros wrote:
> > > > > t
CONFIG_DISTRO_DEFAULTS already?
So, all we are picking up in effect is really CFG_SYS_SDRAM_BASE - which
is consistent across platforms.
--
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Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5
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On 12:10-20231005, Nishanth Menon wrote:
> On 12:36-20231005, Tom Rini wrote:
> > On Thu, Oct 05, 2023 at 09:19:48AM -0500, Andrew Davis wrote:
> > > On 10/4/23 8:54 AM, Nishanth Menon wrote:
> > > > On 08:48-20231004, Andrew Davis wrote:
> > > >
On 12:22-20231005, Andrew Davis wrote:
> On 10/5/23 12:16 PM, Nishanth Menon wrote:
> > On 12:10-20231005, Nishanth Menon wrote:
> > > On 12:36-20231005, Tom Rini wrote:
> > > > On Thu, Oct 05, 2023 at 09:19:48AM -0500, Andrew Davis wrote:
> > > >
.dtsi as 'bootph-all'.
Fixes: 69b19ca67bcb ("arm: dts: k3-j721e: Sync with v6.6-rc1")
Cc: Neha Francis
Signed-off-by: Nishanth Menon
---
The original patch was reviewed prior to commit 9e644284ab81
However the recent break in u-boot requires fixup to maintain sanity.
Neha
or eMMC/SD
>
> - fix secure proxy node
>
> mcu_secproxy changed to used secure_prxy_mcu which is already
> defined in k3-j7200-mcu-wakeup.dtsi
>
> - removed &mcu_ringacc property override since they're present in
> v6.6-rc1
>
> Signed-off-by: Reid Ton
On 09:46-20231006, Manorit Chawdhry wrote:
> Hi Nishanth,
>
> On 06:26-20231005, Nishanth Menon wrote:
> > On 10:29-20231005, Manorit Chawdhry wrote:
> > > Hi Nishanth,
> > >
> > > On 07:24-20231004, Nishanth Menon wrote:
> &g
ddr-evm-lp4-4266.dtsi
> index a0285ce0520e..5a6f9b11b8e3 100644
> --- a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi
> +++ b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi
Sigh. Hope to see a fix some time.
Reviewed-by: Nishanth Menon
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Key (0xDDB5849D1736249D)
scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi#n27
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi#n15
we need to fix it.
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On 14:26-20230427, Bryan Brattlof wrote:
> From: Nishanth Menon
>
> Add erratum i2327 work around for initialization for RTC
> interrupt where interrupt is stuck for ever at startup. Unfortunately,
> this workaround needs to be applied under 1 second of boot.
>
> Signed-o
d hiding this. Same story for TIFS and ATF, they
> > use some variable amount of the end of SRAM.
> >
> Ah, I have other view.
>
> We shrunk SRAM size already, having reserved node on top of SRAM
>
> is good as removing this.
How about we do this:
a) Start by discussi
On 09:43-20230503, Udit Kumar wrote:
> From: Nishanth Menon
>
> Sync with Kernel.org v6.3-rc6 tag.
we are few days away from rc1 tag. I'd rather we refresh.
>
> Signed-off-by: Nishanth Menon
> ---
> arch/arm/dts/k3-j7200-common-proc-board.dts | 63 +++--
98, PIN_INPUT, 0) /* (L4)
> MCU_MDIO0_MDIO */
> + J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1)
> MCU_MDIO0_MDC */
> + J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4)
> MCU_MDIO0_MDIO */
> >;
> };
> };
> --
> 2.34.1
>
Not in upstream k.org. NAK.
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> };
>
> +&wkup_i2c0 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&wkup_i2c0_pins_default>;
> + clock-frequency = <40>;
> +
> + eeprom@50 {
> + compatible = "atmel,24c256";
> + reg = <0x50>;
> + };
> +};
> +
> &ospi0 {
> pinctrl-names = "default";
> pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
> --
> 2.34.1
>
--
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lks 74 2>;
> + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
> + ti,timer-pwm;
> + };
> +
> + mcu_timer5: timer@4045 {
> + compatible = "ti,am654-timer";
> + status = "reserved";
> + reg = <0x00 0x4045 0x00 0x400>;
> + interrupts = ;
> + clocks = <&k3_clks 75 1>;
> + clock-names = "fck";
> + assigned-clocks = <&k3_clks 75 1>;
> + assigned-clock-parents = <&k3_clks 75 2>;
> + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
> + ti,timer-pwm;
> + };
> +
> + mcu_timer6: timer@4046 {
> + compatible = "ti,am654-timer";
> + status = "reserved";
> + reg = <0x00 0x4046 0x00 0x400>;
> + interrupts = ;
> + clocks = <&k3_clks 76 1>;
> + clock-names = "fck";
> + assigned-clocks = <&k3_clks 76 1>;
> + assigned-clock-parents = <&k3_clks 76 2>;
> + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
> + ti,timer-pwm;
> + };
> +
> + mcu_timer7: timer@4047 {
> + compatible = "ti,am654-timer";
> + status = "reserved";
> + reg = <0x00 0x4047 0x00 0x400>;
> + interrupts = ;
> + clocks = <&k3_clks 77 1>;
> + clock-names = "fck";
> + assigned-clocks = <&k3_clks 77 1>;
> + assigned-clock-parents = <&k3_clks 77 2>;
> + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
> + ti,timer-pwm;
> + };
> +
> + mcu_timer8: timer@4048 {
> + compatible = "ti,am654-timer";
> + status = "reserved";
> + reg = <0x00 0x4048 0x00 0x400>;
> + interrupts = ;
> + clocks = <&k3_clks 78 1>;
> + clock-names = "fck";
> + assigned-clocks = <&k3_clks 78 1>;
> + assigned-clock-parents = <&k3_clks 78 2>;
> + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
> + ti,timer-pwm;
> + };
> +
> + mcu_timer9: timer@4049 {
> + compatible = "ti,am654-timer";
> + status = "reserved";
> + reg = <0x00 0x4049 0x00 0x400>;
> + interrupts = ;
> + clocks = <&k3_clks 79 1>;
> + clock-names = "fck";
> + assigned-clocks = <&k3_clks 79 1>;
> + assigned-clock-parents = <&k3_clks 79 2>;
> + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
> + ti,timer-pwm;
> + };
> +
> mcu_conf: syscon@40f0 {
> compatible = "syscon", "simple-mfd";
> reg = <0x00 0x40f0 0x00 0x2>;
> --
> 2.34.1
>
--
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Nishanth Menon
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rview". For handling beyond multiplexing, the
> driver support for timer cascading should be likely be handled via the
> clock framework.
>
> Cc: Nishanth Menon
> Cc: Vignesh Raghavendra
> Cc: Tony Lindgren
> Signed-off-by: Udit Kumar
> ---
> arch/arm/dts/k3-j7200
411a5 100644
> --- a/arch/arm/dts/k3-j7200-som-p0.dtsi
> +++ b/arch/arm/dts/k3-j7200-som-p0.dtsi
> @@ -128,12 +128,15 @@
> };
>
> &main_pmx0 {
> +
> main_i2c0_pins_default: main-i2c0-pins-default {
> + bootph-pre-ram;
> pinctrl-single,pins = <
> J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL
> */
> J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA
> */
> >;
> };
> +
> };
>
> &hbmc {
> --
> 2.34.1
>
a) Once we have the core dts changes in k.org
b) sync u-boot back in. the bootph-pre-ram etc changes can come in via
u-boot.dtsi at this point
c) then get the ph-pre-ram etc changes into k.org
d) drop them from u-boot.dtsi etc.
But, NOT yet.
--
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Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5
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connected as a slave to MCU_MCSPI2
> by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out
> externally.
>
> Signed-off-by: Vaishnav Achath
> Reviewed-by: Keerthy
> Link: https://lore.kernel.org/r/20230321082827.14274-3-vaishna...@ti.com
> Signed-off-by: Nis
CONFIG_SYS_SPL_MALLOC_SIZE=0x100
> CONFIG_SPL_EARLY_BSS=y
> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
> -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
> CONFIG_SPL_DMA=y
> CONFIG_SPL_ENV_SUPPORT=y
> CONFIG_SPL_FS_EXT4=y
> --
> 2.34.1
>
--
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Nishanth Menon
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status = "reserved";
> reg = <0x1f 0x1>;
> };
>
> l3cache-sram@20 {
> + status = "reserved";
> reg = <0x20 0x20>
/*(F28)
> WKUP_GPIO0_7.WKUP_UART0_RTSn*/
> + J721S2_WKUP_IOPAD(0x0b0, PIN_INPUT, 0) /* (D28)
> WKUP_UART0_RXD */
> + J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27)
> WKUP_UART0_TXD */
> + >;
> + };
NAK, not on k.org master. Send and get accepted in
me) that needs explanation in a single doc without needing to dig
through commit messages and variables and defconfigs..
Documentation should clearly indicate what parameters from:
* binman configuration.
* various config header files
* defconfig
We should explain the rationale, variations (HS-SE for example: if any
or if not any) - including risks such as stack-heap collisions. Any
interplay with firmware components in the heterogenous system that folks
need to be careful about needs to be called out as well.
--
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one board that the DDR driver supports
- there are lots of boards that support this + an ecosystem of
tools such as the DDR configuration tool that spits out the DDR
configuration.
All of these should be factored into your patches when you post.
--
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Nishanth Menon
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we
scheme something with a range?
[...]
[1] https://www.kernel.org/doc/html/v6.3/process/email-clients.html
--
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Nishanth Menon
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On 17:25-20230725, Tom Rini wrote:
> On Tue, Jul 25, 2023 at 01:52:50PM -0500, Nishanth Menon wrote:
[..]
> > + /* Set USB0 PHY core voltage to 0.85V */
> > + val = readl(CTRLMMR_USB0_PHY_CTRL);
> > + val &= ~(CORE_VOLTAGE);
> > + writel(val, CTRLMMR_USB0_
On 17:35-20230725, Tom Rini wrote:
> On Tue, Jul 25, 2023 at 01:52:53PM -0500, Nishanth Menon wrote:
>
[...]
> > +
> > +Build procedure:
> > +
> > +1. Trusted Firmware-A:
> > +
> > +.. code-block:: bash
> > +
> > + $ make CROS
On 17:42-20230725, Tom Rini wrote:
> On Tue, Jul 25, 2023 at 04:37:55PM -0500, Nishanth Menon wrote:
> > On 17:25-20230725, Tom Rini wrote:
> > > On Tue, Jul 25, 2023 at 01:52:50PM -0500, Nishanth Menon wrote:
> > [..]
> >
> > > > +
On 10:10-20230726, Nishanth Menon wrote:
> Update the am62 and am625 device-trees from linux v6.3-rc5 This needed the
> followin
Bit of a typo in there :( s/v6.3-rc5/v6.5-rc1 and s/followin/following
I can respin if there are additional comments or if Tom is ok to do a
local
Egorov
Signed-off-by: Nishanth Menon
---
No change since V1
V1: https://lore.kernel.org/all/20230725125856.1807742-3...@ti.com/
Original patch:
https://lore.kernel.org/r/20230406185542.1179073-3-sjo...@collabora.com
arch/arm/mach-k3/am62x/dev-data.c | 1 +
1 file changed, 1 insertion(+)
diff
art of RC Cycle.
RFC: https://lore.kernel.org/u-boot/20230713072019.3153871-1...@ti.com/
Nishanth Menon (1):
arm: dts: k3-am62: Bump dtsi from linux v6.5-rc1
Sjoerd Simons (2):
omap: timer: add ti,am654-timer compatibility
arm: mach-k3: am62: Add timer0 id to the dev list
arch/arm/dts/k3
upport not farther away from it.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5
849D 1736 249D
On 09:36-20230726, Tom Rini wrote:
> On Wed, Jul 26, 2023 at 07:51:15AM -0500, Nishanth Menon wrote:
> > On 10:15-20230726, Maxime Ripard wrote:
> > > On Wed, Jul 26, 2023 at 11:26:05AM +0530, Ravi Gunasekaran wrote:
> > > > On 7/25/23 11:47 PM, Tom Rini wrote:
> &
On 10:15-20230726, Maxime Ripard wrote:
> On Wed, Jul 26, 2023 at 11:26:05AM +0530, Ravi Gunasekaran wrote:
> > On 7/25/23 11:47 PM, Tom Rini wrote:
> > > On Tue, Jul 25, 2023 at 09:09:34AM -0500, Nishanth Menon wrote:
> > >> On 15:56-20230725, Maxime Ripard wrote:
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