Hi Udit
On 04/09/24 09:52, Kumar, Udit wrote:
On 9/3/2024 5:13 PM, Neha Malcom Francis wrote:
Add DT node for PBIST_14 that is responsible for triggering the BIST
self-tests for the MAIN_R5_2_x cores.
Signed-off-by: Neha Malcom Francis
---
dts/upstream/src/arm64/ti/k3-j784s4-main.dtsi
On 04/09/24 09:55, Kumar, Udit wrote:
On 9/3/2024 5:13 PM, Neha Malcom Francis wrote:
Add bootph-pre-ram as well as the clocks and power-domains for
MAIN_R5_2_x. This ensures that LPSC sets the appropriate power and clock
and allows for BIST to turn the cores on and off for running the
self
On 04/09/24 10:35, Kumar, Udit wrote:
On 9/3/2024 5:14 PM, Neha Malcom Francis wrote:
Add a driver for the BIST module which currently includes support for
BIST IPs that trigger PBIST (Memory BIST).
Signed-off-by: Neha Malcom Francis
---
drivers/misc/Kconfig | 8 +
drivers
Hi Udit,
On 05/09/24 17:20, Kumar, Udit wrote:
On 9/5/2024 3:11 PM, Neha Malcom Francis wrote:
On 04/09/24 10:35, Kumar, Udit wrote:
On 9/3/2024 5:14 PM, Neha Malcom Francis wrote:
Add a driver for the BIST module which currently includes support for
BIST IPs that trigger PBIST (Memory
gt;dev, "Command descriptor memory allocation
failed\n");
return -ENOMEM;
Reviewed-by: Neha Malcom Francis
Sorry for the delay in sending out this review, I had reviewed the first few
patches that you had send in an earlier version and looks like this cleanup/fix
was n
ALIGN(datalen, ARCH_DMA_MINALIGN));
+ invalidate_dcache_range(aaddr,
+ ALIGN((uintptr_t)pccb->pdata + datalen,
ARCH_DMA_MINALIGN));
table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY);
buf = pccb->pdata;
Reviewed-
(req_desc, sizeof(*req_desc));
+ ufshcd_cache_flush(prd_table, sizeof(*prd_table) * table_length);
+ ufshcd_cache_flush(req_desc, sizeof(*req_desc));
}
static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb)
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
prepare_prdt_table(hba, pccb);
+ ufshcd_cache_flush(pccb->pdata, pccb->datalen);
+
ufshcd_send_command(hba, TASK_TAG);
+ ufshcd_cache_invalidate(pccb->pdata, pccb->datalen);
+
ocs = ufshcd_get_tr_ocs(hba);
switch (ocs) {
case OCS_SUCCESS:
Reviewe
G1, 1-lane, SLOW-AUTO mode */
ufshcd_init_pwr_info(hba);
--
Thanking You
Neha Malcom Francis
harma
M: Neha Malcom Francis
S:Maintained
I am okay with this!
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
14, 2024 at 10:10:43AM +0530, Neha Malcom Francis wrote:
Hi Andrew
On 11/10/24 01:59, Andrew Davis wrote:
On 10/10/24 1:50 PM, Simon Glass wrote:
Hi Neha,
On Thu, 10 Oct 2024 at 01:09, Neha Malcom Francis wrote:
The message "DRAM: 2 GiB (effective 32 GiB)" can be a little confusi
Hi Udit
On 10/10/24 21:25, Kumar, Udit wrote:
On 10/10/2024 12:39 PM, Neha Malcom Francis wrote:
The message "DRAM: 2 GiB (effective 32 GiB)" can be a little confusing,
modify the message to show exactly what is meant:
"DRAM: 2 GiB (available for U-Boot out of total 32
Hi Tom
On 10/10/24 23:28, Tom Rini wrote:
On Thu, Oct 10, 2024 at 12:39:09PM +0530, Neha Malcom Francis wrote:
The message "DRAM: 2 GiB (effective 32 GiB)" can be a little confusing,
modify the message to show exactly what is meant:
"DRAM: 2 GiB (available for U-Boot out
Hi Andrew
On 11/10/24 01:59, Andrew Davis wrote:
On 10/10/24 1:50 PM, Simon Glass wrote:
Hi Neha,
On Thu, 10 Oct 2024 at 01:09, Neha Malcom Francis wrote:
The message "DRAM: 2 GiB (effective 32 GiB)" can be a little confusing,
modify the message to show exactly what is meant:
Hi Simon
+ Vignesh
On 11/10/24 00:20, Simon Glass wrote:
Hi Neha,
On Thu, 10 Oct 2024 at 01:09, Neha Malcom Francis wrote:
The message "DRAM: 2 GiB (effective 32 GiB)" can be a little confusing,
modify the message to show exactly what is meant:
"DRAM: 2 GiB (available fo
The message "DRAM: 2 GiB (effective 32 GiB)" can be a little confusing,
modify the message to show exactly what is meant:
"DRAM: 2 GiB (available for U-Boot out of total 32 GiB)"
Signed-off-by: Neha Malcom Francis
---
common/board_f.c | 2 +-
1 file changed, 1 inse
Hi Neil
On 07/10/24 13:43, Neil Armstrong wrote:
Hi Bhupesh, Neha Malcom Francis,
On 30/09/2024 14:44, Neil Armstrong wrote:
This serie regroups all the fixes and base enhancements required to
support the Qualcomm UFS controllers in U-Boot.
This syncs headers & defines from Linux,
given where it is in the file
and the rest of the contents. I think the whole list is intended as
"here are all of the K3-based platforms". This however may mean that a
bunch of boards then need :orphan: added as they won't strictly be in
some other ToC list?
--
Tom
I would prefer not to break tree navigation. It would be best if the TI
contribitors stepped in.
I personally feel this is good enough, the toc contains the TI K3 boards present
within the "K3 Generation" page while the references points to the other vendor
boards.
Best regards
Heinrich
--
Thanking You
Neha Malcom Francis
amp;k3_clks 4 1>,
<&k3_clks 323 0>;
+ assigned-clock-parents= <0>, <0>, <0>, <&k3_clks 323 2>;
+ assigned-clock-rates = <20>, <2>, <10>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
--
Thanking You
Neha Malcom Francis
ice *dev, int vdd_id, int opp_id);
int k3_avs_notify_freq(int dev_id, int clk_id, u32 freq);
+int k3_check_opp(struct udevice *dev, int vdd_id, int opp_id);
#endif
--
Thanking You
Neha Malcom Francis
/Efuse
+ return -EINVAL;
+ }
+
vd->opp = opp_id;
vd->flags |= VD_FLAG_INIT_DONE;
--
Thanking You
Neha Malcom Francis
))) {
printf("Cannot set env var\n");
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
Hi Santhosh
On 21/10/24 10:10, Santhosh Kumar K wrote:
Add ss_cfg memory region which maps the DDRSS configuration region
for the memory controller node.
Signed-off-by: Santhosh Kumar K
Signed-off-by: Neha Malcom Francis
---
arch/arm/dts/k3-am62a-ddr.dtsi | 7 ---
arch/arm/dts/k3
Hi Aniket
On 23/10/24 13:28, Aniket Limaye wrote:
On 23/10/24 12:17, Neha Malcom Francis wrote:
Hi Aniket
On 23/10/24 11:42, Aniket Limaye wrote:
On 17/10/24 16:00, Neha Malcom Francis wrote:
Hi Aniket
On 17/10/24 11:59, Aniket Limaye wrote:
From: Reid Tonking
Define the MSMC clk in
Hi Aniket
On 23/10/24 11:42, Aniket Limaye wrote:
On 17/10/24 16:00, Neha Malcom Francis wrote:
Hi Aniket
On 17/10/24 11:59, Aniket Limaye wrote:
From: Reid Tonking
Define the MSMC clk in the a72 node
The usage of MSMC and A72SS interchangeably in this series is confusing. Could
you
loadables = "uboot";
+ loadables = "uboot",
+ "som-no-rtc",
+ "som-no-spi",
+ "som-no-eth",
+ "som-qspi";
fdt = "fdt-0";
};
};
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
loadables = "uboot";
+ loadables = "uboot",
+ "som-no-rtc",
+ "som-no-spi",
+ "som-no-eth",
+ "som-qspi";
fdt = "fdt-0";
};
};
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
ror;
+ }
+
+ memcpy(blob, fdt_copy, fdt_size);
+
+cleanup:
+ free(fdt_copy);
+ return;
+
+fixup_error:
+ pr_err("Failed to apply SoM overlays\n");
+ goto cleanup;
+}
+
int ft_board_setup(void *blob, struct bd_info *bd)
{
+ fdt_apply_som_overlays(blob);
[])
{
struct upl s_upl, *upl = &s_upl;
- struct unit_test_state uts;
+ struct unit_test_state uts = { 0 };
struct abuf buf;
oftree tree;
ulong addr;
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
Hi Bryan
On 23/10/24 20:15, Bryan Brattlof wrote:
On October 21, 2024 thus sayeth Santhosh Kumar K:
From: Neha Malcom Francis
Add CONFIG_K3_INLINE_ECC so that ECC functions can be compiled into R5 SPL
only when the config has been enabled.
Signed-off-by: Neha Malcom Francis
---
drivers
core hasn't changed for a while, and since UFS is core
technology for the Qualcomm SoCs, I volunteer maintaininig the
UFS subsystem if Bhupesh & Neha Malcom Francis are ok with that.
Could you run this serie on the r8a779f0_spider, j721s2_evm_a72, j721e_evm_a72,
j7200_evm_a72, amd_versal2_
we should be able to copy.
But we also make use of this to fix up the device tree that passes onto kernel
as well, I need to look into this patch though. But from a first glance looks
like we will be able to pass on the information from SPL->SPL (with modification
as you said) and SPL->U-Boot but U-Boot->Kernel would still require this
function to be present.
~Bryan
--
Thanking You
Neha Malcom Francis
Enable the NFS command across all platforms to allow network booting via
the NFS. Clean up the J7 configs to use TI_COMMON_CMD_OPTIONS.
Neha Malcom Francis (2):
board: ti: common: Kconfig: Add CMD_NFS
configs: j7*: Enable TI_COMMON_CMD_OPTIONS
board/ti/common/Kconfig | 1 +
configs
Add CMD_NFS to list of configs implied by CONFIG_TI_COMMON_CMD_OPTIONS.
This allows network booting via the NFS protocol from the U-Boot prompt.
Fixes: 10de12570799 ("disable NFS support by default")
Signed-off-by: Neha Malcom Francis
---
board/ti/common/Kconfig | 1 +
1 file
Instead of bloating the defconfig with CONFIG_CMD_*, move J7 devices to
start using TI_COMMON_CMD_OPTIONS.
Signed-off-by: Neha Malcom Francis
---
configs/j7200_evm_a72_defconfig | 8 +---
configs/j721e_evm_a72_defconfig | 8 +---
configs/j721s2_evm_a72_defconfig | 8 +---
configs
Add a driver for the BIST module that support triggering of both PBIST
(Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant
operations and functions that would be required for an end user to
trigger the tests.
Signed-off-by: Neha Malcom Francis
---
drivers/misc/Kconfig
/j721e/modules/lbist.html#introduction
Neha Malcom Francis (4):
arm: dts: k3-j784s4-main: Add PBIST_14 node
drivers: misc: k3_bist: Add K3 BIST driver
configs: j784s4_evm_a72_defconfig: Enable BIST
DONOTMERGE: arm: mach-k3: j784s4_init: Trigger LBIST and PBIST on MAIN
R5 2_0
arch/arm/mach
Add DT node for PBIST_14 that is responsible for triggering the PBIST
self-tests for the MAIN_R5_2_x cores.
Signed-off-by: Neha Malcom Francis
---
dts/upstream/src/arm64/ti/k3-j784s4-main.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4
Trigger all tests of PBIST and LBIST using appropriate calls to set the
core under test (MAIN R5 2_0) to it's required state.
Signed-off-by: Neha Malcom Francis
---
arch/arm/mach-k3/j784s4/j784s4_init.c | 48 +++
1 file changed, 48 insertions(+)
diff --git a/arc
Enable the BIST driver to be able to successfully probe and trigger BIST
tests on MAIN_R5 cores.
Signed-off-by: Neha Malcom Francis
---
configs/j784s4_evm_a72_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig
index
On 28/11/24 09:38, Kumar, Udit wrote:
Thanks Neha.
On 11/27/2024 8:23 PM, Neha Malcom Francis wrote:
Trigger all tests of PBIST and LBIST using appropriate calls to set the
core under test (MAIN R5 2_0) to it's required state.
Signed-off-by: Neha Malcom Francis
---
arch/arm/mach-k3/j
Hi Udit
On 28/11/24 10:26, Kumar, Udit wrote:
On 11/27/2024 8:23 PM, Neha Malcom Francis wrote:
Add a driver for the BIST module that support triggering of both PBIST
(Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant
In general , please think of treating err as error in
Hi Udit
On 28/11/24 09:28, Kumar, Udit wrote:
On 11/27/2024 8:23 PM, Neha Malcom Francis wrote:
Add DT node for PBIST_14 that is responsible for triggering the PBIST
self-tests for the MAIN_R5_2_x cores.
Signed-off-by: Neha Malcom Francis
---
dts/upstream/src/arm64/ti/k3-j784s4-main.dtsi
This series adds AVS support for AM68 SK, AM69 SK and J784S4 EVM.
Boot logs:
https://gist.github.com/nehamalcom/db5dbf98357ebac46f648c24ad1a17e2
Neha Malcom Francis (4):
arm: dts: k3-j784s4-r5: Add VTM node to R5 stage
arm: dts: k3-am68-sk-r5-base-board: Add VTM node to R5 stage
arch: arm
Add VTM node to R5 boot stage so that AVS gets correctly configured for
J784S4 EVM and AM69 SK.
Signed-off-by: Neha Malcom Francis
---
arch/arm/dts/k3-j784s4-r5.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/k3-j784s4-r5.dtsi b/arch/arm/dts/k3-j784s4-r5.dtsi
index
Add the VTM node to the R5 boot stage so that AVS is correctly
configured for AM68 SK.
Signed-off-by: Neha Malcom Francis
---
arch/arm/dts/k3-am68-sk-r5-base-board.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/k3-am68-sk-r5-base-board.dts
b/arch/arm/dts/k3-am68-sk
Probe the AVS driver to set the AVS voltage.
Signed-off-by: Neha Malcom Francis
---
arch/arm/mach-k3/j784s4/j784s4_init.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c
b/arch/arm/mach-k3/j784s4/j784s4_init.c
index 07b5d7d7504..8a41cd3bb50
From: Udit Kumar
Add AVS and PMIC regulator configs
Signed-off-by: Udit Kumar
---
configs/am68_sk_r5_defconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/configs/am68_sk_r5_defconfig b/configs/am68_sk_r5_defconfig
index f4800ef1b8a..81fa58743da 100644
--- a/configs/a
Enable AVS support on J784S4 along with regulator.
Signed-off-by: Neha Malcom Francis
---
configs/j784s4_evm_r5_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig
index 0b5441fa023..0a55f75bbe5 100644
--- a/configs
,
--
Thanking You
Neha Malcom Francis
..31c2959aeb12931b2bbdf26b3c676ae1a7b0fd1a
100644
--- a/drivers/ufs/ufs.c
+++ b/drivers/ufs/ufs.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include
#include
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
--
Acked-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
Management Response UPIU structure */
+ struct utp_upiu_header rsp_header;
+ __be32 output_param1;
+ __be32 output_param2;
+ __be32 __reserved2[3];
+};
+
+#endif
Acked-by: Neha Malcom Francis
--
Thanking You
Neha Malcom
PRGTUNING UNIPRO_CB_OFFSET(0x00FB)
-#define UNIPRO_CB_OFFSET(x) (0x8000 | x)
+#define UNIPRO_CB_OFFSET(x) (0x8000 | (x))
/*
* PHY Adpater attributes
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
}
-int ufs_start(struct ufs_hba *hba)
+static int ufs_start(struct ufs_hba *hba)
{
struct ufs_dev_desc card = {0};
int ret;
--
Thanking You
Neha Malcom Francis
--
Acked-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
Add a driver for the BIST module that support triggering of both PBIST
(Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant
operations and functions that would be required for an end user to
trigger the tests.
Signed-off-by: Neha Malcom Francis
---
drivers/misc/Kconfig
Add DT node for PBIST_14 that is responsible for triggering the PBIST
self-tests for the MAIN_R5_2_x cores.
Signed-off-by: Neha Malcom Francis
---
Link to kernel DT upstreaming:
https://lore.kernel.org/all/20241128140825.263216-1-n-fran...@ti.com/
Will be following up on its v2.
dts/upstream
-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/pbist.html#introduction
[2]
https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/lbist.html#introduction
Neha Malcom Francis (3):
drivers: misc: k3_bist: Add
Trigger all tests of PBIST and LBIST using appropriate calls to set the
core under test (MAIN R5 2_0) to it's required state.
Signed-off-by: Neha Malcom Francis
---
arch/arm/mach-k3/j784s4/j784s4_init.c | 47 +++
1 file changed, 47 insertions(+)
diff --git a/arc
On 05/02/25 11:38, Manorit Chawdhry wrote:
> Hi Neha,
>
> On 18:01-20250204, Neha Malcom Francis wrote:
>> Trigger all tests of PBIST and LBIST using appropriate calls to set the
>> core under test (MAIN R5 2_0) to it's required state.
>>
>> Signed-off-by: Ne
On 04/02/25 19:38, Kumar, Udit wrote:
>
> On 2/4/2025 6:01 PM, Neha Malcom Francis wrote:
>> Add a driver for the BIST module that support triggering of both PBIST
>> (Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant
>> operations and functions that woul
This header file is not in use in these arch/board specific files,
remove them.
Signed-off-by: Neha Malcom Francis
---
arch/arm/mach-k3/k3-ddr.c | 1 -
board/ti/common/k3-ddr.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/arch/arm/mach-k3/k3-ddr.c b/arch/arm/mach-k3/k3-ddr.c
index
The reserved space needed for storing the parity remains the same no
matter the size of the region that is being protected. Add this as a
comment for better code understanding.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/k3-ddrss/k3-ddrss.c | 4
1 file changed, 4 insertions(+)
diff
b.com/nehamalcom/e5a76bece133c1ec716e2ed94d60ce74
Neha Malcom Francis (8):
k3-ddr.c: Remove unwanted header files
ram: k3-ddrss: Use DDR address instead of system address for
ecc_regions
ram: k3-ddrss: Add comment about ecc_reserved_space
ram: k3-ddrss: Add support for a partial inlin
: protected@9e78 {
device_type = "ecc";
reg = <0x9e78 0x008>;
bootph-all;
};
Signed-off-by: Neha Malcom Francis
---
drivers/ram/k3-ddrss/k3-ddrss.c | 52 +++--
1 file changed, 49 insertions(+), 3 deletions(-)
diff --git
Let ecc_regions[x].start reflect the start of the ECC region in terms of
DDR addressing rather than system addressing. This will make it easier
to extend the usage of the same ecc_regions structure for multi-DDR
systems as well.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/k3-ddrss/k3
Add support for calculation of the protected regions for each DDR in
multi-DDR systems. Since MSMC is the parent node of the individual DDRs
as well as responsible for their interleaving, it only makes sense for
MSMC to contain the logic for dividing the regions.
Signed-off-by: Neha Malcom
In K3 multi-DDR systems, the MSMC is responsible for the interleave
mechanism across all the DDR controllers. Add support for MSMC to obtain
the number of controllers it's responsible for using the DT.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/k3-ddrss/k3-ddrss.c | 8
1
The existing approach does not account for interleaving in the DDRs when
setting up regions. There is support for MSMC to calculate the regions
for each DDR, so modify k3_ddrss_probe to set the regions accordingly
for multi-DDR systems.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/k3
As we increase the functionalities that the K3 DDRSS sub-system support,
it is becoming more evident that the same logic cannot apply to both
single as well as multiple DDR controller devices. Add
CONFIG_K3_MULTI_DDR to be used to differentiate between the two.
Signed-off-by: Neha Malcom Francis
truct udevice *dev)
k3_lpddr4_start(ddrss);
- k3_ddrss_ddr_bank_base_size_calc(ddrss);
-
if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) {
if (!ddrss->ddrss_ss_cfg) {
printf("%s: ss_cfg is required if ecc is enabled but not
provided.",
Reviewed-by: Neha Mal
Hi Wadim
On 28-Jan-25 10:43 AM, Wadim Egorov wrote:
Am 27.01.25 um 21:22 schrieb Neha Malcom Francis:
Instead of defaulting to choosing the entire DDR region when enabling
inline ECC, allow picking of a range within the DDR space using DT to
enable.
It expects such a node within the memory
Hi Wadim
On 28-Jan-25 10:32 AM, Wadim Egorov wrote:
Hi Neha,
Am 27.01.25 um 21:22 schrieb Neha Malcom Francis:
This header file is not in use in these arch/board specific files,
remove them.
Signed-off-by: Neha Malcom Francis
---
arch/arm/mach-k3/k3-ddr.c | 1 -
board/ti/common/k3-ddr.c
Hi Udit
On 28-Jan-25 11:23 AM, Kumar, Udit wrote:
On 1/27/2025 7:52 PM, Neha Malcom Francis wrote:
Instead of defaulting to choosing the entire DDR region when enabling
inline ECC, allow picking of a range within the DDR space using DT to
enable.
It expects such a node within the memory node
uot;;
};
+
+&dmsc {
+ bootph-pre-ram;
+
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ bootph-pre-ram;
+ };
+};
--
Thanking You
Neha Malcom Francis
On 28-Jan-25 11:23 AM, Kumar, Udit wrote:
On 1/27/2025 7:52 PM, Neha Malcom Francis wrote:
Instead of defaulting to choosing the entire DDR region when enabling
inline ECC, allow picking of a range within the DDR space using DT to
enable.
It expects such a node within the memory node, in the
t's at a better time for other parts of
the world.
Thanks for initiating this, I think it will be helpful for most of us. For folks
in the IST region, this is a pretty okay time in the evening so sounds good at
least for me.
--
Thanking You
Neha Malcom Francis
Hi Tom,
On 13/02/25 03:53, Tom Rini wrote:
> With a newer pylint, we get a warning that 'br' could be used before
> assignment. Fix this by declaring br first as an empty bytearray.
>
> Signed-off-by: Tom Rini
> ---
> Cc: Neha Malcom Francis
> Cc: Simon Gla
_LDO_VOLT_MASK 0x7E
> #define TPS65941_LDO_VOLT_MAX_HEX0x3A
> #define TPS65941_LDO_VOLT_MIN_HEX0x4
> #define TPS65941_LDO_VOLT_MAX330
> +#define TPS65941_LDO_VOLT_MIN60
> #define TPS65941_LDO_MODE_MASK 0x1
> #define TPS65941_LDO_BYPASS_EN 0x80
> #define TP65941_BUCK_CONF_SLEW_MASK 0x7
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
721S2_R5_EVM=y
>
> CONFIG_ESM_K3=n
> -CONFIG_K3_AVS0=n
> CONFIG_ESM_PMIC=n
> CONFIG_DM_REGULATOR_TPS65941=n
> CONFIG_PMIC_TPS65941=n
--
Thanking You
Neha Malcom Francis
Include spl.h to avoid definition errors in custom builds.
Fixes: commit bc07851897bd ("board: ti: Pull redundant DDR functions to a
common location and Fixup DDR size when ECC is enabled")
Signed-off-by: Neha Malcom Francis
---
arch/arm/mach-k3/include/mach/k3-ddr.h | 2 ++
1 file
nly depends on a couple of configs (is not selecting them)
and I don't see it doing anything in the code.
--
Thanking You
Neha Malcom Francis
register. For N bit wide bitfields, there will be 2^N possible
> + multiplexer states.
> +
> config MUX_MMIO
> bool "MMIO register bitfield-controlled Multiplexer"
> depends on MULTIPLEXER && SYSCON
--
Thanking You
Neha Malcom Francis
Add a driver for the BIST module that support triggering of both PBIST
(Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant
operations and functions that would be required for an end user to
trigger the tests.
Signed-off-by: Neha Malcom Francis
---
Changes since v2:
- code
/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/pbist.html#introduction
[2]
https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/lbist.html#introduction
Neha Malcom Francis (3):
drivers: misc: k3_bist: Add K3 BIST
Trigger all tests of PBIST and LBIST using appropriate calls to set the
core under test (MAIN R5 2_0) to it's required state.
Signed-off-by: Neha Malcom Francis
---
Changes since v2:
- move MCU4_0 BIST code into a separate function
arch/arm/mach-k3/j784s4/j784s4_init.c
On 28/03/25 19:48, Nishanth Menon wrote:
> On 18:01-20250328, Neha Malcom Francis wrote:
>> Add DT node for PBIST_14 that is responsible for triggering the PBIST
>> self-tests for the MAIN_R5_2_x cores.
>>
>> Signed-off-by: Neha Malcom Francis
>> ---
&
52,7 +152,7 @@ int fdt_fixup_reserved(void *blob, const char *name,
>> }
>> }
>> -add_carveout:
>> +add_carveout: ;
>> struct fdt_memory carveout = {
>> .start = new_address,
>> .end = new_address + new_size - 1,
>
> My suggestion will be to move this struct at start of function.
>
> and change only size here
>
> carveout.end = new_address + new_size - 1;
>
>
--
Thanking You
Neha Malcom Francis
er_domain *power_domain)
>> +static inline int power_domain_off_lowlevel(struct power_domain
>> *power_domain)
>> {
>> return -ENOSYS;
>> }
>> #endif
>>
>> +/**
>> + * power_domain_off - Disable power to a power domain (ignores the actual
>> state
>> + *of the power domain)
>> + *
>> + * @power_domain: A power domain struct that was previously successfully
>> + * requested by power_domain_get().
>> + * Return: a negative error code upon error during the transition, 0
>> otherwise.
>> + */
>> +static inline int power_domain_off(struct power_domain *power_domain)
>> +{
>> +int ret;
>> +
>> +ret = power_domain_off_lowlevel(power_domain);
>> +if (ret == -EALREADY || ret == -EBUSY)
>> +ret = 0;
>> +
>> +return ret;
>> +}
>> +
>> /**
>> * dev_power_domain_on - Enable power domains for a device .
>> *
>> diff --git a/test/dm/power-domain.c b/test/dm/power-domain.c
>> index
>> 896cf5b2ae9d26701150fad70e888f8b135a22b0..8a95f6bdb903be9d1993528d87d5cae0075a83e4
>> 100644
>> --- a/test/dm/power-domain.c
>> +++ b/test/dm/power-domain.c
>> @@ -27,7 +27,7 @@ static int dm_test_power_domain(struct unit_test_state
>> *uts)
>>
>> ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "power-domain-test",
>>&dev_test));
>> -ut_asserteq(1, sandbox_power_domain_query(dev_power_domain,
>> +ut_asserteq(0, sandbox_power_domain_query(dev_power_domain,
>>TEST_POWER_DOMAIN));
>> ut_assertok(sandbox_power_domain_test_get(dev_test));
>>
>>
>
--
Thanking You
Neha Malcom Francis
On 15/04/25 18:13, Miquel Raynal wrote:
> On 15/04/2025 at 15:29:09 +0530, Neha Malcom Francis wrote:
>
>> Hi Miquel
>>
>> On 15/04/25 15:20, Miquel Raynal wrote:
>>>>> Francesco, are you also testing on K3 platforms?
>>>>>
>>>
erfaces, as they have a similar pattern as on k3 platform: a
> single power domain node and one cell for figuring out which PD to
> enable.
>
> The uclass does not save any data, so I don't have an immediate fix to
> propose. Let me dig a bit more into that and find a solution.
>
Thanks!
Meanwhile, could we revert this patch to keep the platforms from breaking?
> Thanks,
> Miquèl
--
Thanking You
Neha Malcom Francis
> "envboot=mmc dev ${mmcdev}; " \
> "if mmc rescan; then " \
> "echo SD/MMC found on device ${mmcdev};" \
Are there any other boards that use .h instead of .env other than AM57x?
Would they break with this change?
--
Thanking You
Neha Malcom Francis
4 +163,5 @@ U_BOOT_DRIVER(sandbox_scmi_devices) = {
> .priv_auto = sizeof(struct sandbox_scmi_device_priv),
> .remove = sandbox_scmi_devices_remove,
> .probe = sandbox_scmi_devices_probe,
> + .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
> };
[...]
Thanks for working on this quickly, I've booted it on j784s4-evm and
works fine! And I am good with this approach using subdomains.
Tested-by: Neha Malcom Francis
(on j784s4-evm)
--
Thanking You
Neha Malcom Francis
; which is this patch.
>>
>> And assuming it's the same failure I got reported this morning by one of
>> my coworkers, we just get:
>> U-Boot SPL 2025.04-01050-ga40fc5afaec0 (Apr 14 2025 - 07:31:32 +)
>> SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.7--v09.02.07 (Kool Koala)')
This is not the failure I am seeing, we hang before console comes up so
no prints. Looks like the different failure signature is due to TIFS
(SYSFW) firmware being different (v9.2.7 vs. 11.0.4)
> I have not tried reverting that commit yet, but I do have the same
> failure.
>
> Francesco
>
--
Thanking You
Neha Malcom Francis
now what board/SoC was used for the test, so I
> can look the relevant driver up.
Booted on j784s4_evm
https://gist.github.com/nehamalcom/b09687a523bec89f9df3537fdd99b6f3
Currently debugging on my build where I hang in console_init itself, I
think the path for failure is different here, will confirm.
>
> Thanks for your help,
> Miquèl
>
> ---
>
--
Thanking You
Neha Malcom Francis
al driver probe
(ns16550_serial_probe) tries to do a readb() and fails, this could
possibly be because the device was not powered on to begin with. Whereas
in another case (what Francesco is seeing), this issue is not run into.
>
> Thanks,
> Miquèl
--
Thanking You
Neha Malcom Francis
Malcom Francis
---
Sanity boot log:
https://gist.github.com/nehamalcom/ef40be06080cb5bc4d1be881690aaebb
Changes since v1:
- updated commit message with version and explanation
- added sanity boot log
board/ti/j784s4/rm-cfg.yaml | 24
board/ti/j784s4/tifs-rm-cfg.yaml
would not be enough for all such use
cases for RTOS and Linux, thus sharing of resources in needed.
Signed-off-by: Vaishnav Achath
[n-fran...@ti.com: rebased and sent on behalf]
Signed-off-by: Neha Malcom Francis
---
board/ti/j784s4/rm-cfg.yaml | 24
board/ti
clk_clk"),
> @@ -400,7 +452,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
>
> const struct ti_k3_clk_platdata j721s2_clk_platdata = {
> .clk_list = clk_list,
> - .clk_list_cnt = 105,
> + .clk_list_cnt = ARRAY_SIZE(clk_list),
> .soc_dev_clk_data = soc_dev_clk_data,
> - .soc_dev_clk_data_cnt = 124,
> + .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data),
> };
> diff --git a/arch/arm/mach-k3/r5/j721s2/dev-data.c
> b/arch/arm/mach-k3/r5/j721s2/dev-data.c
> index df70c5e5d7c..b78550707c5 100644
> --- a/arch/arm/mach-k3/r5/j721s2/dev-data.c
> +++ b/arch/arm/mach-k3/r5/j721s2/dev-data.c
> @@ -5,7 +5,7 @@
> * This file is auto generated. Please do not hand edit and report any issues
> * to Dave Gerlach .
> *
> - * Copyright (C) 2020-2021 Texas Instruments Incorporated -
> https://www.ti.com/
> + * Copyright (C) 2020-2025 Texas Instruments Incorporated -
> https://www.ti.com/
> */
>
> #include "k3-dev.h"
> @@ -47,6 +47,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
> };
>
> static struct ti_dev soc_dev_list[] = {
> + PSC_DEV(29, &soc_lpsc_list[0]),
> PSC_DEV(35, &soc_lpsc_list[0]),
> PSC_DEV(108, &soc_lpsc_list[0]),
> PSC_DEV(109, &soc_lpsc_list[0]),
--
Thanking You
Neha Malcom Francis
601 - 700 of 751 matches
Mail list logo
