As we increase the functionalities that the K3 DDRSS sub-system support,
it is becoming more evident that the same logic cannot apply to both
single as well as multiple DDR controller devices. Add
CONFIG_K3_MULTI_DDR to be used to differentiate between the two.
Signed-off-by: Neha Malcom Francis <n-fran...@ti.com>
---
drivers/ram/Kconfig | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 899d7585489..0d19021d8e3 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -126,6 +126,16 @@ config K3_INLINE_ECC
need to be primed with a predefined value prior to enabling ECC
check.
+config K3_MULTI_DDR
+ bool "Enable support for multiple K3 DDRSS controllers"
+ depends on K3_DDRSS
+ help
+ Enabling this option adds support for configuring multiple DDR memory
+ controllers for K3 devices. The external memory interleave layer
+ present in the MSMC (Multicore Shared Memory Controller) is
+ responsible for interleaving between the controllers.
+ default y if SOC_K3_J721S2 || SOC_K3_J784S4
+
source "drivers/ram/aspeed/Kconfig"
source "drivers/ram/cadence/Kconfig"
source "drivers/ram/octeon/Kconfig"
--
2.34.1
