On 10/20/19 2:27 PM, Tom Rini wrote:
On Sun, Oct 20, 2019 at 08:30:44AM +0200, Heinrich Schuchardt wrote:
Hello Tom,
I tested with the updated origin/WIP/Update-test.py-tests:
$ python3 ./test/py/test.py --bd=qemu-arm64 --build-dir=. -k=test_efi_
INTERNALERROR> Traceback (most recent call last
On Sun, Oct 20, 2019 at 03:11:43PM +0200, Heinrich Schuchardt wrote:
> On 10/20/19 2:27 PM, Tom Rini wrote:
> > On Sun, Oct 20, 2019 at 08:30:44AM +0200, Heinrich Schuchardt wrote:
> > > Hello Tom,
> > >
> > > I tested with the updated origin/WIP/Update-test.py-tests:
> > >
> > > $ python3 ./test
On 10/20/19 3:11 PM, Heinrich Schuchardt wrote:
On 10/20/19 2:27 PM, Tom Rini wrote:
On Sun, Oct 20, 2019 at 08:30:44AM +0200, Heinrich Schuchardt wrote:
Hello Tom,
I tested with the updated origin/WIP/Update-test.py-tests:
$ python3 ./test/py/test.py --bd=qemu-arm64 --build-dir=. -k=test_efi
On Sun, Oct 20, 2019 at 03:21:03PM +0200, Heinrich Schuchardt wrote:
> On 10/20/19 3:11 PM, Heinrich Schuchardt wrote:
> > On 10/20/19 2:27 PM, Tom Rini wrote:
> > > On Sun, Oct 20, 2019 at 08:30:44AM +0200, Heinrich Schuchardt wrote:
> > > > Hello Tom,
> > > >
> > > > I tested with the updated or
On 10/20/19 3:22 PM, Tom Rini wrote:
On Sun, Oct 20, 2019 at 03:21:03PM +0200, Heinrich Schuchardt wrote:
On 10/20/19 3:11 PM, Heinrich Schuchardt wrote:
On 10/20/19 2:27 PM, Tom Rini wrote:
On Sun, Oct 20, 2019 at 08:30:44AM +0200, Heinrich Schuchardt wrote:
Hello Tom,
I tested with the upd
The following changes since commit 6891152a4596d38ac25d2fe1238e3b6a938554b8:
Merge branch 'master' of git://git.denx.de/u-boot-socfpga (2019-10-14
21:00:10 -0400)
are available in the Git repository at:
git://git.denx.de/u-boot-usb.git master
for you to fetch changes up to 79b03816cb7d17ce7
This adds platform code and the device tree for the Phytium Durian Board.
The initial support comprises the UART the GMAC and the PCIE.
Cc: Bin Meng
Cc: Kever Yang
Cc: Tom Rini
Cc: Heinrich Schuchardt
Signed-off-by: Steven Hao
---
Changes for v4:
- Drop the changelog from the commit message
This fixes a problem, where booting Linux using distro boot will
sometimes lead to an invalid instruction exception on the main hart. The
secondary harts are not affected and boot Linux successfully. The root
cause of this problem is a stack overflow on the main hart.
With distro boot, the current
Hi Jean-Jacques,
> This is the second of a few series, the goal of which is to facilitate
> porting drivers from the linux kernel. Most of the series will be
> about adding managed API to existing infrastructure (GPIO, reset,
> phy,...)
>
> This particular series is about clocks. It adds a manage
Thank you Daniel!
-Original Message-
From: Daniel Schwierzeck [mailto:daniel.schwierz...@gmail.com]
Sent: Friday, October 18, 2019 4:37 AM
To: William Zhang; philippe.rey...@softathome.com
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH] drivers: nand: brcmnand: fix nand_chip ecc
lay
Hi Simon,
On Sat, Oct 19, 2019 at 4:37 AM Simon Glass wrote:
>
> Hi Bin,
>
> On Fri, 18 Oct 2019 at 09:38, Bin Meng wrote:
> >
> > Hi Simon,
> >
> > On Fri, Oct 18, 2019 at 10:14 PM Simon Glass wrote:
> > >
> > > Hi Bin,
> > >
> > > On Thu, 17 Oct 2019 at 20:32, Bin Meng wrote:
> > > >
> > > >
Hi Simon,
On Sat, Oct 19, 2019 at 10:44 AM Simon Glass wrote:
>
> Hi Bin,
>
> On Wed, 9 Oct 2019 at 07:10, Bin Meng wrote:
>>
>> Hi Simon,
>>
>> On Wed, Sep 25, 2019 at 10:12 PM Simon Glass wrote:
>> >
>> > This provides access to SPI flash both through a read-only memory map and
>> > with oper
Hi Bin,
On Sun, 20 Oct 2019 at 20:29, Bin Meng wrote:
>
> Hi Simon,
>
> On Sat, Oct 19, 2019 at 4:37 AM Simon Glass wrote:
> >
> > Hi Bin,
> >
> > On Fri, 18 Oct 2019 at 09:38, Bin Meng wrote:
> > >
> > > Hi Simon,
> > >
> > > On Fri, Oct 18, 2019 at 10:14 PM Simon Glass wrote:
> > > >
> > > >
Hi Bin,
On Sun, 20 Oct 2019 at 20:34, Bin Meng wrote:
>
> Hi Simon,
>
> On Sat, Oct 19, 2019 at 10:44 AM Simon Glass wrote:
> >
> > Hi Bin,
> >
> > On Wed, 9 Oct 2019 at 07:10, Bin Meng wrote:
> >>
> >> Hi Simon,
> >>
> >> On Wed, Sep 25, 2019 at 10:12 PM Simon Glass wrote:
> >> >
> >> > This
Apollolake is an Intel SoC generation aimed at relatively low-end embedded
systems. It was released in 2016 but has become more popular recently with
some embedded boards using it.
This series adds support for apollolake. As an example it adds an
implementation of chromebook_coral (a large range o
This entry is used to hold an Intel FSP-S (Firmware Support Package
Silicon init) binary. Add support for this in binman.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
tools/binman/README.entries | 17 +
tools/binman/etype/intel_fsp_s.py |
At present binman adds the image base address to the symbol value before
it writes it to the binary. This is not correct since the symbol value
itself (e.g. image position) has no relationship to the image base.
Fix this and update the tests to cover this case.
Signed-off-by: Simon Glass
---
Ch
This entry is used to hold an Intel FSP-T (Firmware Support Package
Temp-RAM init) binary. Add support for this in binman.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
tools/binman/README.entries | 16
tools/binman/etype/intel_fsp_t.py |
This is hacked into the driver at present. It seems better to have it as
a separate driver that uses the base driver. Create a new file and put
the X86 code into it.
Actually the Baytrail settings should really come from the device tree.
Signed-off-by: Simon Glass
---
Changes in v3: None
Change
This function can be called before the timer is set up. Make sure that the
init function is called so that it works correctly.
This is needed so that bootstage can work correctly in TPL.
Signed-off-by: Simon Glass
---
Changes in v3:
- Update commit message
Changes in v2: None
drivers/timer/t
At present PCI auto-configuration happens in U-Boot both before and after
relocation. This is a waste of time and may mess up static addresses used
in board_init_f(). Adjust the code to do auto-configuration once, after
relocation.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2
When device-tree compilation fails it is sometimes tricky to see which
line is broken, since the input file to dtc is a pre-processed version
of the device tree.
Add a line that points to the file that needs to be checked:
Output is something like this:
Error: arch/x86/dts/u-boot.dtsi:137.14-15
Most x86 CPUs use a mechanism where the SPI flash is mapped into the very
top of 32-bit address space, so that it can be executed in place and read
simply by copying from memory. For an 8MB ROM the mapping starts at
0xff80.
However some recent Intel CPUs do not use a simple 1:1 memory map. Ins
SPL and TPL can access information about binman entries using link-time
symbols but this is not available in U-Boot proper. Of course it could be
made available, but the intention is to just read the device tree.
Add support for this, so that U-Boot can locate entries.
Signed-off-by: Simon Glass
The code in swapcase can be used by other sandbox drivers. Move it into a
common place to allow this.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/pci/pci_sandbox.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pci_sandbox.c b/drivers/pci/pci
These functions are used by code outside the network support, so move them
to lib/ to be more accessible.
Fix up a few code-style nits while we are here.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
lib/Makefile| 2 +-
lib/net_utils.c | 48 ++
We have the ability to enforce a maximum size for SPL but not yet for TPL.
Add a new option for this.
Document the size check macro while we are here.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
Makefile | 7 +++
common/spl/Kconfig | 8
2 file
Early in boot it is necessary to decode the PCI device/function values for
particular peripherals in the device tree or of-platdata. This is needed
in TPL where CONFIG_PCI is not defined.
To handle this, move pci_get_devfn() into a file that is built even when
CONFIG_PCI is not defined.
Signed-of
These warnings appear every thing sandbox is run (see below) and dwarf the
actual useful output. Suppress them in two ways:
1. For the mismatch warnings, only set the ethaddr environment
variables when running tests.
2. For the 'MAC address from ROM' warning, never print this on sandbox.
Signed-
It is now possible to obtain the memory map for a SPI controllers instead
of having it hard-coded in the device tree. Update the code to support
this.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- Use SPI mmap() instead of SPI flash
arch/x86/lib/mrccache.c | 18 ++
This comment references the wrong FSP component. Fix it.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
tools/binman/etype/intel_fsp_m.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/binman/etype/intel_fsp_m.py
b/tools/binman/etype/intel_fs
If the offset is -1 this function correct sets up a null ofnode. But if
the offset is any other negative number (e.g. an FDT_ERR) then it does the
wrong thing.
Fix it.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
include/dm/ofnode.h | 2 +-
1 file changed, 1 insertio
This reverts commit 96ac4def8b6686de8566b91419ce98cd5765079b.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/sandbox/cpu/state.c | 12 ++--
arch/sandbox/include/asm/state.h | 5 +
cmd/nvedit.c | 8
include/configs/
At present the name of the image comes first in the linker-list symbol
used. This means that the name of the function sets the sort order, which
is not the intention.
Update it to put the boot-device type first, then the priority. This
produces the expected behaviour.
Signed-off-by: Simon Glass
These are mostly specific to a particular SoC. Add the definitions for
apollolake.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add VBT signature
- Add structures for FSP-S also
- Drop struct fsp_usp_header as it is now in the API file
Changes in v2: None
.../asm/arch-apollolake/fsp/fsp_co
Add loaders for SPL and TPL so that the next stage can be loaded from
memory-mapped SPI or, failing that, the Fast SPI driver.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add a driver for APL SPI for TPL (using of-platdata)
- Support TPL without CONFIG_TPL_SPI_SUPPORT
- Support bootstage ti
Add basic plumbing to allow apollolake support to be used.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add MMC, video, USB configs
- Add an APL_SPI_FLASH_BOOT option to enable non-mmap boot
- Fix the incorrect value of CPU_ADDR_BITS
Changes in v2: None
arch/x86/Kconfig| 1
The Primary-to-Sideband bus (P2SB) is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added in
the device tree as
On x86 platforms the SPI flash can be mapped into memory so that the
contents can be read with normal memory accesses.
Add a new SPI method to find the location of the SPI flash in memory. This
differs from the existing device-tree "memory-map" mechanism in that the
location can be discovered at r
At present we don't support loading microcode with FSP2. The correct way
to do this is by adding it to the FIT. For now, disable including
microcode in the image.
Signed-off-by: Simon Glass
---
Changes in v3:
- Drop unnecessary #else part of CONFIG_HAVE_MICROCODE
Changes in v2: None
arch/x86/
Use dev_get_driver_data() to obtain the device type. It has the same
effect and is shorter.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c | 22 +-
1 file changed, 5 insertions(+), 17 deletions(-)
diff --git a/drivers/spi/ich.c b/d
Add a driver for the apollolake Platform Controller Hub. It does not have
any functionality and is just a placeholder for now.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- Drop probe() function
- Implement set_spi_protect()
arch/x86/cpu/apollolake/Makefile | 1
Add a note about the driver name in the of-platdata documentation since
the naming must follow the compatible string.
Signed-off-by: Simon Glass
---
Changes in v3:
- Rework patch now that the original CONFIG_IS_ENABLED() problems is fixed
Changes in v2: None
doc/driver-model/of-plat.rst | 2 +
This function needs to be different for FSP2, so move the existing
function into the fsp1 directory. Since it is only called from one file,
drop it from the header file.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
arch/x86/include/asm/fsp/fsp_s
Most of the timer-calibration methods are not needed on recent Intel CPUs
and just increase code size. Add an option to use the known-good way to
get the clock frequency in TPL. Size reduction is about 700 bytes.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/ti
For TPL we only need to set up the features and identify the CPU to a
basic level. Add a function to handle that.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/i386/cpu.c | 8
arch/x86/include/asm/u-boot-x86.h | 9 +
2 files chan
At present we call spl_init() before identifying the CPU. This is not a
good idea - e.g. if bootstage is enabled then it will try to set up the
timer which works better if the CPU is identified.
Put explicit code at each entry pointer to identify the CPU.
Signed-off-by: Simon Glass
---
Changes
Define this symbol so that we can use binman symbols correctly.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/u-boot-spl.lds | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/x86/cpu/u-boot-spl.lds b/arch/x86/cpu/u-boot-spl.lds
i
For apollolake SPL is run from CAR (cache-as-RAM) which is in a different
location from where SPL must be placed in ROM. In other words, although
SPL runs before SDRAM is set up, it is not execute-in-place (XIP).
Add a Kconfig option for the ROM position.
Signed-off-by: Simon Glass
---
Changes
This should take account of the end of the new cache record since a record
cannot extend beyond the end of the flash region. This problem was not
seen before due to the alignment of the relatively small amount of MRC
data.
But with apollolake the MRC data is about 45KB, even if most of it is
zeroe
Add support for Apollolake to the ICH driver. This involves adjusting the
mmio address and skipping setting of the bbar.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c | 19 ++-
drivers/spi/ich.h | 1 +
2 files changed, 15 insertions(+
At present the interrupt table is included in all phases of U-Boot. Allow
it to be omitted, e.g. in TPL, to reduce size.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3:
- Move write_pirq_routing_table() to avoid 64-bit build error
Changes in v2: None
arch/x86/cpu/Makefile
Move the header files into the right order.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 7c29369a169..516b859a674 100644
--- a/drivers
Add a simple sandbox test for this uclass.
Signed-off-by: Simon Glass
---
Changes in v3:
- Change the sandbox test from ITSS to IRQ
Changes in v2: None
arch/sandbox/dts/test.dts | 4 +++
configs/sandbox_defconfig | 3 +-
configs/sandbox_flattree_defconfig | 1 +
configs/s
This is used on several boards so add it to the common file. Also add a
useful power-limit value while we are here.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/include/asm/arch-broadwell/cpu.h | 1 -
arch/x86/include/asm/arch-ivybridge/model_206ax.h
This driver handles communication with the systemagent which needs to be
told when U-Boot has completed its init.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 2 ++
arch/x86/cpu/apollolake/systemagent.c | 19 +++
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
Add support for these along with suitable configuration options.
Signed-off-by: Simon Glass
---
Changes in v3:
- Drop unneeded Kconfig file
Changes in v2: None
arch/x86/Kconfig| 16 +
arch/x86/cpu/
This function is a bit confusing at present due to the error handling.
Update it to remove the goto, returning errors as they happen.
While we are here, use hex for the data size since this is the norm in
U-Boot.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3:
- Move an add
For apollolake we need to take the I2C bus controller out of reset before
using this. Add this functionality to the driver.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add a weak function to avoid errors on other platforms
Changes in v2: None
drivers/i2c/dw_i2c_pci.c | 20
The fsp_notify() API is the same for FSP1 and FSP2. Move it into a new
common API file.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/include/asm/fsp/fsp_api.h | 27 +++
arch/x86/include/asm/fsp1/fsp_api.h | 21 +++--
2
Add very basic support for taking an lpss device out of reset.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/lpss.c | 31 +++
arch/x86/include/asm/lpss.h | 11 ++
Add code to init the system both in TPL and SPL. Each phase has its own
procedure.
Signed-off-by: Simon Glass
---
Changes in v3:
- Adjust fast_spi_cache_bios_region() to avoid using SPI driver
- Drop calls to x86_cpu_init_f(), x86_cpu_reinit_f()
- Fix build error when debug UART is disabled
- In
We don't expect an exception in TPL and don't need to print out full
details if one happens. Add a reduced version of the code for TPL.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/i386/interrupt.c | 13 +
1 file changed, 13 insertions(+)
dif
Add a sandbox driver and PCI-device emulator for p2sb. Also add a test
which uses a simple 'adder' driver to test the p2sb functionality.
Signed-off-by: Simon Glass
---
Changes in v3:
- Fix build errors in sandbox_spl, etc
Changes in v2: None
arch/sandbox/cpu/state.c | 1 +
arch/s
Intel x86 SoCs have a power manager/controller which handles several
power-related aspects of the platform. Add a uclass for this, with a few
useful operations.
Signed-off-by: Simon Glass
---
Changes in v3:
- Rename power-mgr uclass to acpi-pmc
Changes in v2: None
drivers/power/Kconfig
With FSP2 we need to run silicon init early after relocation. Add a new
hook for this.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
common/board_r.c | 3 +++
include/init.h | 11 +++
2 files changed, 14 insertions(+)
diff --git a/common/board_r.c b/common/
On some platforms the timer is reset to 0 when the SoC is reset. Having
this as the timer base is useful since it provides an indication of how
long it takes before U-Boot is running.
When U-Boot sets the timer base to something else, time is lost and we
no-longer have an accurate account of the t
This incorrectly shortens read operations if there is a maximum write size
but no maximum read size. Fix it.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/ich.c b/
We already a message indicating that U-Boot is about to jump to SPL, so
make this one a debug() to reduce code size.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/lib/tpl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/lib/tpl.c
At present binman does not support updating a device tree that is part of
U-Boot (i.e u-boot.bin). Separate the entries into two so that we can get
updated entry information. This makes binman_entry_find() work correctly.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
a
The Intel Fast SPI interface is similar to ICH. Add of-platdata support
for this using the "intel,fast-spi" compatible string.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff
Add a driver for the apollolake UART. It uses the standard ns16550 device
but also sets up the input clock with LPSS and supports configuration via
of-platdata.
Signed-off-by: Simon Glass
---
Changes in v3:
- Use the LPSS code from a separate file
Changes in v2: None
arch/x86/cpu/apollolake/M
It is useful to store the mmio base in platdata. It reduces the amount of
casting needed. Update the code and move the struct to the C file at the
same time, as we will need to use with of-platdata.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c | 27 +
Add this method so that the memory-mapped location of the SPI flash can
be queried.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich
Many Intel SoCs require a FIT in order to boot properly. Add an option to
include this and enable it by default.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add help to CONFIG_FIT and don't make it 'default y'
Changes in v2: None
arch/x86/Kconfig | 9 +
arch/x86/dts/u-boot
The FSP-S may do this but at least for coral it does not. Set this up so
that graphics is not deathly slow.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/lib/fsp/fsp_graphics.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/x86/lib/fsp/fsp_graphi
Set up MTRRs for the FST SDRAM regions to improve performance.
Signed-off-by: Simon Glass
---
Changes in v3:
- Move mtrr_add_request() call into this patch
Changes in v2: None
arch/x86/lib/fsp/fsp_dram.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/ar
Add support for a second cache type, for apollolake.
Signed-off-by: Simon Glass
---
Changes in v3:
- Move the mrccache_get_region() change into this patch
Changes in v2: None
arch/x86/include/asm/mrccache.h | 1 +
arch/x86/lib/mrccache.c | 3 ++-
2 files changed, 3 insertions(+), 1 de
With apollolake we need to support a normal cache, which almost never
changes and a much smaller 'variable' cache which changes every time.
Update the code to add a cache type, use an array for the caches and use a
for loop to iterate over the caches.
Signed-off-by: Simon Glass
---
Changes in v
Add a driver for the apollolake SoC. It supports the basic operations and
can use device tree or of-platdata.
Signed-off-by: Simon Glass
---
Changes in v3:
- Use pci_get_devfn()
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 5 +
arch/x86/cpu/apollolake/pmc.c |
At present the value of the timer base is used to determine whether the
timer has been set up or not. It is true that the timer is essentially
never exactly 0 when it is read. However 'time 0' may indicate the time
that the machine was reset so it is useful to be able to denote that.
Update the co
Add a driver for the apollolake GPIOs. It also handles pinctrl since this
is not very well separated on x86.
Signed-off-by: Simon Glass
---
Changes in v3:
- Fix mixed case in GPIO defines
- Rework how pads configuration is defined in TPL and SPL
- Use the IRQ uclass instead of ITSS
Changes in v
We don't want to pull in libfdt if of-platdata is being used, since it
reduces the available code-size saves. Also, SPI flash is seldom needed
in TPL.
Drop these options.
Signed-off-by: Simon Glass
---
Changes in v3:
- Don't imply SPI flash either
- Rewrite commit message
Changes in v2: None
The x86 power unit handles power management. Support initing this device
which is modelled as a new type of system controller since there are no
operations needed.
Signed-off-by: Simon Glass
---
Changes in v3:
- Fix 'err-%d' typo
Changes in v2: None
arch/x86/include/asm/cpu.h | 1 +
arch/x86
Update this uclass to support the needs of the apollolake ITSS. It
supports four operations.
Move the uclass into a separate directory so that sandbox can use it too.
Add a new Kconfig to control it and enable this on x86.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add two more operations
This driver models some sort of interrupt thingy but there are so many
abreviations that I cannot find out what it stands for. Possibly something
to do with interrupts.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add snapshot/restore for IRQs
- Use the IRQ uclass instead of ITSS
Changes in
In TPL we want to reduce code size and support running with CONFIG_PCI
disabled. Add special code to handle this using a fixed BAR programmed
into the SPI on boot. Also cache the SPI flash to speed up boot.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/spi/ich.
We don't normally need this on x86 unless the size of SPI flash devices is
larger than 16MB. This can be enabled by particular SoCs as needed, since
it adds to code size.
Drop the default enabling of this option on x86.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
dr
We don't generally have enough space to run this, so don't build it into
TPL. This helps reduce the size of TPL.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
arch/x86/lib/Makefile | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/li
Use debug() instead of printf() to reduce code size and change a bool
return value to the use the 'bool' type. Also drop the global data
declaration since it not actually used. Finally, set the log category.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/spi/ich
Add a bare-bones CPU driver so that CPUs can be probed.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add two more defines for the CPU driver
- Expand comments for BOOT_FROM_FAST_SPI_FLASH
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/cpu.c
At present we reuse the mrc_output char * to also point to the cache
record after it has been set up. This is confusing and doesn't save much
data space.
Add a new mrc_cache member instead.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
arch/x86/
This generic FSP file should include the generic FSP support header, not
the FSP1 version. Fix it.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/lib/fsp/fsp_support.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/lib/fsp/fsp_supp
Change the algorithm to first find the flash device then read the
properties using the livetree API. With this change the device is not
probed so this needs to be done in mrccache_save().
Signed-off-by: Simon Glass
---
Changes in v3:
- Update mrccache livetree patch to just convert to livetree
At present with fsp a single DRAM bank is added which extends to the
whole size of memory. However there is typically only 2GB of memory
available below the 4GB boundary, and this is what is used by U-Boot while
running in 32-bit mode.
Scan the tables to set the banks correct. The first bank is se
Add support for some important configuration options and FSP memory init.
The memory init uses swizzle tables from the device tree.
Support for the FSP_S binary is also included.
Bootstage timing is used for both FSP_M and FSP_M and memory-mapped SPI
reads.
Signed-off-by: Simon Glass
---
Chang
At present we have to have an xfer() method even if it does nothing. This
is not correct, so fix it.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c| 9 +
drivers/spi/spi-uclass.c | 5 -
include/spi.h| 2 +-
3 files chang
Add a simple PMC for sandbox to permit tests to run.
Signed-off-by: Simon Glass
---
Changes in v3:
- Rename power-mgr uclass to acpi-pmc
Changes in v2: None
Makefile | 3 +-
arch/Kconfig | 2 +
arch/sandbox/dts/sandbox.dtsi | 14 ++
arch/
The existing work-around for positioning U-Boot in the ROM when it
actually runs from RAM still exists and there is not obvious way to change
this.
Add a proper Kconfig option to handle this case. This also adds a new bool
property to indicate whether CONFIG_SYS_TEXT_BASE exists.
Signed-off-by: S
At present if SPL sets up the microcode then it is still included in
U-Boot as well. This is wasteful as microcode is large. Adjust the logic
in the image to prevent this.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/dts/u-boot.dtsi | 7 +++
1 file change
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