At present we don't support loading microcode with FSP2. The correct way
to do this is by adding it to the FIT. For now, disable including
microcode in the image.
Signed-off-by: Simon Glass <s...@chromium.org>
---
Changes in v3:
- Drop unnecessary #else part of CONFIG_HAVE_MICROCODE
Changes in v2: None
arch/x86/Kconfig | 4 ++++
arch/x86/dts/u-boot.dtsi | 7 +++++++
2 files changed, 11 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 69327bd746a..37e94d8913a 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -598,6 +598,10 @@ config HAVE_REFCODE
broadwell) U-Boot will be missing some critical setup steps.
Various peripherals may fail to work.
+config HAVE_MICROCODE
+ bool
+ default y if !FSP_VERSION2
+
config SMP
bool "Enable Symmetric Multiprocessing"
default n
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 049f47c9ffd..aaca8874540 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -37,11 +37,13 @@
};
#endif
#ifdef CONFIG_TPL
+#ifdef CONFIG_HAVE_MICROCODE
u-boot-tpl-with-ucode-ptr {
offset = <CONFIG_TPL_TEXT_BASE>;
};
u-boot-tpl-dtb {
};
+#endif
u-boot-spl {
offset = <CONFIG_SPL_TEXT_BASE>;
};
@@ -77,11 +79,16 @@
offset = <CONFIG_SYS_TEXT_BASE>;
};
#endif
+#ifdef CONFIG_HAVE_MICROCODE
u-boot-dtb-with-ucode {
};
u-boot-ucode {
align = <16>;
};
+#else
+ u-boot-dtb {
+ };
+#endif
#ifdef CONFIG_X86_HAS_FIT
intel-fit {
};
--
2.23.0.866.gb869b98d4c-goog
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