On some platforms the timer is reset to 0 when the SoC is reset. Having
this as the timer base is useful since it provides an indication of how
long it takes before U-Boot is running.
When U-Boot sets the timer base to something else, time is lost and we
no-longer have an accurate account of the time since reset. This
particularly affects bootstage.
Add an option to leave the timer base as 0 on boot.
Signed-off-by: Simon Glass <s...@chromium.org>
---
Changes in v3: None
Changes in v2: None
drivers/timer/Kconfig | 13 +++++++++++++
drivers/timer/tsc_timer.c | 3 ++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 5f4bc6edb67..0c922f54603 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -174,6 +174,19 @@ config X86_TSC_TIMER
help
Select this to enable Time-Stamp Counter (TSC) timer for x86.
+config X86_TSC_ZERO_BASE
+ bool "Assume that TSC timer starts at 0"
+ depends on X86_TSC_TIMER
+ help
+ On some platforms the TSC timer tick starts at the value 0 on reset.
+ This it makes no sense to read the timer on boot and use that as the
+ base, since we will miss some time taken to load U-Boot, etc. This
+ delay is controlled by the SoC and we cannot reduce it, but for
+ bootstage we want to record the time since reset as accurately as
+ possible.
+
+ Enable this to always us an initial TSC value of 0.
+
config MTK_TIMER
bool "MediaTek timer support"
depends on TIMER
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index 637c8ff25a5..ac7ba7fb00d 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -396,7 +396,8 @@ static void tsc_timer_ensure_setup(bool early)
{
if (gd->arch.tsc_inited)
return;
- gd->arch.tsc_base = rdtsc();
+ if (!IS_ENABLED(CONFIG_X86_TSC_ZERO_BASE))
+ gd->arch.tsc_base = rdtsc();
if (!gd->arch.clock_rate) {
unsigned long fast_calibrate;
--
2.23.0.866.gb869b98d4c-goog
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