Add very basic support for taking an lpss device out of reset.
Signed-off-by: Simon Glass <s...@chromium.org>
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 1 +
arch/x86/cpu/apollolake/lpss.c | 31 +++++++++++++++++++++++++++++++
arch/x86/include/asm/lpss.h | 11 +++++++++++
3 files changed, 43 insertions(+)
create mode 100644 arch/x86/cpu/apollolake/lpss.c
create mode 100644 arch/x86/include/asm/lpss.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 5d98a5a6db2..b58ef8e019c 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -2,4 +2,5 @@
#
# Copyright (c) 2016 Google, Inc
+obj-y += lpss.o
obj-y += pmc.o
diff --git a/arch/x86/cpu/apollolake/lpss.c b/arch/x86/cpu/apollolake/lpss.c
new file mode 100644
index 00000000000..2f4aea79c07
--- /dev/null
+++ b/arch/x86/cpu/apollolake/lpss.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Special driver to handle of-platdata
+ *
+ * Copyright 2019 Google LLC
+ *
+ * Some code from coreboot lpss.c
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/lpss.h>
+
+enum {
+ LPSS_RESET_CTL_REG = 0x204,
+
+ /*
+ * Bit 1:0 controls LPSS controller reset.
+ *
+ * 00 ->LPSS Host Controller is in reset (Reset Asserted)
+ * 01/10 ->Reserved
+ * 11 ->LPSS Host Controller is NOT at reset (Reset Released)
+ */
+ LPSS_CNT_RST_RELEASE = 3,
+};
+
+/* Take controller out of reset */
+void lpss_reset_release(void *regs)
+{
+ writel(LPSS_CNT_RST_RELEASE, regs + LPSS_RESET_CTL_REG);
+}
diff --git a/arch/x86/include/asm/lpss.h b/arch/x86/include/asm/lpss.h
new file mode 100644
index 00000000000..4bd56a5fa30
--- /dev/null
+++ b/arch/x86/include/asm/lpss.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef __ASM_LPSS_H
+#define __ASM_LPSS_H
+
+void lpss_reset_release(void *regs);
+
+#endif
--
2.23.0.866.gb869b98d4c-goog
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