On Fri, Apr 14, 2017 at 6:15 PM, Marek Vasut wrote:
> On 04/13/2017 07:41 PM, Ley Foon Tan wrote:
>> Restructure clock manager driver in the preparation to support A10.
>> Move the Gen5 specific code to _gen5 files.
>>
>> - Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
>
- Add SD secure boot target for ls1043ardb.
- Implement FSL_LSCH2 specific spl_board_init() to setup CAAM stream ID and
corresponding stream ID in SMMU.
- Change the u-boot size defined by a macro for copying the main U-Boot by SPL
to also include the u-boot Secure Boot header size as header is
Add NAND secure boot target for ls1043ardb.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size as
header is appended to u-boot image. So header will also be copied from SD to
DDR.
- MACRO for CONFIG_BOOTSCRIPT_COPY
- Add SD secure boot target for ls1046ardb.
- Change the u-boot size defined by a macro for copying the main U-Boot by SPL
to also include the u-boot Secure Boot header size as header is appended to
u-boot image. So header will also be copied from SD to DDR.
- CONFIG_MAX_SPL_SIZE is limited to
On Mon, Apr 17, 2017 at 3:38 AM, Chen-Yu Tsai wrote:
> Hi,
>
> (Resent from my main email address.)
>
> What's the current status of u-boot-sunxi? There are still some
> patch series floating around. Some of them have been around for
> a while now, listed here in no particular order:
>
> - sunxi
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Wednesday, April 12, 2017 9:10 PM
> To: Ruchika Gupta ; u-boot@lists.denx.de
> Cc: Vini Pillai ; Sumit Garg
> Subject: Re: [PATCH 1/3][v3] arm: ls1043ardb: Add SD secure boot target
>
> On 04/04/2017 10:36 AM, Ruchi
RK3399 device memory region is 0xf800~0x.
Signed-off-by: Kever Yang
---
arch/arm/mach-rockchip/rk3399/rk3399.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c
b/arch/arm/mach-rockchip/rk3399/rk3399.c
index 8bb950e..
Hi Philipp,
On 04/14/2017 06:51 PM, Dr. Philipp Tomsich wrote:
Kever,
Do we really need to change the SPL layout (i.e. BL2) for this?
The SPL code should remain independent of later stages. This change would tie
the
U-Boot SPL (BL2) to a specific implementation/memory layout of the later BL3
Hi Bin,
On 12.04.2017 10:14, Bin Meng wrote:
> On Wed, Mar 22, 2017 at 4:06 AM, Simon Glass wrote:
>> Hi Bin,
>>
>> On 16 March 2017 at 08:26, Bin Meng wrote:
>>> In an S3 resume path, U-Boot does everything like a cold boot except
>>> in the last_stage_init() it jumps to the OS resume vector.
>
Enable gmac for evb-rk3399.
Signed-off-by: Kever Yang
---
Changes in v2:
- correct rst pin number
arch/arm/dts/rk3399-evb.dts | 24
configs/evb-rk3399_defconfig | 4
2 files changed, 28 insertions(+)
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk339
The pwm3 on evb-rk3399 is used for pwm regulator, need to invert
the polarity to make it works correct.
Signed-off-by: Kever Yang
---
arch/arm/dts/rk3399-evb.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index d
Eric Gao (2):
rockchip: video: Kconfig: Add Kconfig for rockchip video driver
rockchip: video: Makefile: Modify Makefile for rockchip video driver
configs/chromebit_mickey_defconfig | 1 +
configs/chromebook_jerry_defconfig | 2 ++
configs/chromebook_minnie_defconfig | 2 ++
configs/fire
1. add Kconfig for rockchip video driver, so that video port can be
selected as needed.
2. move VIDEO_ROCKCHIP option to new Kconfig for concision.
Signed-off-by: Eric Gao
---
configs/chromebit_mickey_defconfig | 1 +
configs/chromebook_jerry_defconfig | 2 ++
configs/chromebook_minnie_def
Modify Makefile for rockchip video driver according to Kconfig, so that
source code will not be compiled if not needed.
Signed-off-by: Eric Gao
---
drivers/video/rockchip/Makefile | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/video/rockchip/Makefile b/driver
1. add Kconfig for rockchip video driver, so that video port can be
selected as needed.
2. move VIDEO_ROCKCHIP option to new Kconfig for concision.
Signed-off-by: Eric Gao
---
configs/chromebit_mickey_defconfig | 1 +
configs/chromebook_jerry_defconfig | 2 ++
configs/chromebook_minnie_def
patch 1: add Kconfig file rockchip video driver.
patch 2: modify Makefile according to the new Kconfig.
Eric Gao (2):
rockchip: video: Kconfig: Add Kconfig for rockchip video driver
rockchip: video: Makefile: Modify Makefile for rockchip video driver
configs/chromebit_mickey_defconfig | 1
Modify Makefile for rockchip video driver according to Kconfig, so that
source code will not be compiled if not needed.
Signed-off-by: Eric Gao
---
drivers/video/rockchip/Makefile | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/video/rockchip/Makefile b/drivers
On 04/17/2017 06:49 AM, Ley Foon Tan wrote:
> On Fri, Apr 14, 2017 at 6:20 PM, Marek Vasut wrote:
>> On 04/13/2017 07:41 PM, Ley Foon Tan wrote:
>>> Add i2c, timer and other A10 macros.
>>
>> What's NOC anyway ?
> Network on chip.
Ah, OK :)
>>> Signed-off-by: Ley Foon Tan
>>> ---
>>> arch/arm/
On 04/17/2017 05:05 AM, Ley Foon Tan wrote:
> On Fri, Apr 14, 2017 at 6:25 PM, Marek Vasut wrote:
>> On 04/13/2017 07:41 PM, Ley Foon Tan wrote:
>>> Add config and defconfig for the Arria10 and update socfpga_common.h.
>>>
>>> Signed-off-by: Tien Fong Chee
>>> Signed-off-by: Ley Foon Tan
>>
>> [
On 04/17/2017 09:20 AM, Ley Foon Tan wrote:
> On Fri, Apr 14, 2017 at 6:15 PM, Marek Vasut wrote:
>> On 04/13/2017 07:41 PM, Ley Foon Tan wrote:
>>> Restructure clock manager driver in the preparation to support A10.
>>> Move the Gen5 specific code to _gen5 files.
>>>
>>> - Change all uint32_t to
If the tx_delay is not enabled, the RGMII/1000M can't work.
Signed-off-by: David Wu
---
arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
b/arch/arm/include/asm/arch-rockchip/grf_rk
Hi Oliver,
On 10 April 2017 at 09:33, Olliver Schinagl wrote:
> In certain conditions we currently print the MAC address. For example a
> warning when a random mac address is in use or a missmatch between HW
> and ENV.
>
> If all things went well however (but even if there is a miss-match) we
> d
ARM errata 852421 and 852423 applies to r1p0, r1p1 and r1p2
revisions of Cortex-A17 processors. These workarounds
exist in Linux kernel and I thought it would be better
to add them in to U-Boot.
Signed-off-by: Nisal Menuka
---
arch/arm/cpu/armv7/start.S | 12
1 file changed, 12 inse
When MC is loaded, but DPL is not deployed, it results in FDT fix-up
code execution hang.
To resolve this, returns success instead of return -ENODEV and print message
on console.
This update allows to continue fdt fixup execution.
Signed-off-by: Yogesh Gaur
Signed-off-by: Priyanka Jain
---
Chang
On Sun, Apr 16, 2017 at 08:22:17PM -0600, Simon Glass wrote:
> These should follow the UBoot standard. Update them.
>
> Signed-off-by: Simon Glass
> ---
>
> include/fdt.h| 46 +-
> include/libfdt.h | 46 +--
This patch series copies the Linux Device trees for the OMAP3 and
OMAP3630 platforms as well as some additional device trees to support
the Logic PD Torpedo and Logic PD SOM-LV both based on DM3730
(OMAP3630) processors. There are no changes to patches 2-6 from the
initial version posted as RFC, b
This patch changes the way DM_MMC calculates offset to the base register of
MMC. Previously this was through an #ifdef but that wasn't necessary for OMAP3.
This patch will now add in the offset to the base address based on the
.compatible flags.
Signed-off-by: Adam Ford
V2: Remove ifdef complet
Add device tree support to allow for CONFIG_OF_CONTROL in OMAP3630 boards.
DM3730 can use this same device tree.
Signed-off-by: Adam Ford
Reviewed-by: Lokesh Vutla
diff --git a/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi
b/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi
new file mode 100644
index 00
Many OMAP3 boards use a TWL4030 PMIC. This brings in the related
device tree information for common TWL4030 and TWL4030 with OMAP3.
Signed-off-by: Adam Ford
Reviewed-by: Lokesh Vutla
diff --git a/arch/arm/dts/twl4030.dtsi b/arch/arm/dts/twl4030.dtsi
new file mode 100644
index 000..6cb0a01
Add device tree support to allow for CONFIG_OF_CONTROL in OMAP3 boards.
Signed-off-by: Adam Ford
Reviewed-by: Lokesh Vutla
diff --git a/arch/arm/dts/omap3.dtsi b/arch/arm/dts/omap3.dtsi
new file mode 100644
index 000..a0f2412
--- /dev/null
+++ b/arch/arm/dts/omap3.dtsi
@@ -0,0 +1,854 @@
+/*
Some OMAP3 devices support an SMSC ethernet PHY connected to the GPMC bus.
This copies this device tree from Linux 4.9.y stable
Signed-off-by: Adam Ford
Reviewed-by: Lokesh Vutla
diff --git a/arch/arm/dts/omap-gpmc-smsc9221.dtsi
b/arch/arm/dts/omap-gpmc-smsc9221.dtsi
new file mode 100644
index
This patch also removes all the excessive code for NS16550 intiailization
as the device tree can do that now. This also adds DM_I2C and DM_MMC
since the overlying drivers have the built-in support already. The
corresponding include/config/omap3_logic.h also reduced in size
due to the new device t
This adds the device tree. Previous commit added both boards at the
same time.
Signed-off-by: Adam Ford
Changes in V2:
Split the SOM-LV from Torpedo
diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
b/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
new file mode 100644
index 000..170
Hi Tom,
2017-04-17 22:05 GMT+09:00 Tom Rini :
> On Sun, Apr 16, 2017 at 08:22:17PM -0600, Simon Glass wrote:
>
>> These should follow the UBoot standard. Update them.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> include/fdt.h| 46 +-
>> include/l
Previous commit has this combined with SOM-LV. This commit has only
the Torpedo Device Tree.
The device trees were sync'd with 4.9.y stable with two changes:
disable mmc2 and stdout-path = &uart1. Both of those two changes
will be submitted to the linux-omap list
Signed-off-by: Adam Ford
Chan
New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
(4430/60/70), OMAP5 (5430) and AM335X (3359) were added in 960187ffa125(
"ARM: OMAP: I2C: New read, write and probe functions") but not tested
on OMAP3. This patch will allow the updated drivers using device tree and
DM_I2C to operat
There are more and more cases where if we do not use gcc-6.0 or later we
run into problems where our binaries are too large for the targets.
Given the prevalence of gcc-6.0 or later toolchains at this point in
time, we give notice now that starting with v2018.01 we will require
gcc-6 (or later) for
On Mon, Apr 10, 2017 at 4:43 AM, Fabio Estevam wrote:
> On Sun, Apr 9, 2017 at 4:12 PM, Jagan Teki wrote:
>
>> Bcz we need to define dtb through CONFIG_DEFAULT_DEVICE_TREE
>
> Having 3 defconfigs for SPL is not good. Looks like a step in the
> opposite direction.
>
> Can this limitation be change
On Mon, Apr 17, 2017 at 10:13:06PM +0900, Masahiro Yamada wrote:
> Hi Tom,
>
>
> 2017-04-17 22:05 GMT+09:00 Tom Rini :
> > On Sun, Apr 16, 2017 at 08:22:17PM -0600, Simon Glass wrote:
> >
> >> These should follow the UBoot standard. Update them.
> >>
> >> Signed-off-by: Simon Glass
> >> ---
> >>
Hi Tom,
On 17 April 2017 at 07:33, Tom Rini wrote:
>
> On Mon, Apr 17, 2017 at 10:13:06PM +0900, Masahiro Yamada wrote:
> > Hi Tom,
> >
> >
> > 2017-04-17 22:05 GMT+09:00 Tom Rini :
> > > On Sun, Apr 16, 2017 at 08:22:17PM -0600, Simon Glass wrote:
> > >
> > >> These should follow the UBoot stand
On Mon, Apr 17, 2017 at 07:47:34AM -0600, Simon Glass wrote:
> Hi Tom,
>
> On 17 April 2017 at 07:33, Tom Rini wrote:
> >
> > On Mon, Apr 17, 2017 at 10:13:06PM +0900, Masahiro Yamada wrote:
> > > Hi Tom,
> > >
> > >
> > > 2017-04-17 22:05 GMT+09:00 Tom Rini :
> > > > On Sun, Apr 16, 2017 at 08:2
Eric Gao (8):
rockchip: video: Add mipi dsi driver for rk3399
rockchip: video: vop: Add mipi display mode for rk3399
rockchip: video: vop: Set different bitwidth for different display mode
rockchip: video: vop: Reserve enough space for mipi dispaly
rockchip: board: evb_rk3399: initialize
Signed-off-by: Eric Gao
---
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 25 ++
arch/arm/include/asm/arch-rockchip/mipi_rk3399.h | 195 +
drivers/video/rockchip/Kconfig | 11 +-
drivers/video/rockchip/Makefile | 1 +
drivers/video/rockchip/rk
Add mipi display mode for rk3399 vop, so that we can use mipi panel
for display.
Signed-off-by: Eric Gao
---
arch/arm/include/asm/arch-rockchip/vop_rk3288.h | 1 +
drivers/video/rockchip/rk_vop.c | 6 ++
2 files changed, 7 insertions(+)
diff --git a/arch/arm/include/asm/arc
Because the bitwidth is different for different display mode, so we need
to set them according to demand.
Signed-off-by: Eric Gao
---
drivers/video/rockchip/rk_vop.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/video/rockchip/rk_vop.c b/drive
plat->size here is used to reserve enough frame buffer space befor relocation.
our mipi display mode need more space, so reset it.
Signed-off-by: Eric Gao
---
drivers/video/rockchip/rk_vop.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/rockchip/rk_vop.c b/dr
Signed-off-by: Eric Gao
---
board/rockchip/evb_rk3399/evb-rk3399.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c
b/board/rockchip/evb_rk3399/evb-rk3399.c
index 362fa0b..76ab467 100644
--- a/board/rockchip/evb_rk3399/evb-rk3399.c
+++ b/board/ro
patch 1: add Kconfig file rockchip video driver.
patch 2: modify Makefile according to the new Kconfig.
Eric Gao (2):
rockchip: video: Kconfig: Add Kconfig for rockchip video driver
rockchip: video: Makefile: Modify Makefile for rockchip video driver
configs/chromebit_mickey_defconfig | 1
Add dts config for mipi display, include vop, mipi controller, panel, backlight
. And Enable rk808 for lcd_3v3 in another patch.
Signed-off-by: Eric Gao
---
arch/arm/dts/rk3399-evb.dts | 84 +
arch/arm/dts/rk3399.dtsi| 72 +
The function clk_set_rate() will return it's input parameter, so it's return
value in normal condition is nonzero. In this case, we should report an error
when it return zero rather than return a nonzero value.
Signed-off-by: Eric Gao
---
drivers/video/rockchip/rk_vop.c | 2 +-
1 file changed,
Enable mipi dsi by default for rk3399-evb board
Signed-off-by: Eric Gao
---
configs/evb-rk3399_defconfig| 6 ++
drivers/video/rockchip/Kconfig | 2 +-
drivers/video/rockchip/Makefile | 2 +-
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/configs/evb-rk3399_defconfig b/c
Modify Makefile for rockchip video driver according to Kconfig, so that
source code will not be compiled if not needed.
Signed-off-by: Eric Gao
---
drivers/video/rockchip/Makefile | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/video/rockchip/Makefile b/drivers
1. add Kconfig for rockchip video driver, so that video port can be
selected as needed.
2. move VIDEO_ROCKCHIP option to new Kconfig for concision.
Signed-off-by: Eric Gao
---
configs/chromebit_mickey_defconfig | 1 +
configs/chromebook_jerry_defconfig | 2 ++
configs/chromebook_minnie_def
On Thu, Apr 13, 2017 at 3:10 AM, Peng Fan wrote:
> +#define BOARD_REV_C 0x300
> +#define BOARD_REV_B 0x200
> +#define BOARD_REV_A 0x100
> +
> +static int mx7sabre_rev(void)
> +{
> + /*
> +* Get Board ID information from OCOTP_GP1[15:8]
> +* i.MX7D SDB RevA: 0x41
> +
This change adds support for configuring the module clocks for SPI1 and
SPI5 from the 594MHz GPLL.
Note that the driver (rk_spi.c) always sets this to 99MHz, but the
implemented functionality is more general and will also support
different clock configurations.
X-AffectedPlatforms: RK3399-Q7
Sign
To provide more (runtime) configuration points for the SPI data rate
at higher speeds (e.g. above 9MHz), we increase the module input rate
to 198MHz (from 99MHz) for the RK3399.
Signed-off-by: Philipp Tomsich
---
Changes in v3:
- increase the module input clock from 99MHz to 198MHz for the RK33
From: Jakob Unterwurzacher
The existing Rockchip SPI (rk_spi.c) driver also matches the hardware
block found in the RK3399. This has been confirmed both with SPI NOR
flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5.
This change adds the 'rockchip,rk3399-spi' string to its co
The original code for the clock clamping did not support going up to
half the module input frequency (even when clocking the module at
99MHz), as a hard limit (of 48MHz) was used for the maximum bitrate.
This rewrites the check to allow frequencies of up to half the SPI
module rate as bitrates and
To include the ability to load from an SPI flash in SPL, it's not
sufficient to define SPL_SPI_SUPPORT and SPL_SPI_FLASH_SUPPORT via
Kconfig... so we conditionally define SPL_SPI_LOAD if SPI support
is already enabled for SPL via Kconfig.
Signed-off-by: Philipp Tomsich
---
Changes in v3: None
C
To support SPI flashes (via the device model) and enable loading of
later-stage images from SPI in SPL, we need a few adjustments to the
common configuration header for the RK3399:
- enable SPL_SPI_LOAD if SPI is enabled for SPL (in rk3399_common)
- move CONFIG_SPI and CONFIG_SPI_FLASH (from rk3
When OF control is enabled for the SPL stage, nodes are removed from
the DTB to reduce its size. While /chosen is kept, /config is removed.
There's no reason why /chosen should be kept over /config (and as we
would like to put properties into /config that control the SPL stage),
we add '/config' t
For the RK3399, i2c_set_rate (and by extension: our spi_set_rate,
which had been mindlessly following the template of the i2c_set_rate
implementation) miscalculates the rate returned due to a off-by-one
error resulting from the following sequence of events:
1. calculates 'src_div := src_freq / ta
This commit adds support for the pin-configuration of the SPI5
controller of the RK3399 through the following changes:
* grf_rk3399.h: adds definition for configuring the SPI5 pins
in the GPIO2C group
* periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
* pinctrl_rk3399.c:
This adds documentation on the u-boot,spl-payload-offset property
(which overrides CONFIG_SYS_SPI_U_BOOT_OFFS during the SPI loading in
the SPL stage, if present).
Signed-off-by: Philipp Tomsich
---
doc/device-tree-bindings/config.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/doc
For the RK3399-Q7, we need some flexibility (depending on the feature
set we include in the SPL stage and how large our SPI flash is) in
positioning the SPL payload (i.e. the FIT image containing U-Boot, ATF
and the M0 payload) in our SPI flash.
To avoid having to deal with this through different
In (first) breaking and (then) fixing the rkspi tool, I realised that
the calculation of the required padding (for the header-size and the
2K-in-every-4K SPI layout) was not as self-explainatory as it could
have been. This change rewrites the code (using new, common functions
in rkcommon.c) and ad
We support booting both from SD/MMC images and SPI images on the
RK3399-Q7 for different use-cases (e.g. external boot in development
from the SD card, internal boot from MMC or SPI depending on whether
the SPI flash is populated on any given configuration option).
In getting the SPI image suppor
Dumpimage (it invoked with "-T rkspi" or "-T rksd") would not work due
to check_params failing. These changes ensure that we can both be called
with an empty imagename.
Signed-off-by: Philipp Tomsich
---
tools/rkcommon.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
d
The rockchip image generation was previously missing the ability to
verify the generated header (and dump the image-type) without having
to resort to hexdump or od. Experience in our testing has showed it
to be very easy to get the rkspi and rksd images mixed up and the
lab... so we add the necessa
Signed-off-by: Philipp Tomsich
---
tools/rksd.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/tools/rksd.c b/tools/rksd.c
index 6dafedf..8627b6d 100644
--- a/tools/rksd.c
+++ b/tools/rksd.c
@@ -62,8 +62,11 @@ static int rksd_check_image_type(uint8_t type)
static int
The calculation of the variable header size in rkcommon_vrec_header
had been update twice in the earlier series (introducing boot0-style
images to deal with the alignment of the first instruction in 64bit
binaries). Unfortunately, I didn't update the comment twice (so it
remained out-of-date).
Thi
This change set adds documentation to the header0 initialisation and
improves readability for the calculations of various offsets/lengths.
As the U-Boot SPL stage doesn't use any payload beyond what is covered
by init_size, we no longer add RK_MAX_BOOT_SIZE to init_boot_size.
Signed-off-by: Phili
Our earlier change broke the generation of SPI images, by excluding the
2K used for header0 from the size-calculation.
This commit makes sure that these are included before calculating the
required total size (including the padding from the 2K-from-every-4K
conversion).
Signed-off-by: Philipp Tom
With our validation having progresses to the point of tuning the DRAM
interface, we can now use a DDR3-1600 timing (i.e. 800MHz base clock)
as the default for the RK3399-Q7 (Puma).
This series
- adds a DDR3-1600 timing for the RK3399-Q7
- switches the RK3399-Q7 over to use this new timing
- cl
The DDR3-1333 timings for the RK3399-Q7 (Puma) has some unintended
left-over comments in them. This change cleans the file up.
Signed-off-by: Philipp Tomsich
---
arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk3
The imagetool framework checks whether function pointer for the verify,
print and extract actions are available and will will handle their
absence appropriately.
This change removes the unnecessary functions and uses the driver
structure to convey available functionality to imagetool. This is in
With the validation done for DDR3-1600 (i.e. 800 MHz bus clock), we
add the timings (rk3399-sdram-ddr3-1600.dtsi) and change rk3399-puma.dts
to use these by default.
Signed-off-by: Philipp Tomsich
---
arch/arm/dts/rk3399-puma.dts |6 +-
arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi
We used to have opencoded ehci_readl()/writel() which required no
external functions to be called.
Now with attempt to switch to generic readl()/writel() accessors
we see a missing declaration of those accessors in ehci-ppc4xx.
Something like that happens if applied
http://patchwork.ozlabs.org/pat
On Sun, Apr 16, 2017 at 10:13:55AM +0530, Lokesh Vutla wrote:
> As per the DM[1] Dated June 2016–Revised February 2017, Table 5-3,
> DRA71 supports the following OPPs for various voltage domains:
>
> VDD_MPU: OPP_NOM
> VDD_CORE: OPP_NOM
> VDD_GPU: OPP_NOM
> VDD_DSPEVE: OPP_NOM, OP
On Sun, Apr 16, 2017 at 11:21:28AM +0530, Lokesh Vutla wrote:
> Standardise U-Boot prompt on all keystone2 platforms
> instead of platform specific prompt.
>
> Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
--
Tom
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Hi Tom, Marek,
On Fri, 2017-04-14 at 16:06 -0400, Tom Rini wrote:
> On Fri, Apr 14, 2017 at 05:16:11PM +, Alexey Brodkin wrote:
> >
> > Hi Marek,
> >
> > On Fri, 2017-04-14 at 16:44 +0200, Marek Vasut wrote:
> > >
> > > On 03/24/2017 01:56 PM, Marek Vasut wrote:
> > > >
> > > >
> > > Eve
On Mon, Apr 17, 2017 at 04:19:17PM +, Alexey Brodkin wrote:
> Hi Tom, Marek,
>
> On Fri, 2017-04-14 at 16:06 -0400, Tom Rini wrote:
> > On Fri, Apr 14, 2017 at 05:16:11PM +, Alexey Brodkin wrote:
> > >
> > > Hi Marek,
> > >
> > > On Fri, 2017-04-14 at 16:44 +0200, Marek Vasut wrote:
> >
Hi Simon,
El 16/04/2017 a las 21:34, Simon Glass escribió:
> Hi Alvaro,
>
> On 15 April 2017 at 16:03, Álvaro Fernández Rojas wrote:
>> Add a new sysreset driver based on linux/drivers/power/reset/syscon-reboot.c,
>> which provides a generic driver for platforms that only require writing a
>> m
Hi Alvaro,
On 17 April 2017 at 11:38, Álvaro Fernández Rojas wrote:
>
> Hi Simon,
>
> El 16/04/2017 a las 21:34, Simon Glass escribió:
> > Hi Alvaro,
> >
> > On 15 April 2017 at 16:03, Álvaro Fernández Rojas wrote:
> >> Add a new sysreset driver based on
> >> linux/drivers/power/reset/syscon-re
This series expands support for Aspeed AST2500 SoC, commonly used as
Board Management Controller in many servers.
The main goal of this series is I2C driver, the rest are
either cleanups or supporting patches. Most notable among them is
addition of Watchdog uclass, so that watchdog drivers can now
Enable Pinctrl Driver in AST2500 Eval Board's defconfig
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
configs/evb-ast2500_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 74808a71ee..f8ef9b779c 100644
--- a/
This change switches all existing users of ast2500 Watchdog to Driver
Model based Watchdog driver.
To perform system reset Sysreset Driver uses first Watchdog device found
via uclass_first_device call. Since the system is going to be reset
anyway it does not make much difference which watchdog is
Add Reset Driver configuration to ast2500 SoC Device Tree and bindings
for various reset signals
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
arch/arm/dts/ast2500-evb.dts | 15 +++
arch/arm/dts/ast2500-u-boot.dtsi | 10 +++
include/dt-bindings/reset/ast
Add Device Model based I2C driver for ast2500/ast2400 SoCs.
The driver is very limited, it only supports master mode and
synchronous byte-by-byte reads/writes, no DMA or Pool Buffers.
Signed-off-by: Maxim Sloyko
---
Changes in v1:
- Style fixes
---
drivers/i2c/Kconfig | 9 ++
drivers/i2c
Add support for clocks needed by MACs to ast2500 clock driver.
The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
PCLK_MAC2 for MAC1 and MAC2 respectively.
The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed
SDK. It is not entirely clear from the datasheet how th
Remove unnecessary apb and ahb nodes and just override necessary
nodes/values.
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
---
arch/arm/dts/ast2500-u-boot.dtsi | 41
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/arch/arm/dts/
This driver supports ast2500 and ast2400 SoCs.
Only ast2500 supports reset_mask and thus the option of resettting
individual peripherals using WDT.
Signed-off-by: Maxim Sloyko
---
Changes in v1:
- Rename reset to expire_now
- Rename restart to reset
---
arch/arm/include/asm/arch-aspeed/wdt.h
This is a simple uclass for Watchdog Timers. It has four operations:
start, restart, reset, stop. Drivers must implement start, restart and
stop operations, while implementing reset is optional: It's default
implementation expires watchdog timer in one clock tick.
Signed-off-by: Maxim Sloyko
---
Pull in the Device Tree for ast2500 from the mainline Linux kernel.
The file is copied from
https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi
Signed-off-by: Maxim Sloyko
---
Changes in v1:
- Added link to the original version to commit message
---
arch
Enable I2C driver in ast2500 Eval Board defconfig.
Also enable i2c command.
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
configs/evb-ast2500_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index f8ef9b779c..0
Make functions for locking and unlocking SCU part of SCU API.
Many drivers need to modify settings in SCU and thus need to unlock it
first. This change makes it possible.
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 14 ++
arc
On Sun, Apr 16, 2017 at 7:50 PM, Nisal Menuka wrote:
> ARM errata 852421 and 852423 applies to r1p0, r1p1 and r1p2
> revisions of Cortex-A17 processors. These workarounds
> exist in Linux kernel and I thought it would be better
> to add them in to U-Boot.
>
> Signed-off-by: Nisal Menuka
> ---
>
This driver uses Generic Pinctrl framework and is compatible with
the Linux driver for ast2500: it uses the same device tree
configuration.
Not all pins are supported by the driver at the moment, so it actually
compatible with ast2400. In general, however, there are differences that
in the future
Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to
perform resets and thus depends on it. The actual Watchdog device used
needs to be configured in Device Tree using "aspeed,wdt" property, which
must be WDT phandle, for example:
rst: reset-controller {
compatible = "aspeed,as
Refactor SCU header to use consistent Mask & Shift values.
Now, consistently, to read value from SCU register, mask needs
to be applied before shift.
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 12
arch/arm/mach-aspeed/ast2500/s
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