On Fri, Apr 14, 2017 at 6:15 PM, Marek Vasut <ma...@denx.de> wrote:
> On 04/13/2017 07:41 PM, Ley Foon Tan wrote:
>> Restructure clock manager driver in the preparation to support A10.
>> Move the Gen5 specific code to _gen5 files.
>>
>> - Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
>> - Check return value from wait_for_bit(). So change return type to int for
>> cm_write_with_phase() and cm_basic_init().
>>
>> Signed-off-by: Ley Foon Tan <ley.foon....@intel.com>
>
> [...]
>
>> /* function to write a clock register that has phase information */
>> -static void cm_write_with_phase(uint32_t value,
>> - uint32_t reg_address, uint32_t mask)
>> +static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask)
>> {
>> + int ret;
>> +
>> /* poll until phase is zero */
>> - while (readl(reg_address) & mask)
>> - ;
>> + ret = wait_for_bit(__func__, (const u32 *)reg_address, mask,
>> + false, 20000, false);
>> + if (ret)
>> + return ret;
>>
>> writel(value, reg_address);
>>
>> - while (readl(reg_address) & mask)
>> - ;
>> + return wait_for_bit(__func__, (const u32 *)reg_address, mask,
>> + false, 20000, false);
>> }
>>
>
> Could it be that this active wait is here so that it'd work without an
> initialized timer ? Because at this point, you don't have timer and I
> think wait_for_bit() uses timer.
>
Timer is initialized before calling to this function. So, should be no problem.
In arch/arm/mach-socfpga/spl.c, timer is initialized before calling to
cm_basic_init(). Note, cm_write_with_phase() is called by
cm_basic_init().
socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
timer_init();
debug("Reconfigure Clock Manager\n");
/* reconfigure the PLLs */
if (cm_basic_init(cm_default_cfg))
hang();
Regards
Ley Foon
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