The original code for the clock clamping did not support going up to
half the module input frequency (even when clocking the module at
99MHz), as a hard limit (of 48MHz) was used for the maximum bitrate.
This rewrites the check to allow frequencies of up to half the SPI
module rate as bitrates and then clamps to whatever the DTS allows
as a maximum (board-specific) frequency.
Signed-off-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
Changes in v3:
- change the top bitrate permissible (without generating a -EINVAL)
from 48MHz/MBit to half the input clockrate (i.e. 49.5MHz/MBit for
a 99MHz module input clock)
Changes in v2: None
drivers/spi/rk_spi.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 63cceef..d518f9d 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -372,10 +372,17 @@ static int rockchip_spi_set_speed(struct udevice *bus,
uint speed)
{
struct rockchip_spi_priv *priv = dev_get_priv(bus);
- if (speed > ROCKCHIP_SPI_MAX_RATE)
+ /*
+ * The minimum divider configurable is 2, so we can't exceed
+ * half the input frequency for the SPI module.
+ */
+ if (speed > (priv->input_rate / 2))
return -EINVAL;
+
+ /* Clamp to the maximum frequency specified in the DTS */
if (speed > priv->max_freq)
speed = priv->max_freq;
+
priv->speed_hz = speed;
return 0;
--
1.9.1
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