Hi,
Marek Vasut writes:
>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>> index b2c7eb1..f58c7ba 100644
>> --- a/drivers/usb/dwc3/core.c
>> +++ b/drivers/usb/dwc3/core.c
>> @@ -125,6 +125,8 @@ static struct dwc3_event_buffer
>> *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
>
Hi,
Marek Vasut writes:
Merely using dma_alloc_coherent does not ensure that there is no stale
data left in the caches for the allocated DMA buffer (i.e. that the
affected cacheline may still be dirty).
The original code was doing the following (on AArch64, which
tr
Hi
> -Original Message-
> From: Masahiro Yamada [mailto:yamada.masah...@socionext.com]
> Sent: 05 April 2017 06:36
>
> 2017-04-05 14:05 GMT+09:00 Kever Yang :
> > SPL is considered as BL2 in ATF terminology, it needs to load other
> > parts of ATF binary like BL31, BL32, SCP-BL30, and BL33
Felipe,
> On 05 Apr 2017, at 10:18, Felipe Balbi wrote:
>
>>> Good point on the “long”, especially as I just copied this from other
>>> occurences and it’s consistently wrong throughout DWC3 in U-Boot:
>>
>> Hrm, I thought the driver was ported over from Linux, so is this broken
>> in Linux to
Hi Simon
Please see my inline reply, thanks a lot!
-Original Message-
From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: 2017年4月1日 12:22
To: Ken Ma
Cc: U-Boot Mailing List; Stefan Roese; Michal Simek
Subject: [EXT] Re: [PATCH 1/7] scsi: move base, max_lun and ma
Hi Eric,
1. Please use full name in you signature;
2. add commit message for all your commits;
3. add 'rockchip' and module name for all your patches.
4. 'From: ' in not need for patch from yourself.
Thanks,
- Kever
On 04/01/2017 10:42 PM, eric@rock-chips.com wrote:
From: "eric.gao"
Hi Simon
Please see my inline reply, thanks a lot!
Yours,
Ken
-Original Message-
From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: 2017年4月1日 12:22
To: Ken Ma
Cc: U-Boot Mailing List; Stefan Roese; Michal Simek
Subject: [EXT] Re: [PATCH 3/7] scsi: call children
Signed-off-by: Santan Kumar
Signed-off-by: Priyanka Jain
---
arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
index ab83e85..4db3c76 1006
Not yet, i rebased against u-boot-net/master. As it is it is a bug however so
we should just put the fix in for now.
On April 5, 2017 8:29:22 AM CEST, Michal Simek wrote:
>On 3.4.2017 16:18, Olliver Schinagl wrote:
>> The .read_rom_hwaddr net_ops hook does not check the return value,
>which
>> i
On 4.4.2017 19:53, Joe Hershberger wrote:
> On Mon, Apr 3, 2017 at 9:18 AM, Olliver Schinagl wrote:
>>
>> The .read_rom_hwaddr net_ops hook does not check the return value, which
>> is why it was never caught that we are currently returning 0 if the
>> read_rom_hwaddr function return -ENOSYS and -
Hi Stefan, Hi Simon
Please see my inline reply, thanks!
Yours,
Ken
-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: 2017年4月3日 14:14
To: Simon Glass; Ken Ma
Cc: u-boot@lists.denx.de; Michal Simek; Kostya Porotchkin; Hua Jing; Wilson Ding
Subject: Re: [EXT] Re: [PATCH 7/7
Hi Tom,
This deals with closing down devices which have used DMA.
he following changes since commit 11db152246607868f0e74db958947fbf79f28119:
Prepare v2017.05-rc1 (2017-04-04 17:53:24 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-dm.git
for you to fetch changes
This is the 4th version of patchset to adds support for Intel Arria 10 SoC.
This version mainly resolved comments from Marek and Dinh in [v3]. Only patch
#01,
#14 and #16 have changes in this revision.
This is initial patchset enables the basic support for Arria 10 and other
features will come af
Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.
- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
cm_write_with_phase() and cm_basic
Restructure system manager in the preparation to support A10.
No functional change.
Change uint32_t to u32.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile | 5 +-
.../arm/mach-socfpga/include/mach/system_manager.h | 128 ++---
.../{system_ma
Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files. Change socfpga_per_reset() return
type to int.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile | 2 +-
arch/arm/mach-socfpga/include/mach/reset_mana
Add i2c, timer and other A10 macros.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
b/arch/arm/mach-socfpga/include/mach/base_addr_a1
Restructure misc driver in the preparation to support A10.
Move the Gen5 specific code to gen5 file.
Change all uint32_t_to u32 and check return value from
socfpga_bridges_reset.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile| 2 +-
arch/arm/mach-socfpga/includ
Add reset driver support for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile | 2 +
arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 +
.../include/mach/reset_manager_arria10.h | 144
arch/ar
Add clock driver support for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile |3 +-
arch/arm/mach-socfpga/clock_manager.c | 10 +
arch/arm/mach-socfpga/clock_manager_arria10.c | 1096 +
Add system manager register struct and macros for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
.../arm/mach-socfpga/include/mach/system_manager.h | 74 +---
.../include/mach/system_manager_arria10.h | 81 ++
2 files changed
Add sdram header file for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 380 +
1 file changed, 380 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_arria10.h
diff --git
Add misc support for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile| 1 +
arch/arm/mach-socfpga/include/mach/misc.h | 6 +
arch/arm/mach-socfpga/misc_arria10.c | 258 ++
3 files changed, 265
Add compatible strings for Intel Arria 10 SoCFPGA device.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
include/fdtdec.h | 8
lib/fdtdec.c | 8
2 files changed, 16 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index d074478..2134701 100644
Device tree files for Arria 10
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_arria10.dtsi | 859 +
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 30 +
..
Add config and defconfig for the Arria10 and update socfpga_common.h.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
configs/socfpga_arria10_defconfig | 28 ++
include/configs/socfpga_arria10_socdk.h | 66 +
include/configs/socfpg
Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have different driver.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Kconfig| 1 +
drivers/Kconfig | 2 ++
driv
Add pinmux support for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/include/mach/pinmux.h | 15 +
arch/arm/mach-socfpga/pinmux_arria10.c | 96 +
3 files chan
On 04/05/2017 04:21 AM, Simon Glass wrote:
> Hi,
>
> On 4 April 2017 at 19:26, Kever Yang wrote:
>> Hi Eddie,
>>
>>
>> We should only need to do only one time cache operation for a buffer
>>
>> ready to do DMA transfer, so you need to remove another cache invalidate
>>
>> operation for the sa
Update Kconfig and Makefile to enable Arria 10.
Clean up Makefile and sorting *.o alphanumerically.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Kconfig | 10 +
arch/arm/mach-socfpga/Makefile | 46 ++
2 file
These registers only available for Gen5 device, exclude them
from Arria 10 build.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
drivers/fpga/socfpga.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index f1b2f2c..3751574
Add SPL support for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/spl.c | 74 ++---
1 file changed, 69 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
in
Hi Jelle,
On Tue, Apr 4, 2017 at 11:59 PM, Jelle van der Waa wrote:
> @@ -22,6 +22,25 @@
> #include
> #include
> #include
> +
You also need
#include
here (in rsa-sign.c as well).
> +#if OPENSSL_VERSION_NUMBER < 0x1010L || defined(LIBRESSL_VERSION_NUMBER)
> +void RSA_get0_key(const
Add support for the Arria10 SoCDK.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
board/altera/arria10-socdk/Kconfig | 18 ++
board/altera/arria10-socdk/Makefile | 7 +++
board/altera/arria10-socdk/socfpga.c | 7 +++
3 files changed, 32 insertions(+)
Hi Jelle,
On Tue, Apr 4, 2017 at 11:59 PM, Jelle van der Waa wrote:
> @@ -20,6 +20,19 @@
> #define HAVE_ERR_REMOVE_THREAD_STATE
> #endif
>
> +#if OPENSSL_VERSION_NUMBER < 0x1010L || defined(LIBRESSL_VERSION_NUMBER)
> +void RSA_get0_key(const RSA *r,
> + const BIGNUM **n, con
Hi,
"Dr. Philipp Tomsich" writes:
Good point on the “long”, especially as I just copied this from other
occurences and it’s consistently wrong throughout DWC3 in U-Boot:
>>>
>>> Hrm, I thought the driver was ported over from Linux, so is this broken
>>> in Linux too ?
>>
>> haven't
Hi Marek,
On 5 April 2017 at 03:35, Marek Vasut wrote:
> On 04/05/2017 04:21 AM, Simon Glass wrote:
>> Hi,
>>
>> On 4 April 2017 at 19:26, Kever Yang wrote:
>>> Hi Eddie,
>>>
>>>
>>> We should only need to do only one time cache operation for a buffer
>>>
>>> ready to do DMA transfer, so you
On 4 April 2017 at 17:20, Michal Simek wrote:
> On 3.4.2017 13:38, Jean-Francois Dagenais wrote:
>>
>>> On Apr 3, 2017, at 02:55, Michal Simek wrote:
>>>
>>> This is not only one way how to configure system. You can use
>>> psu_init*.tcl and configure chip through jtag and then you don't need
>>>
On 04/04/2017 10:26 PM, Dr. Philipp Tomsich wrote:
>
>> On 04 Apr 2017, at 22:09, Marek Vasut wrote:
>>
>>> The DWC3 flush expands to a clean+invalidate. It is not wrong, as long as
>>> it is used as in my patch:
>>> a. before the first time data is expected to be written by the peripheral
>>> (
Hi Alex,
On 2 April 2017 at 02:25, Alex Deymo wrote:
> In some boards like the Raspberry Pi the initial bootloader will pass
> a DT to the kernel. When using U-boot as such kernel, the board code in
Please use 'U-Boot' consistently.
> U-Boot should be able to provide U-boot with this, already a
On 31 March 2017 at 16:31, Andre Przywara wrote:
> Currently the SPL FIT loader uses the spl_fit_select_fdt() function to
> find the offset to the right DTB within the FIT image.
> For this it iterates over all subnodes of the /configuration node in
> the FIT tree and compares all "description" st
On 31 March 2017 at 16:31, Andre Przywara wrote:
> At the moment we load two images from a FIT image: the actual U-Boot
> image and the .dtb file. Both times we have very similar code, that deals
> with alignment requirements the media we load from imposes upon us.
> Factor out this code into a ne
Hi Andre,
On 31 March 2017 at 17:21, André Przywara wrote:
> On 31/03/17 23:43, Simon Glass wrote:
>> Hi Andre,
>>
>> On 31 March 2017 at 16:31, Andre Przywara wrote:
>>> Some minor fixes version of the SPL FIT loading series and the respective
>>> patches to enable this feature on 64-bit Allwin
On 31 March 2017 at 16:31, Andre Przywara wrote:
> Currently the SPL FIT loader always looks only for the first image in
> the /images node a FIT tree, which it loads and later executes.
>
> Generalize this by looking for a "firmware" property in the matched
> configuration subnode, or, if that do
On 31 March 2017 at 16:31, Andre Przywara wrote:
> So far we were not using the FIT image format to its full potential:
> The SPL FIT loader was just loading the first image from the /images
> node plus one of the listed DTBs.
> Now with the refactored loader code it's easy to load an arbitrary
>
Hi Andre,
On 31 March 2017 at 16:31, Andre Przywara wrote:
> At the moment we ignore any errors due to missing FIT properties,
> instead go ahead and calculate our addresses with the -1 return value.
> Fix this and bail out if any of the mandatory properties are missing.
>
> Signed-off-by: Andre
> On 05 Apr 2017, at 12:25, Marek Vasut wrote:
>
> On 04/04/2017 10:26 PM, Dr. Philipp Tomsich wrote:
>>
>>> On 04 Apr 2017, at 22:09, Marek Vasut wrote:
>>>
The DWC3 flush expands to a clean+invalidate. It is not wrong, as long as
it is used as in my patch:
a. before the first
Dear Tom,
In message <20170404190647.GH19897@bill-the-cat> you wrote:
>
> Why? I'm not sure that in most cases __FILE__ is providing any more
> useful infomration on top of what we have from __func__ and __LINE__.
Is there not quite a lot of functions that are implemented in many
files? I exp
The board is now manufactured by Aries Embedded GmbH , rename it.
Signed-off-by: Marek Vasut
---
arch/arm/Kconfig | 2 +-
board/{denx => aries}/m28evk/Kconfig | 2 +-
board/{denx => aries}/m28evk/MAINTAINERS | 2 +-
board/{denx => aries}/m28evk/Makefile| 0
board/
The board is now manufactured by Aries Embedded GmbH , rename it.
Signed-off-by: Marek Vasut
---
arch/arm/Kconfig | 2 +-
board/{denx => aries}/m53evk/Kconfig | 2 +-
board/{denx => aries}/m53evk/MAINTAINERS | 2 +-
board/{denx => aries}/m53evk/Makefile | 2 +-
The board is now manufactured by Aries Embedded GmbH , rename it.
Signed-off-by: Marek Vasut
---
arch/arm/dts/socfpga_cyclone5_mcvevk.dts | 2 +-
arch/arm/mach-socfpga/Kconfig| 10 +-
board/{denx => aries}/mcvevk/MAINTAINERS | 4 ++--
board/{denx =>
There is no point in having such gargantuan buffer, it only requires
huge malloc area. Reduce the DFU buffer size.
Signed-off-by: Marek Vasut
---
include/configs/socfpga_common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/socfpga_common.h b/include/config
Add default DFU altinfo for eMMC.
Signed-off-by: Marek Vasut
---
include/configs/socfpga_mcvevk.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h
index 604ea20..2d36702 100644
--- a/include/configs/socfpga_mcvevk.h
+++ b/inc
Disable the OC test on MCVEVK as the old PHY version does not provide
this information. This fixes the USB OTG operation.
Signed-off-by: Marek Vasut
---
arch/arm/dts/socfpga_cyclone5_mcvevk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts
b/arch/a
Turing Computer is a designer and manufacturer of ARM-based
System on Modules, specialized on i.MX SoCs from Freescale/NXP.
This patch adds support for their Evaluation Board running i.MX53 SoC.
More information can be found at:
http://www.turingcomputer.com.br/
Signed-off-by: Mauricio Cirelli
-
Turing Computer is a designer and manufacturer of ARM-based
System on Modules, specialized on i.MX SoCs from Freescale/NXP.
This patch adds support for their Evaluation Board running i.MX6
Solo, Dual Lite, Dual and Quad SoCs.
There are two board revisions according to the memory available:
Full-S
2017-04-01 12:23 GMT+08:00 Simon Glass :
> Hi,
>
> On 27 March 2017 at 08:38, wrote:
> > From: Ziping Chen
> >
> > Sometimes we need to read back the status of a LED.
> >
> > Add a led_get_status function for DM LED support, and add a get_status
> > function for the driver to implement this fun
2017-04-01 12:22 GMT+08:00 Simon Glass :
> Hi,
>
> On 27 March 2017 at 08:38, wrote:
> > From: Ziping Chen
> >
> > Currently the "led" command only supports the old API without DM.
> >
> > Add DM-based implementation of this command.
> >
> > Also allow this command to be select with Kconfig.
>
On Tue, Apr 4, 2017 at 4:32 PM, Mauricio Cirelli
wrote:
>
> Turing Computer is a designer and manufacturer of ARM-based
> System on Modules, specialized on i.MX SoCs from Freescale/NXP.
> This patch adds support for their Evaluation Board running i.MX6
> Solo, Dual Lite, Dual and Quad SoCs.
>
> T
On Tue, Mar 28, 2017 at 05:05:09PM +0800, Peng Fan wrote:
> Sync with Linux commit ad0376eb1483b ("Merge tag 'edac_for_4.11_2'").
>
> Signed-off-by: Peng Fan
> Cc: Tom Rini
> ---
> include/linux/math64.h | 172
> +
> lib/div64.c| 141
On Wed, Mar 29, 2017 at 12:17:31PM +0100, Andre Przywara wrote:
> Hi,
>
> On 29/03/17 07:57, Maxime Ripard wrote:
> > On Tue, Mar 28, 2017 at 01:45:22AM +0100, Andre Przywara wrote:
> >> The Pine64 (and all other 64-bit Allwinner boards) need to load an
> >> ARM Trusted Firmware image beside the a
On Fri, Mar 31, 2017 at 10:34:35PM -0600, Simon Glass wrote:
> Hi Tom,
>
> On 31 March 2017 at 22:19, Simon Glass wrote:
> > Hi Tom,
> >
> > On 6 February 2017 at 08:32, Simon Glass wrote:
> >>
> >> Hi Tom,
> >>
> >> On 23 January 2017 at 10:22, Tom Rini wrote:
> >> > On Fri, Jan 20, 2017 at 07
On Sun, Apr 02, 2017 at 11:22:42AM +0200, Wolfgang Denk wrote:
> Dear Nobuhiro,
>
> In message <20170401224812.11646-1-iwama...@nigauri.org> you wrote:
> > The default value of BOOTSTAGE_STASH_SIZE should be set to hexadecimal,
> > but an integer value is set. This fixes the BOOTSTAGE_STASH_SIZE n
Hi Ken,
On 05.04.2017 11:29, Ken Ma wrote:
Hi Stefan, Hi Simon
Please see my inline reply, thanks!
Yours,
Ken
-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: 2017年4月3日 14:14
To: Simon Glass; Ken Ma
Cc: u-boot@lists.denx.de; Michal Simek; Kostya Porotchkin; Hua Jing;
> On 29/03/17 07:57, Maxime Ripard wrote:
>> On Tue, Mar 28, 2017 at 01:45:22AM +0100, Andre Przywara wrote:
>>> The Pine64 (and all other 64-bit Allwinner boards) need to load an
>>> ARM Trusted Firmware image beside the actual U-Boot proper.
>>> This can now be easily achieved by using the just e
Hi Tom,
Please take this PR.
thanks!
Jagan.
The following changes since commit 11db152246607868f0e74db958947fbf79f28119:
Prepare v2017.05-rc1 (2017-04-04 17:53:24 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-sunxi.git master
for you to fetch changes up to e7bd1
From: Konstantin Porotchkin
Add PCIe initialization at early init stage.
This operation has a side effect of detecting all PCIe
plug-in cards, so the operator is not obligated to issue
"pci enum" command though CLI for this purpose.
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Iga
When this board was switched to using more DM drivers we didn't disable
the legacy PCA953X driver. This in turn learn to a build time warning
about implicit functions as i2c.h would not say anything about
'i2c_read' nor 'i2c_write'. But this was not a fatal error as none of
the legacy driver woul
On 04/05/2017 10:15 AM, Felipe Balbi wrote:
>
> Hi,
>
> Marek Vasut writes:
>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>>> index b2c7eb1..f58c7ba 100644
>>> --- a/drivers/usb/dwc3/core.c
>>> +++ b/drivers/usb/dwc3/core.c
>>> @@ -125,6 +125,8 @@ static struct dwc3_event_bu
On 04/05/2017 11:32 AM, Ley Foon Tan wrote:
> Convert Altera DDR SDRAM driver to use Kconfig method.
> Enable ALTERA_SDRAM by default if it is on Gen5 target.
> Arria 10 will have different driver.
>
> Signed-off-by: Tien Fong Chee
> Signed-off-by: Ley Foon Tan
> ---
Applied, thanks.
--
Best
On 04/05/2017 12:08 PM, Simon Glass wrote:
> Hi Marek,
>
> On 5 April 2017 at 03:35, Marek Vasut wrote:
>> On 04/05/2017 04:21 AM, Simon Glass wrote:
>>> Hi,
>>>
>>> On 4 April 2017 at 19:26, Kever Yang wrote:
Hi Eddie,
We should only need to do only one time cache operat
On 04/05/2017 11:32 AM, Ley Foon Tan wrote:
> Add compatible strings for Intel Arria 10 SoCFPGA device.
>
> Signed-off-by: Tien Fong Chee
> Signed-off-by: Ley Foon Tan
> ---
Applied.
--
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists
On 04/05/2017 11:32 AM, Ley Foon Tan wrote:
> Restructure misc driver in the preparation to support A10.
> Move the Gen5 specific code to gen5 file.
>
> Change all uint32_t_to u32 and check return value from
> socfpga_bridges_reset.
>
> Signed-off-by: Ley Foon Tan
[...]
> static void socfpga_
On 04/05/2017 12:57 PM, Dr. Philipp Tomsich wrote:
>
>> On 05 Apr 2017, at 12:25, Marek Vasut wrote:
>>
>> On 04/04/2017 10:26 PM, Dr. Philipp Tomsich wrote:
>>>
On 04 Apr 2017, at 22:09, Marek Vasut wrote:
> The DWC3 flush expands to a clean+invalidate. It is not wrong, as long as
On 04/05/2017 01:32 PM, Marek Vasut wrote:
> The board is now manufactured by Aries Embedded GmbH , rename it.
>
> Signed-off-by: Marek Vasut
Applied, thanks.
--
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.den
On 04/05/2017 11:32 AM, Ley Foon Tan wrote:
> Add misc support for Arria 10.
>
> Signed-off-by: Tien Fong Chee
> Signed-off-by: Ley Foon Tan
[...]
> +static int find_peripheral_uart(const void *blob,
> + int child, const char *node_name)
> +{
> + int len;
> + fdt_addr_t base_addr =
On 04/05/2017 10:18 AM, Felipe Balbi wrote:
>
> Hi,
>
> Marek Vasut writes:
> Merely using dma_alloc_coherent does not ensure that there is no stale
> data left in the caches for the allocated DMA buffer (i.e. that the
> affected cacheline may still be dirty).
>
> The origina
On 04/05/2017 01:42 PM, Marek Vasut wrote:
> There is no point in having such gargantuan buffer, it only requires
> huge malloc area. Reduce the DFU buffer size.
>
> Signed-off-by: Marek Vasut
Applied all three.
> ---
> include/configs/socfpga_common.h | 2 +-
> 1 file changed, 1 insertion(+),
+Tom
Hi Marek,
On 5 April 2017 at 04:21, Marek Vasut wrote:
> On 04/05/2017 12:08 PM, Simon Glass wrote:
>> Hi Marek,
>>
>> On 5 April 2017 at 03:35, Marek Vasut wrote:
>>> On 04/05/2017 04:21 AM, Simon Glass wrote:
Hi,
On 4 April 2017 at 19:26, Kever Yang wrote:
> Hi Eddie,
Hi Stefan,
> On 2017-04-04 01:23, Lukasz Majewski wrote:
> > Hi Stefan,
> >
> >> Hi Lukasz,
> >>
> >> On 2017-04-03 04:20, Lukasz Majewski wrote:
> >> > Hi Stefan,
> >> >
> >> > Thanks for your patch. Please allow me to share some ideas for
> >> > improvements.
> >> >
> >> >> From: Stefan Agner
From: Konstantin Porotchkin
Add NAND configuration parameters to A8K shared config file.
Add defconfig for db-88f7040 board with boot from NAND setup.
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Igal Liberman
Cc: Nadav Haklai
---
Changes from v1:
- Rebase on top of latest maste
From: Konstantin Porotchkin
Add NAND to CP master device tree. Add armada-7040-db-nand
device tree for the board configured with NAND boot device.
Add comment about boot device ID to armada-7040-db DTS.
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Igal Liberman
Cc: Nadav Haklai
From: Konstantin Porotchkin
Implement mvebu_get_nand_clock call for A8K family.
This function is used by PXA3XX NAND driver.
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Igal Liberman
Cc: Nadav Haklai
---
Changes from v1:
- Add TODO notice for moving the functionality to a futur
On 05/04/2017 16:46, Tom Rini wrote:
> When this board was switched to using more DM drivers we didn't disable
> the legacy PCA953X driver. This in turn learn to a build time warning
> about implicit functions as i2c.h would not say anything about
> 'i2c_read' nor 'i2c_write'. But this was not a
On 04/05/2017 02:01 AM, Santan Kumar wrote:
> Signed-off-by: Santan Kumar
> Signed-off-by: Priyanka Jain
> ---
> arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
> b/arch/arm/cpu/armv8/
Not force to use python from PATH. Issue was noted when building with
Yocto, because python from the distro is always taken instead of
python-native built during Yocto process.
Signed-off-by: Stefano Babic
CC: Simon Glass
---
Makefile | 2 +-
tools/Makefile | 2 +-
2 files changed, 2 inse
> -Original Message-
> From: york sun
> Sent: Wednesday, April 5, 2017 9:13 PM
> To: Santan Kumar ; u-boot@lists.denx.de
> Cc: Priyanka Jain
> Subject: Re: [PATCH] armv8: ls2080a: Add serdes2 protocol 0x51 support
>
> On 04/05/2017 02:01 AM, Santan Kumar wrote:
> > Signed-off-by: Santan
On 04/05/2017 08:47 AM, Santan Kumar wrote:
>
>>
>> Santan,
>>
>> Does this patch replace another one with subject "armv8: ls2081a: Add
>> serdes2 protocol 0x51 support"? It changes the same file the same way.
>> For future update, you are required to put version number and change log to
>> it.
>>
it is superseded. I have sent another patch with subject changed.
> -Original Message-
> From: Santan Kumar [mailto:santan.ku...@nxp.com]
> Sent: Wednesday, April 5, 2017 10:25 AM
> To: u-boot@lists.denx.de; york sun
> Cc: Santan Kumar ; Priyanka Jain
>
> Subject: [PATCH] armv8: ls2081a:
This series addresses some issues when the environment tools
are used as library and linked to an external program.
Stefano Babic (4):
Rename aes.h to uboot_aes.h
env: split fw_env.h in public and private parts
env: add a version number to check API
env: fix memory leak in fw_env routines
aes.h is a too generic name if this file can
be exported and used by a program.
Rename it to avoid any conflicts with
other files (for example, from openSSL).
Signed-off-by: Stefano Babic
---
arch/arm/mach-tegra/tegra20/crypto.c | 2 +-
cmd/aes.c| 2 +-
common/env_c
Move U-Boot private data into a separate file. This
lets export fw_env.h to be used by external programs
that want to change the environment using the library
built in tools/env.
Signed-off-by: Stefano Babic
---
common/env_flags.c | 1 +
tools/env/fw_env.c | 1 +
tools/env/fw_
fw_env_open allocates buffers to store the environment, but these
buffers are never freed. This becomes quite nasty using the fw_ tools as
library, because each access to the environment (even just reading a
variable) generates a memory leak equal to the size of the environment.
Fix this renaming
Changes in the environment library are difficult to tracked by programs
using the library. Add simply an API version number that must be
increased each time when the API is changed.
This can be detected and a program can work with different versions of
the library.
Signed-off-by: Stefano Babic
-
On 05/04/2017 13:31, Marek Vasut wrote:
> The board is now manufactured by Aries Embedded GmbH , rename it.
>
> Signed-off-by: Marek Vasut
> ---
> arch/arm/Kconfig | 2 +-
> board/{denx => aries}/m28evk/Kconfig | 2 +-
> board/{denx => aries}/m28evk/MAINTAINERS | 2 +-
On 05/04/2017 13:31, Marek Vasut wrote:
> The board is now manufactured by Aries Embedded GmbH , rename it.
>
> Signed-off-by: Marek Vasut
> ---
> arch/arm/Kconfig | 2 +-
> board/{denx => aries}/m53evk/Kconfig | 2 +-
> board/{denx => aries}/m53evk/MAINTAINERS | 2
"On Thu, Mar 30, 2017 at 8:29 PM, Robert Nelson wrote:
> BeagleBone Black Wireless is clone of the BeagleBone Black (BBB) with
> the Ethernet replaced by a TI wl1835 wireless module.
>
> This board can be indentified by the BWAx value after A335BNLT (BBB)
> in the at24 eeprom:
> BWAx [aa 55 33 ee
Hi Simon,
On 04/04/2017 08:27 PM, Simon Glass wrote:
> Hi Vikas,
>
> On 4 April 2017 at 15:59, Vikas Manocha wrote:
>> Address translation is not working at present even if SPL_OF_TRANSLATE is
>> enabled which makes this configuration useless. This patch enables address
>> translation for SPL U-
Hi.
2017-04-05 14:05 GMT+09:00 Kever Yang :
> --- a/common/spl/Kconfig
> +++ b/common/spl/Kconfig
> @@ -670,6 +670,20 @@ config SPL_YMODEM_SUPPORT
> means of transmitting U-Boot over a serial line for using in SPL,
> with a checksum to ensure correctness.
>
> +config SPL_ATF_
On Wed, Apr 5, 2017 at 11:14 AM, Peter Robinson wrote:
> "On Thu, Mar 30, 2017 at 8:29 PM, Robert Nelson
> wrote:
>> BeagleBone Black Wireless is clone of the BeagleBone Black (BBB) with
>> the Ethernet replaced by a TI wl1835 wireless module.
>>
>> This board can be indentified by the BWAx valu
1 - 100 of 208 matches
Mail list logo