Turing Computer is a designer and manufacturer of ARM-based System on Modules, specialized on i.MX SoCs from Freescale/NXP. This patch adds support for their Evaluation Board running i.MX6 Solo, Dual Lite, Dual and Quad SoCs.
There are two board revisions according to the memory available: Full-Sized Memory and Half-Sized (SMART) variants. More information can be found at: http://www.turingcomputer.com.br/ Signed-off-by: Mauricio Cirelli <mauri...@turingcomputer.com.br> --- arch/arm/cpu/armv7/mx6/Kconfig | 17 + board/turing/mx6turing/Kconfig | 35 ++ board/turing/mx6turing/MAINTAINERS | 6 + board/turing/mx6turing/Makefile | 10 + board/turing/mx6turing/README | 22 + board/turing/mx6turing/mx6turing.c | 800 +++++++++++++++++++++++++++++++++++++ configs/mx6turing_defconfig | 51 +++ configs/mx6turing_smart_defconfig | 51 +++ include/configs/mx6turing.h | 247 ++++++++++++ 9 files changed, 1239 insertions(+) create mode 100644 board/turing/mx6turing/Kconfig create mode 100644 board/turing/mx6turing/MAINTAINERS create mode 100644 board/turing/mx6turing/Makefile create mode 100644 board/turing/mx6turing/README create mode 100644 board/turing/mx6turing/mx6turing.c create mode 100644 configs/mx6turing_defconfig create mode 100644 configs/mx6turing_smart_defconfig create mode 100644 include/configs/mx6turing.h diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 9174136..17477c8 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -225,6 +225,22 @@ config TARGET_MX6SXSABREAUTO select DM_THERMAL select BOARD_EARLY_INIT_F +config TARGET_MX6TURING + bool "Turing Computer i.MX6 boards" + select BOARD_LATE_INIT + select SUPPORT_SPL + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + +config TARGET_MX6TURING_SMART + bool "Turing Computer i.MX6 SMART boards" + select BOARD_LATE_INIT + select SUPPORT_SPL + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + config TARGET_MX6UL_9X9_EVK bool "mx6ul_9x9_evk" select BOARD_LATE_INIT @@ -413,6 +429,7 @@ source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/toradex/apalis_imx6/Kconfig" source "board/toradex/colibri_imx6/Kconfig" +source "board/turing/mx6turing/Kconfig" source "board/udoo/Kconfig" source "board/udoo/neo/Kconfig" source "board/wandboard/Kconfig" diff --git a/board/turing/mx6turing/Kconfig b/board/turing/mx6turing/Kconfig new file mode 100644 index 0000000..72b60e5 --- /dev/null +++ b/board/turing/mx6turing/Kconfig @@ -0,0 +1,35 @@ +if TARGET_MX6TURING + +config SYS_BOARD + default "mx6turing" + +config SYS_SOC + default "mx6" + +config SYS_VENDOR + default "turing" + +config SYS_CONFIG_NAME + default "mx6turing" + +endif + +if TARGET_MX6TURING_SMART + +config SYS_BOARD + default "mx6turing" + +config SYS_SOC + default "mx6" + +config SYS_VENDOR + default "turing" + +config SYS_CONFIG_NAME + default "mx6turing" + +config TURING_SMART_VARIANT + bool "Turing Smart Variant" + default y + +endif diff --git a/board/turing/mx6turing/MAINTAINERS b/board/turing/mx6turing/MAINTAINERS new file mode 100644 index 0000000..8c8e56b --- /dev/null +++ b/board/turing/mx6turing/MAINTAINERS @@ -0,0 +1,6 @@ +MX6XTURING BOARD +M: Mauricio Cirelli <mauri...@turingcomputer.com.br> +S: Maintained +F: board/turing/imx6x/ +F: include/configs/mx6turing.h +F: configs/mx6turing_defconfig diff --git a/board/turing/mx6turing/Makefile b/board/turing/mx6turing/Makefile new file mode 100644 index 0000000..ae3466d --- /dev/null +++ b/board/turing/mx6turing/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <l...@denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ccflags-$(CONFIG_TURING_SMART_VARIANT) += -DTURING_SMART_VARIANT +obj-y := mx6turing.o diff --git a/board/turing/mx6turing/README b/board/turing/mx6turing/README new file mode 100644 index 0000000..5c9ab1e --- /dev/null +++ b/board/turing/mx6turing/README @@ -0,0 +1,22 @@ +How to use U-boot on Turing's i.MX6 Boards +----------------------------------------------------------- + +- Build U-boot for Turing's i.MX6 Boards: + +$ make mrproper +$ make mx6turing_defconfig +$ make + +This will generate the SPL image called SPL and the u-boot.img. + +- Flash the SPL image into the SD card: + +sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + +- Flash the u-boot.img image into the SD card: + +sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Insert the SD card in the board, power it up and U-boot messages should come up. + +If you want to build for SMART variants (i.MX6Q 1GB and i.MX6DL 512MB), change it accordingly in the Kconfig file. \ No newline at end of file diff --git a/board/turing/mx6turing/mx6turing.c b/board/turing/mx6turing/mx6turing.c new file mode 100644 index 0000000..e353886 --- /dev/null +++ b/board/turing/mx6turing/mx6turing.c @@ -0,0 +1,800 @@ +/* + * Copyright (C) 2015 Turing Computer. + * + * Author: Mauricio Cirelli <mauri...@turingcomputer.com.br> + * + * Copyright (C) 2013 Jon Nettleton <jon.nettle...@gmail.com> + * + * Based on SPL code from Solidrun tree, which is: + * Author: Tungyi Lin <tungyilin1...@gmail.com> + * + * Derived from EDM_CF_IMX6 code by TechNexion,Inc + * Ported to SolidRun microSOM by Rabeeh Khoury <rab...@solid-run.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/mxc_hdmi.h> +#include <linux/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/video.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <malloc.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> +#include <spl.h> +#include <usb.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define I2C_PMIC 1 + +#define DISP0_PWR_EN IMX_GPIO_NR(1, 22) +#define USB_HUB_RSTn IMX_GPIO_NR(3, 20) +#define USB_OTG_PWR_EN IMX_GPIO_NR(3, 22) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +static iomux_v3_cfg_t const uart5_pads[] = { + IOMUX_PADS(PAD_KEY_COL1__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW1__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const uart3_pads[] = { + IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(UART_PAD_CTRL)), /* CD */ +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const i2c2_pads[] = { + IOMUX_PADS(PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const gpio_pads[] = { + IOMUX_PADS(PAD_ENET_MDIO__GPIO1_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static struct i2c_pads_info i2cq_pad_info = { + .scl = { + .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 13) + } +}; + +static struct i2c_pads_info i2cdl_pad_info = { + .scl = { + .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 13) + } +}; + +#ifdef CONFIG_USB_EHCI_MX6 + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +/** + * USB OTG Pins (ID & PWR EN) + */ +static iomux_v3_cfg_t const usb_otg_pads[] = { + IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL)), +}; + +/** + * USB Host Power Enable (Hub RSTn) + */ +static iomux_v3_cfg_t const usb_hc1_pads[] = { + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void setup_usb(void) +{ + SETUP_IOMUX_PADS(usb_otg_pads); + + /* + * set daisy chain for otg_pin_id on 6q. + * for 6dl, this bit is reserved + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); + + SETUP_IOMUX_PADS(usb_hc1_pads); + + /** + * Make sure the Hub is Enabled + */ + gpio_direction_output(USB_HUB_RSTn, 1); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + port * 4); + + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} + +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + break; + case 1: + if (on) + gpio_direction_output(USB_OTG_PWR_EN, 1); + else + gpio_direction_output(USB_OTG_PWR_EN, 0); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + + return 0; +} +#endif + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart5_pads); + SETUP_IOMUX_PADS(uart3_pads); +} + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(2, 0) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = 1; /* eMMC/USDHC4 is always present */ + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ +#ifndef CONFIG_SPL_BUILD + int ret; + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 uSD (USDHC1) + * mmc1 eMMC (USDHC4) + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[i].max_bus_width = 4; + break; + case 1: + SETUP_IOMUX_PADS(usdhc4_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + usdhc_cfg[i].max_bus_width = 8; + break; + default: + printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n", + i + 1, CONFIG_SYS_FSL_USDHC_NUM); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +#else + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned reg = readl(&psrc->sbmr1) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x0 SD1 + * 0x1 SD2 + * 0x2 SD3 + * 0x3 SD4 + */ + + int port = reg & 0x3; + switch (port) { + case 0x0: + SETUP_IOMUX_PADS(usdhc1_pads); + usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + printf("Initializing USDHC1 as boot device\n"); + break; + case 0x3: + SETUP_IOMUX_PADS(usdhc4_pads); + usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + printf("Initializing USDHC4 as boot device\n"); + break; + default: + printf("Unknown USDHC boot device: 0x%x\n", port); + break; + } + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif +} +#endif + +#if defined(CONFIG_VIDEO_IPUV3) + +static void disable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + int reg = readl(&iomux->gpr[2]); + + reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | IOMUXC_GPR2_LVDS_CH1_MODE_MASK); + + writel(reg, &iomux->gpr[2]); +} + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) IOMUXC_BASE_ADDR; + u32 reg = readl(&iomux->gpr[2]); + reg |= (IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT); + writel(reg, &iomux->gpr[2]); + gpio_direction_output(DISP0_PWR_EN, 1); +} + +struct display_info_t const displays[] = { + { + .bus = 0, + .addr = 0, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "atm0700l6bt", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 30000, + .left_margin = 46, + .right_margin = 210, + .upper_margin = 23, + .lower_margin = 22, + .hsync_len = 10, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + } + } +}; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *) CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *) IOMUXC_BASE_ADDR; + + int reg; + + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET | MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK + | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK + | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) + | (CHSCCDR_PODF_DIVIDE_BY_3 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + | (CHSCCDR_IPU_PRE_CLK_540M_PFD + << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_early_init_f(void) +{ + int ret = 0; + SETUP_IOMUX_PADS(gpio_pads); + setup_iomux_uart(); + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2cq_pad_info); + } else { + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2cdl_pad_info); + } +#ifdef CONFIG_VIDEO_IPUV3 + setup_display(); +#endif +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + return ret; +} + +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return ret; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return ret; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Set VGEN3 to 2.5V */ + pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_2_50V; + pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); + + /* Set VGEN4 to 2.8V */ + pmic_reg_read(p, PFUZE100_VGEN4VOL, ®); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_2_80V; + pmic_reg_write(p, PFUZE100_VGEN4VOL, reg); + + /* Set VGEN5 to 2.8V */ + pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_2_80V; + pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); + + /* Set SW2VOLT to 3.3V */ + pmic_reg_read(p, PFUZE100_SW2VOL, ®); + reg = 0x72; /* 0x72 = 3.3V */ + pmic_reg_write(p, PFUZE100_SW2VOL, reg); + + /* Set SW4VOLT to 3.3V */ + pmic_reg_read(p, PFUZE100_SW4VOL, ®); + reg = 0x72; /* 0x72 = 3.3V */ + pmic_reg_write(p, PFUZE100_SW4VOL, reg); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: MX6-Turing\n"); + return 0; +} + +int board_late_init(void) +{ + /* Defines the processor family, to load the correct device tree binaries */ + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { + setenv("board_rev", "MX6Q"); + } else { + setenv("board_rev", "MX6DL"); + } + + /* Kernel Memory Allocation */ +#ifndef TURING_SMART_VARIANT + if (is_cpu_type(MXC_CPU_MX6Q)) { + setenv("bootargs_mem", "cma=320M"); + } else if (is_cpu_type(MXC_CPU_MX6D)) { + setenv("bootargs_mem", "cma=320M"); + } else if (is_cpu_type(MXC_CPU_MX6DL)) { + setenv("bootargs_mem", "cma=320M"); + } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { + setenv("bootargs_mem", "cma=256M"); + } +#else + if (is_cpu_type(MXC_CPU_MX6Q)) { + setenv("bootargs_mem", "cma=320M"); + } else if (is_cpu_type(MXC_CPU_MX6D)) { + setenv("bootargs_mem", "cma=320M"); + } else if (is_cpu_type(MXC_CPU_MX6DL)) { + setenv("bootargs_mem", "cma=256M"); + } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { + setenv("bootargs_mem", "cma=256M"); + } +#endif + + return 0; +} + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + return 1; +} +#endif + +#ifdef CONFIG_SPL_BUILD +#include <asm/arch/mx6-ddr.h> +static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = { + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = { + .grp_ddr_type = 0x000C0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = { + .dram_sdclk_0 = 0x00000030, + .dram_sdclk_1 = 0x00000030, + .dram_cas = 0x00000030, + .dram_ras = 0x00000030, + .dram_reset = 0x00000030, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00000030, + .dram_sdodt1 = 0x00000030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_dqm2 = 0x00000030, + .dram_dqm3 = 0x00000030, + .dram_dqm4 = 0x00000030, + .dram_dqm5 = 0x00000030, + .dram_dqm6 = 0x00000030, + .dram_dqm7 = 0x00000030, +}; + +static const struct mx6sdl_iomux_grp_regs mx6dl_grp_ioregs = { + .grp_ddr_type = 0x000C0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +/* SOM with Dual/Quad processors */ +static const struct mx6_mmdc_calibration mx6q_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpwldectrl1 = 0x00000000, + .p1_mpwldectrl0 = 0x00000000, + .p1_mpwldectrl1 = 0x00000000, + .p0_mpdgctrl0 = 0x0314031c, + .p0_mpdgctrl1 = 0x023e0304, + .p1_mpdgctrl0 = 0x03240330, + .p1_mpdgctrl1 = 0x03180260, + .p0_mprddlctl = 0x3630323c, + .p1_mprddlctl = 0x3436283a, + .p0_mpwrdlctl = 0x36344038, + .p1_mpwrdlctl = 0x422a423c, +}; + +/* SOM with Solo/Dual Lite processors */ +static const struct mx6_mmdc_calibration mx6dl_mmcd_calib = { + .p0_mpwldectrl0 = 0x0045004D, + .p0_mpwldectrl1 = 0x003A0047, + .p0_mpdgctrl0 = 0x023C0224, + .p0_mpdgctrl1 = 0x02000220, + .p0_mprddlctl = 0x44444846, + .p0_mpwrdlctl = 0x32343032, + .p1_mpwldectrl0 = 0x001F001F, + .p1_mpwldectrl1 = 0x00210035, + .p1_mpdgctrl0 = 0x02200220, + .p1_mpdgctrl1 = 0x02000220, + .p1_mprddlctl = 0x4042463C, + .p1_mpwrdlctl = 0x36363430, +}; + + +/* MT41K256M16HA-125:E */ +static struct mx6_ddr3_cfg mem_ddr_4g = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, + .SRT = 0, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +static void spl_dram_init(int width) +{ + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus: 0=16, 1=32, 2=64 */ + .dsize = width / 32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + .ncs = 1, /* single chip select */ + .cs1_mirror = 0, + .rtt_wr = 1, /* DDR3_RTT_60_OHM RTT_Wr = RZQ/4 */ + .rtt_nom = 1, /* DDR3_RTT_60_OHM RTT_Nom = RZQ/4 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q)) { + mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_4g); + } else { + mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6dl_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6dl_mmcd_calib, &mem_ddr_4g); + } +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* iomux and setup of uart */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ +#ifndef TURING_SMART_VARIANT + if (is_cpu_type(MXC_CPU_MX6Q)) { + printf("Configuring DDR3 for i.MX6 Quad\n"); + spl_dram_init(64); + } else if (is_cpu_type(MXC_CPU_MX6D)) { + printf("Configuring DDR3 for i.MX6 Dual\n"); + spl_dram_init(32); + } else if (is_cpu_type(MXC_CPU_MX6DL)) { + printf("Configuring DDR3 for i.MX6 Dual Lite\n"); + spl_dram_init(32); + } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { + printf("Configuring DDR3 for i.MX6 Solo\n"); + spl_dram_init(16); + } +#else + if (is_cpu_type(MXC_CPU_MX6Q)) { + printf("Configuring DDR3 for i.MX6 Quad Smart\n"); + spl_dram_init(32); + } else if (is_cpu_type(MXC_CPU_MX6D)) { + printf("Configuring DDR3 for i.MX6 Dual\n"); + spl_dram_init(32); + } else if (is_cpu_type(MXC_CPU_MX6DL)) { + printf("Configuring DDR3 for i.MX6 Dual Lite Smart\n"); + spl_dram_init(16); + } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { + printf("Configuring DDR3 for i.MX6 Solo\n"); + spl_dram_init(16); + } +#endif + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif diff --git a/configs/mx6turing_defconfig b/configs/mx6turing_defconfig new file mode 100644 index 0000000..926704e --- /dev/null +++ b/configs/mx6turing_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_MX6TURING=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SPL=y +CONFIG_SPL_EXT_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_OS_BOOT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_SF is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +# CONFIG_CMD_MII is not set +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_SPI_FLASH is not set +# CONFIG_SPI_FLASH_STMICRO is not set +# CONFIG_PCI is not set +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="FSL" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_OF_LIBFDT=y diff --git a/configs/mx6turing_smart_defconfig b/configs/mx6turing_smart_defconfig new file mode 100644 index 0000000..770ef5c --- /dev/null +++ b/configs/mx6turing_smart_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_MX6TURING_SMART=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SPL=y +CONFIG_SPL_EXT_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_OS_BOOT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_SF is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +# CONFIG_CMD_MII is not set +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_SPI_FLASH is not set +# CONFIG_SPI_FLASH_STMICRO is not set +# CONFIG_PCI is not set +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="FSL" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_OF_LIBFDT=y diff --git a/include/configs/mx6turing.h b/include/configs/mx6turing.h new file mode 100644 index 0000000..4fe4de5 --- /dev/null +++ b/include/configs/mx6turing.h @@ -0,0 +1,247 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Turing's mx6 based boards + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6TURING_CONFIG_H +#define __MX6TURING_CONFIG_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> +#include "mx6_common.h" + +#define CONFIG_IMX_THERMAL + +#ifdef CONFIG_SPL +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 +#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K) +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ +#include "imx6_spl.h" +#endif + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) +#define CONFIG_MXC_GPIO +#define CONFIG_MXC_UART +#define CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP + +#define CONFIG_CMD_PCI +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#endif + +#ifdef CONFIG_CMD_SF +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +/* MMC Configs */ +#define CONFIG_FSL_USDHC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define MMCROOT1 "/dev/mmcblk0p2" +#define MMCROOT2 "/dev/mmcblk3p2" +#define CONFIG_MMCROOT MMCROOT1 + +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_RBTREE +#define CONFIG_LZO + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* USB */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL +#define CONFIG_USB_HOST_ETHER +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#define CONFIG_MXC_UART_BASE UART5_BASE +#define CONSOLE_DEV "ttymxc4" + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + "image=zImage\0" \ + "splashpos=m,m\0" \ + "panel=atm0700l6bt\0" \ + "fdtfile=undefined\0" \ + "fdt_addr_r=0x18000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "console=" CONSOLE_DEV "\0" \ + "bootm_size=0x10000000\0" \ + "mmcdev=" __stringify(SYS_MMC_ENV_DEV1) "\0" \ + "mmcpart=1\0" \ + "mmcroot=" MMCROOT1 " rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} no_console_suspend ${bootargs_mem} root=${mmcroot} fbcon=map:<02>\0" \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} no_console_suspend ${bootargs_mem} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp fbcon=map:<02>\0" \ + "netboot=echo Booting from net ...; " \ + "usb start;" \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ + "bootz ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "findfdt=" \ + "if test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-turing-eval.dtb; fi; " \ + "if test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-turing-eval.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine dtb to use; fi; \0" \ + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else " \ + "setenv mmcdev " __stringify(SYS_MMC_ENV_DEV2) "; " \ + "setenv mmcroot " __stringify(MMCROOT2) "; " \ + "mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else " \ + "run netboot; " \ + "fi; " \ + "else " \ + "run netboot; " \ + "fi; " \ + "fi; " \ + "else " \ + "setenv mmcdev " __stringify(SYS_MMC_ENV_DEV2) "; " \ + "setenv mmcroot " __stringify(MMCROOT2) "; " \ + "mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else " \ + "run netboot; " \ + "fi; " \ + "else " \ + "run netboot; " \ + "fi; " \ + "fi;" \ + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define SYS_MMC_ENV_DEV1 0 /* 0: SDHC1; 1:SDHC4 */ +#define SYS_MMC_ENV_DEV2 1 /* 0: SDHC1; 1:SDHC4 */ +#define CONFIG_SYS_MMC_ENV_DEV SYS_MMC_ENV_DEV1 +#define CONFIG_ENV_OFFSET (8 * 64 * 1024) + +/* Framebuffer */ +#define CONFIG_CMD_BMP +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_IMX_VIDEO_SKIP + + +#endif /* __MX6TURING_CONFIG_H */ -- 2.8.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
