ARC cores may have up to 2 built-in timers: timer0 and timer1,
usually at least one of them exists. They both are driven by the
same core clock.
They are controlled through auxiliary registers and so we
don't have to remap their control registers as we used to do
with MMIO registers of external
This commit introduces timer driver for ARC.
ARC timers are configured via ARC AUX registers so we use special
functions to access timer control registers.
This driver allows utilization of either timer0 or timer1
depending on which one is available in real hardware. Essentially
only existing tim
We want to use the same device tree blobs in both Linux and U-Boot for
ARC boards.
Earlier device tree sources in U-Boot were very simplified and hadn't been
updated for quite a long period of time.
So this commit is the first step on the road to unified device tree blobs.
First of all we re-org
This commit replaces legacy timer code with usage of arc timer
driver.
It removes arch/arc/lib/time.c file and selects CONFIG_CLK,
CONFIG_TIMER and CONFIG_ARC_TIMER options for all ARC boards by default.
Therefore we remove CONFIG_CLK option from less common axs101 and
axs103 defconfigs.
Also it
On 07/02/17 05:13, Lokesh Vutla wrote:
>
>
> On 2/6/2017 3:06 PM, Roger Quadros wrote:
>> In stead of defining the board EEPROM address in the board headers
>> let's define them in the board config files and make them
>> configurable by Kconfig.
>>
>> Signed-off-by: Roger Quadros
>> ---
>> boar
On 07/02/17 05:22, Lokesh Vutla wrote:
>
>
> On 2/6/2017 3:06 PM, Roger Quadros wrote:
>> PRU ethernet MAC address range is present in the
>> board EEPROM. Parse it and setup eth?addr
>> environment variables.
>>
>> Signed-off-by: Roger Quadros
>> Reviewed-by: Lokesh Vutla
>> ---
>> board/ti
Hi Stefano,
On Tue, Dec 27, 2016 at 06:04:06PM +0800, Peng Fan wrote:
>This patchset is to add i.MX7 ULP support default enabling OF_CONTROL.
>Also there are some new IPs, such lpi2c/lpuart/rapid gpio2p and etc.
Do you have plan to pick this patchset? or any comments?
We plan to choose 2017.03
Hi Igor,
On 07/02/17 09:52, Igor Grinberg wrote:
> Hi Roger,
>
> On 02/06/17 11:36, Roger Quadros wrote:
>> PRU ethernet MAC address range is present in the
>> board EEPROM. Parse it and setup eth?addr
>> environment variables.
>>
>> Signed-off-by: Roger Quadros
>> Reviewed-by: Lokesh Vutla
>>
On Wednesday 08 February 2017 04:29 AM, Andrew F. Davis wrote:
> FIT support in the net boot case is much like the RAM boot case in that
> we load our image to "load_addr" and pass a dummy read function into
> "spl_load_simple_fit()". As the load address is no longer hard-coded to
> the final exe
Hi Roger,
On 02/08/17 10:51, Roger Quadros wrote:
> Hi Igor,
>
> On 07/02/17 09:52, Igor Grinberg wrote:
>> Hi Roger,
>>
>> On 02/06/17 11:36, Roger Quadros wrote:
>>> PRU ethernet MAC address range is present in the
>>> board EEPROM. Parse it and setup eth?addr
>>> environment variables.
>>>
>>>
Hi Tom,
On 02/07/17 20:28, Tom Rini wrote:
> On Tue, Feb 07, 2017 at 09:52:25AM +0200, Igor Grinberg wrote:
>> Hi Roger,
>>
>> On 02/06/17 11:36, Roger Quadros wrote:
>>> PRU ethernet MAC address range is present in the
>>> board EEPROM. Parse it and setup eth?addr
>>> environment variables.
>>>
>
Hi,
On 08/02/17 13:51, Igor Grinberg wrote:
> Hi Roger,
>
> On 02/08/17 10:51, Roger Quadros wrote:
>> Hi Igor,
>>
>> On 07/02/17 09:52, Igor Grinberg wrote:
>>> Hi Roger,
>>>
>>> On 02/06/17 11:36, Roger Quadros wrote:
PRU ethernet MAC address range is present in the
board EEPROM. Pars
Hi Peng,
On 08/02/2017 09:36, Peng Fan wrote:
>
> Hi Stefano,
>
> On Tue, Dec 27, 2016 at 06:04:06PM +0800, Peng Fan wrote:
>> This patchset is to add i.MX7 ULP support default enabling OF_CONTROL.
>> Also there are some new IPs, such lpi2c/lpuart/rapid gpio2p and etc.
>
> Do you have plan to p
On Wed, Feb 08, 2017 at 02:04:15PM +0200, Roger Quadros wrote:
> Hi,
>
> On 08/02/17 13:51, Igor Grinberg wrote:
> > Hi Roger,
> >
> > On 02/08/17 10:51, Roger Quadros wrote:
> >> Hi Igor,
> >>
> >> On 07/02/17 09:52, Igor Grinberg wrote:
> >>> Hi Roger,
> >>>
> >>> On 02/06/17 11:36, Roger Quadr
- Enable SPL_DM on all DRA7 and AM57xx based platforms.
- SPL uses a generic dts on all platforms with same defconfig.
- After this series SPL size is increased by ~7KB.
Verified MMC, eMMC boot on DRA74-evm, DRA72-evm.
MMC boot on AM57xx-evm.
Lokesh Vutla (6):
tools: omapimage: Fix size in head
Add a generic dts file for spl that is used by all
AM57xx based platforms.
Signed-off-by: Lokesh Vutla
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/am57xx-generic-spl.dts | 24
configs/am57xx_evm_defconfig| 2 +-
configs/am57xx_hs_evm_defconfig
Add a generic dts file for spl that is used by all
DRA7 based platforms.
Signed-off-by: Lokesh Vutla
---
arch/arm/dts/Makefile | 2 +-
arch/arm/dts/dra7-generic-spl.dts | 50 +++
configs/dra7xx_evm_defconfig | 2 +-
configs/dra7xx_hs_evm_def
Enable SPL_DM on all DRA7 based platforms.
Signed-off-by: Lokesh Vutla
---
configs/dra7xx_evm_defconfig | 5 -
configs/dra7xx_hs_evm_defconfig | 5 -
include/configs/dra7xx_evm.h | 5 -
include/configs/ti_omap5_common.h | 8 +---
4 files changed, 9 insertions(+), 14 d
Enable SPL_DM on all AM57xx based platforms.
Signed-off-by: Lokesh Vutla
---
configs/am57xx_evm_defconfig| 5 -
configs/am57xx_hs_evm_defconfig | 5 -
include/configs/am57xx_evm.h| 5 -
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/configs/am57xx_evm_defconfi
The size field in GP header that is expected by ROM is size of the
image + size of the header. But omapimage generates a gp header
only with size of the image as size field. Fix it
Signed-off-by: Lokesh Vutla
---
tools/gpimage.c | 2 +-
tools/omapimage.c | 2 +-
2 files changed, 2 insertions(+
To make SPL_OF_CONTROL work on OAP2+ SoCs, _image_binary_end must be
defined in the linker script along with CONFIG_SPL_SEPARATE_BSS.
Signed-off-by: Lokesh Vutla
---
arch/arm/mach-omap2/u-boot-spl.lds | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-omap2/u-boot-spl.lds
b/arc
We don't ever search for these so there is no need for a 4KB alignment.
It just wastes space.
Drop this and use the standard 4-byte alignment.
Signed-off-by: Simon Glass
---
board/samsung/common/exynos-uboot-spl.lds | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/board/sa
On 08/02/17 14:18, Tom Rini wrote:
> On Wed, Feb 08, 2017 at 02:04:15PM +0200, Roger Quadros wrote:
>> Hi,
>>
>> On 08/02/17 13:51, Igor Grinberg wrote:
>>> Hi Roger,
>>>
>>> On 02/08/17 10:51, Roger Quadros wrote:
Hi Igor,
On 07/02/17 09:52, Igor Grinberg wrote:
> Hi Roger,
On Wed, Feb 08, 2017 at 02:46:20PM +0200, Roger Quadros wrote:
> On 08/02/17 14:18, Tom Rini wrote:
> > On Wed, Feb 08, 2017 at 02:04:15PM +0200, Roger Quadros wrote:
> >> Hi,
> >>
> >> On 08/02/17 13:51, Igor Grinberg wrote:
> >>> Hi Roger,
> >>>
> >>> On 02/08/17 10:51, Roger Quadros wrote:
> >>>
On Wed, Feb 08, 2017 at 06:03:31PM +0530, Lokesh Vutla wrote:
> - Enable SPL_DM on all DRA7 and AM57xx based platforms.
> - SPL uses a generic dts on all platforms with same defconfig.
> - After this series SPL size is increased by ~7KB.
That's not a bad size growth, esp here where we can afford
On 12 January 2017 at 10:47, Moritz Fischer wrote:
>
> Replace dm_i2c_write() / dm_i2c_read() with transaction using
> struct i2c_msg[2] in order to allow for i2c controller to detect
> write/read cycle to emit a repeated start condition.
>
> Signed-off-by: Moritz Fischer
> Cc: Simon Glass
> Cc:
On 12 January 2017 at 14:59, Moritz Fischer wrote:
> Add support for version 3 of the ec protocol. It basically works by
> stitching some additional header in front (special command code),
> and having a result and packet_length stitched on for the reply.
>
> Signed-off-by: Moritz Fischer
> Cc: S
On 7 February 2017 at 00:11, Chris Packham wrote:
> When gathering addresses for the Cc list patman would encounter a
> UnicodeDecodeError due to non-ascii characters in the author name.
> Address this by explicitly using utf-8 when building the Cc list.
>
> Signed-off-by: Chris Packham
> ---
> O
On 20 January 2017 at 13:35, Moritz Fischer wrote:
> Add support for version 3 of the ec protocol. It basically works by
> stitching some additional header in front (special command code),
> and having a result and packet_length stitched on for the reply.
>
> Signed-off-by: Moritz Fischer
> Cc: S
On 8 February 2017 at 06:02, Simon Glass wrote:
> On 12 January 2017 at 14:59, Moritz Fischer wrote:
>> Add support for version 3 of the ec protocol. It basically works by
>> stitching some additional header in front (special command code),
>> and having a result and packet_length stitched on for
On Wednesday 08 February 2017 06:26 PM, Tom Rini wrote:
> On Wed, Feb 08, 2017 at 06:03:31PM +0530, Lokesh Vutla wrote:
>
>> - Enable SPL_DM on all DRA7 and AM57xx based platforms.
>> - SPL uses a generic dts on all platforms with same defconfig.
>> - After this series SPL size is increased by ~
As per the latest pinmux data available for AM572x EVM,
rev A3, input should be enabled on MMC clock lines for
MMC2/2/3 for stable operation.
Further, AM572x TRM, SPRUHZ6, Revised June 2016, in
section 18.4.6.1.1 "Pad Configuration Registers" states
that input should be enabled for MMC 2/3/4 clock
On Wed, Feb 08, 2017 at 06:37:17PM +0530, Lokesh Vutla wrote:
>
>
> On Wednesday 08 February 2017 06:26 PM, Tom Rini wrote:
> > On Wed, Feb 08, 2017 at 06:03:31PM +0530, Lokesh Vutla wrote:
> >
> >> - Enable SPL_DM on all DRA7 and AM57xx based platforms.
> >> - SPL uses a generic dts on all plat
On Wednesday 08 February 2017 06:45 PM, Tom Rini wrote:
> On Wed, Feb 08, 2017 at 06:37:17PM +0530, Lokesh Vutla wrote:
>>
>>
>> On Wednesday 08 February 2017 06:26 PM, Tom Rini wrote:
>>> On Wed, Feb 08, 2017 at 06:03:31PM +0530, Lokesh Vutla wrote:
>>>
- Enable SPL_DM on all DRA7 and AM57x
On Wed, Feb 08, 2017 at 06:58:10PM +0530, Lokesh Vutla wrote:
>
>
> On Wednesday 08 February 2017 06:45 PM, Tom Rini wrote:
> > On Wed, Feb 08, 2017 at 06:37:17PM +0530, Lokesh Vutla wrote:
> >>
> >>
> >> On Wednesday 08 February 2017 06:26 PM, Tom Rini wrote:
> >>> On Wed, Feb 08, 2017 at 06:03:
On Wednesday 08 February 2017 06:43 PM, Sekhar Nori wrote:
> As per the latest pinmux data available for AM572x EVM,
> rev A3, input should be enabled on MMC clock lines for
> MMC2/2/3 for stable operation.
>
> Further, AM572x TRM, SPRUHZ6, Revised June 2016, in
> section 18.4.6.1.1 "Pad Configu
On Wed, Feb 08, 2017 at 06:03:34PM +0530, Lokesh Vutla wrote:
> Add a generic dts file for spl that is used by all
> AM57xx based platforms.
>
> Signed-off-by: Lokesh Vutla
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/am57xx-generic-spl.dts | 24
>
On Wed, Feb 08, 2017 at 06:03:33PM +0530, Lokesh Vutla wrote:
> To make SPL_OF_CONTROL work on OAP2+ SoCs, _image_binary_end must be
> defined in the linker script along with CONFIG_SPL_SEPARATE_BSS.
>
> Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
--
Tom
signature.asc
Description: Di
On Wed, Feb 08, 2017 at 06:03:32PM +0530, Lokesh Vutla wrote:
> The size field in GP header that is expected by ROM is size of the
> image + size of the header. But omapimage generates a gp header
> only with size of the image as size field. Fix it
>
> Signed-off-by: Lokesh Vutla
Reviewed-by: T
On Wednesday 08 February 2017 04:29 AM, Andrew F. Davis wrote:
> FIT support in the net boot case is much like the RAM boot case in that
> we load our image to "load_addr" and pass a dummy read function into
> "spl_load_simple_fit()". As the load address is no longer hard-coded to
> the final exe
Hello Masahiro,
This is my understanding of the parameters 'dev' and 'perihp' passed to
the function implementing set_state_simple().
On 08.02.2017 04:02, Masahiro Yamada wrote:
> Hi.
>
>
>
> 2017-02-07 22:30 GMT+09:00 Felix Brack :
>
>> +
>> +static int single_set_state_simple(struct udevice
On Tue, Jan 31, 2017 at 12:17:06PM +0100, Emmanuel Vadot wrote:
> From: Warner Losh
>
> Some application might load some code at location that contain stale
> cache entries. Before running a elf or raw binary, flush the caches
> if they are enabled.
>
> Reviewed-by: Tom Rini
> Signed-off-by: E
On 02/08/2017 04:00 PM, Tom Rini wrote:
On Tue, Jan 31, 2017 at 12:17:06PM +0100, Emmanuel Vadot wrote:
From: Warner Losh
Some application might load some code at location that contain stale
cache entries. Before running a elf or raw binary, flush the caches
if they are enabled.
Reviewed-by:
On 12/06/2016 09:47 PM, Simon Glass wrote:
> Hi Andrew,
>
> On 5 December 2016 at 17:37, Andrew F. Davis wrote:
>> On 11/14/2016 06:33 PM, Simon Glass wrote:
>>> Hi Andrew,
>>>
>>> On 14 November 2016 at 15:05, Andrew F. Davis wrote:
On 11/14/2016 02:44 PM, Simon Glass wrote:
> Hi Andre
Hi.
>> 2017-02-07 22:30 GMT+09:00 Felix Brack :
>>
>>> +
>>> +static int single_set_state_simple(struct udevice *dev,
>>> + struct udevice *periph)
>>> +{
>>> + const void *fdt = gd->fdt_blob;
>>> + const struct single_fdt_pin_cfg *prop;
>>> + in
From: Konstantin Porotchkin
This patch series adds initil support for A8K community board MACCHIATOBin
manufactured by SolidRun.
It should be applied on top of Stefan Roese patches adding support for SD/eMMC
devices on Marvell A37x0/A80x0/A70x0 SoCs.
The top level patch is called:
"arm64: mvebu
From: Konstantin Porotchkin
Add GPIO nodes to AP-806 and CP-110-master DTSI files.
Change-Id: I05958698d460cb721b7d8683d34f74a5ea32532c
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Nadav Haklai
Cc: Igal Liberman
Cc: Haim Boot
---
Changes for v3:
- Rebase on top of master branch
From: Konstantin Porotchkin
The USB device should linked to VBUS regulator through "vbus-supply"
DTS property.
This patch adds handling for "vbus-supply" property inside the USB
device entry for turning on the VBUS regulator upon the host adapter probe.
Change-Id: Ibcf72d82298be42353ca03fee064ae
From: Konstantin Porotchkin
Add support for "marvell,reset-gpio" property to mvebu DW PCIe
driver.
This option is valid when CONFIG_DM_GPIO=y
Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986
Signed-off-by: Konstantin Porotchkin
Signed-off-by: Rabeeh Khoury
Cc: Stefan Roese
Cc: Nadav Hakla
From: Konstantin Porotchkin
Add i2c-1 pin mappings to CP0(master) DTSI file
Change-Id: I0c6e6de8a557393f518f7df8e6daa6dfce1788b0
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Nadav Haklai
Cc: Neta Zur Hershkovits
Cc: Igal Liberman
Cc: Haim Boot
---
Changes for v3:
- Rebase on t
From: Konstantin Porotchkin
Add default configuration for MACHHIATOBin community board
based on Aramda-8040 SoC.
This config has MMC support removed, pending mainline support.
Change-Id: Ic6b562065c0929ec338492452f765115c15a6188
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Nadav H
From: Rabeeh Khoury
Added A8040 dts file for community board MACCHIATIBin.
The patch includes the following features:
AP - Serial console (connected to onboard FTDI usb to serial)
CP0 - PCIe x4, SATA, I2C and 10G KR
(connected to Marvell 3310 10G copper / SFP+ phy)
CP1 - Boot SPI, USB3 hos
On 02/08/2017 04:34 PM, kos...@marvell.com wrote:
> From: Konstantin Porotchkin
>
> The USB device should linked to VBUS regulator through "vbus-supply"
> DTS property.
> This patch adds handling for "vbus-supply" property inside the USB
> device entry for turning on the VBUS regulator upon the h
Hi, Marek,
On 02/08/2017 05:35 PM, Marek Vasut wrote:
On 02/08/2017 04:34 PM, kos...@marvell.com wrote:
> From: Konstantin Porotchkin
>
> The USB device should linked to VBUS regulator through "vbus-supply"
> DTS property.
> This patch adds handling for "vbus-supply" property inside the USB
> d
On 02/08/2017 04:45 PM, Konstantin Porotchkin wrote:
> Hi, Marek,
>
> On 02/08/2017 05:35 PM, Marek Vasut wrote:
>> On 02/08/2017 04:34 PM, kos...@marvell.com wrote:
>> > From: Konstantin Porotchkin
>> >
>> > The USB device should linked to VBUS regulator through "vbus-supply"
>> > DTS property.
Hi, Marek,
On 02/08/2017 06:04 PM, Marek Vasut wrote:
On 02/08/2017 04:45 PM, Konstantin Porotchkin wrote:
Hi, Marek,
On 02/08/2017 05:35 PM, Marek Vasut wrote:
On 02/08/2017 04:34 PM, kos...@marvell.com wrote:
From: Konstantin Porotchkin
The USB device should linked to VBUS regulator thro
On Wed, Feb 08, 2017 at 06:03:33PM +0530, Lokesh Vutla wrote:
> To make SPL_OF_CONTROL work on OAP2+ SoCs, _image_binary_end must be
OMAP2+ ---> ^
Just a nitpick, but helps grepping for changes in git log.
Thank you,
ladis
> defined in the linker script along wit
On 02/08/2017 04:07 AM, Vignesh R wrote:
>
>
> On Wednesday 08 February 2017 04:29 AM, Andrew F. Davis wrote:
>> FIT support in the net boot case is much like the RAM boot case in that
>> we load our image to "load_addr" and pass a dummy read function into
>> "spl_load_simple_fit()". As the load
On 02/08/2017 08:05 AM, Lokesh Vutla wrote:
>
>
> On Wednesday 08 February 2017 04:29 AM, Andrew F. Davis wrote:
>> FIT support in the net boot case is much like the RAM boot case in that
>> we load our image to "load_addr" and pass a dummy read function into
>> "spl_load_simple_fit()". As the lo
On 02/08/2017 05:28 PM, Konstantin Porotchkin wrote:
> Hi, Marek,
>
> On 02/08/2017 06:04 PM, Marek Vasut wrote:
>> On 02/08/2017 04:45 PM, Konstantin Porotchkin wrote:
>>> Hi, Marek,
>>>
>>> On 02/08/2017 05:35 PM, Marek Vasut wrote:
On 02/08/2017 04:34 PM, kos...@marvell.com wrote:
> Fr
Hi Bin,
On 04.02.2017 06:57, Bin Meng wrote:
On Mon, Jan 23, 2017 at 10:55 PM, Stefan Roese wrote:
Without configuring these registers in the SPI controller, the Linux
MTD device driver is not able to correctly read/write to the SPI
NOR chip at all. In fact, the chip is not detected at all.
S
Hello all,
To address a needed feature brought up by Andreas[0], we need a way to
disable SPL from loading non-FIT images.
The function spl_parse_image_header is common to all SPL loading paths
(common/spl/spl_(nand|net|nor|etc..)) so we add the check here.
This version of the series is a bit di
CONFIG_SPL_ABORT_ON_RAW_IMAGE causes SPL to abort and move on when it
encounters RAW images, express this same functionality as a positive
option enabling support for RAW images: CONFIG_SPL_RAW_IMAGE_SUPPORT
Signed-off-by: Andrew F. Davis
---
Kconfig | 7 +++
README
Disable support for loading non-FIT images for AM57xx platforms using
the high-security (HS) device variant.
Signed-off-by: Andrew F. Davis
---
configs/am57xx_hs_evm_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
Disable support for loading non-FIT images for DRA7xx platforms using
the high-security (HS) device variant.
Signed-off-by: Andrew F. Davis
---
configs/dra7xx_hs_evm_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
Add a Kconfig option that enables Legacy image support, this allows
boards to explicitly disable this, for instance when needed for
security reasons.
Signed-off-by: Andrew F. Davis
---
Kconfig | 8
common/spl/spl.c | 9 +++--
2 files changed, 15 insertions(+), 2 deletions(-
Disable support for loading non-FIT images for AM43xx platforms using
the high-security (HS) device variant.
Signed-off-by: Andrew F. Davis
---
configs/am43xx_hs_evm_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
On 02/07/2017 10:48 PM, Udit Agarwal wrote:
> For validating images from uboot (Such as Kernel Image), either keys
> from SoC fuses can be used or keys from a verified table of public keys
> can be used. The latter feature is called IE Key Extension Feature.
>
> On ls-ch3 platforms,IE table is vali
Disable support for loading non-FIT images for AM335x platforms using
the high-security (HS) device variant.
Signed-off-by: Andrew F. Davis
---
configs/am335x_hs_evm_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
On 9 January 2017 at 03:17, Ladislav Michl wrote:
> fdt_fixup_mtdparts currently does nothing when partitin info is
> runtime generated or compiled-in defaults are used.
>
> Signed-off-by: Ladislav Michl
> ---
> common/fdt_support.c | 5 -
> 1 file changed, 5 deletions(-)
Fixed commit messa
On 15 January 2017 at 21:09, Simon Glass wrote:
> If there is a '.' in a compatible string, then dtoc will produce a struct
> with a name containing a '.'. This won't work, so replace it with '_'.
>
> Also add a suitable test to the sandbox device tree to catch this.
>
> Signed-off-by: Simon Glass
On 8 February 2017 at 06:02, Simon Glass wrote:
> On 12 January 2017 at 10:47, Moritz Fischer wrote:
>>
>> Replace dm_i2c_write() / dm_i2c_read() with transaction using
>> struct i2c_msg[2] in order to allow for i2c controller to detect
>> write/read cycle to emit a repeated start condition.
>>
>
On 17 January 2017 at 16:52, Simon Glass wrote:
> At present devices use a simple integer offset to record the device tree
> node associated with the device. In preparation for supporting a live
> device tree, which uses a node pointer instead, refactor existing code to
> access this field through
On 17 January 2017 at 16:52, Simon Glass wrote:
> It is convenient to be able to deal with checkpatch warnings in the same
> way as build warnings. Tools such as emacs and kate can quickly locate
> the source file and line automatically.
>
> To achieve this, adjust the format to match the C compil
On 23 January 2017 at 05:38, Simon Glass wrote:
> As well as showing the number of boards, allow showing the actual list of
> boards that would be built, if -v is provided.
>
> Signed-off-by: Simon Glass
> ---
>
> tools/buildman/README | 2 +-
> tools/buildman/board.py | 10 +-
>
On 8 February 2017 at 06:04, Simon Glass wrote:
> On 20 January 2017 at 13:35, Moritz Fischer wrote:
>> Add support for version 3 of the ec protocol. It basically works by
>> stitching some additional header in front (special command code),
>> and having a result and packet_length stitched on for
On 7 February 2017 at 22:09, Simon Glass wrote:
> Hi Kever,
>
> On 4 February 2017 at 17:24, Kever Yang wrote:
>>
>> Hi Simon,
>>
>> Found 1 typo on the subject, 'suport' should be 'support',
>> do I need to send a new patch or you can correct it when you apply?
>
> I can correct it when I ap
On 8 February 2017 at 06:03, Simon Glass wrote:
> On 7 February 2017 at 00:11, Chris Packham wrote:
>> When gathering addresses for the Cc list patman would encounter a
>> UnicodeDecodeError due to non-ascii characters in the author name.
>> Address this by explicitly using utf-8 when building th
Hi Tom,
This includes a few more DM and patman/buildman patches and some
cros_ec additions. The change to of_offset is best applied now that
rc1 is out, since I should have picked up all the usages.
The following changes since commit 446d4e048ee3b00f7907e15cd02aa404cc714c77:
x86: make LOAD_FR
FIT support in the net boot case is much like the RAM boot case in that
we load our image to "load_addr" and pass a dummy read function into
"spl_load_simple_fit()". As the load address is no longer hard-coded to
the final execution address, RAW image loading will rely on "load_addr"
pointing to th
On 02/07/2017 07:32 PM, Marek Vasut wrote:
> On 02/08/2017 02:21 AM, Marek Vasut wrote:
>> On 01/31/2017 07:33 PM, Dinh Nguyen wrote:
>>> The mpuclk register in the Altera group of the clock manager
>>> divides the mpu_clk that is generated from the C0 output of the main
>>> pll.
>>>
>>> Without
On 02/08/2017 07:07 AM, Lokesh Vutla wrote:
>
>
> On Wednesday 08 February 2017 06:26 PM, Tom Rini wrote:
>> On Wed, Feb 08, 2017 at 06:03:31PM +0530, Lokesh Vutla wrote:
>>
>>> - Enable SPL_DM on all DRA7 and AM57xx based platforms.
>>> - SPL uses a generic dts on all platforms with same defconf
On Wed, Feb 8, 2017 at 12:26 AM, Sekhar Nori wrote:
> On Wednesday 08 February 2017 12:36 AM, Yung-Ching LIN wrote:
>> On Tue, Feb 7, 2017 at 12:50 AM, Sekhar Nori wrote:
>>> On Monday 06 February 2017 11:06 PM, Ken.Lin wrote:
>>>
>> The register setting would turn out to be 0x3D47 on our pro
On 02/07/2017 09:08 PM, Priyanka Jain wrote:
>
>
> We have verified VID support on LS2080AQDS, LS2080ARDB, LS2088AQDS,
> LS2080ARDB (all SoCs in upstream for which LSCH3 flag is applicable)
>
>
Great! Thanks.
York
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The non-HS defconfig has been modified without equivalent changes being
applied to the HS defconfig. Sync these here.
Signed-off-by: Andrew F. Davis
---
configs/am43xx_hs_evm_defconfig | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/configs/am43xx_hs_evm_defconf
On Wed, Feb 08, 2017 at 12:42:33PM -0600, Andrew F. Davis wrote:
> On 02/08/2017 07:07 AM, Lokesh Vutla wrote:
> >
> >
> > On Wednesday 08 February 2017 06:26 PM, Tom Rini wrote:
> >> On Wed, Feb 08, 2017 at 06:03:31PM +0530, Lokesh Vutla wrote:
> >>
> >>> - Enable SPL_DM on all DRA7 and AM57xx b
On 02/08/2017 02:40 PM, Tom Rini wrote:
> On Wed, Feb 08, 2017 at 12:42:33PM -0600, Andrew F. Davis wrote:
>> On 02/08/2017 07:07 AM, Lokesh Vutla wrote:
>>>
>>>
>>> On Wednesday 08 February 2017 06:26 PM, Tom Rini wrote:
On Wed, Feb 08, 2017 at 06:03:31PM +0530, Lokesh Vutla wrote:
>
On Wed, Feb 08, 2017 at 02:46:22PM -0600, Andrew F. Davis wrote:
> On 02/08/2017 02:40 PM, Tom Rini wrote:
> > On Wed, Feb 08, 2017 at 12:42:33PM -0600, Andrew F. Davis wrote:
> >> On 02/08/2017 07:07 AM, Lokesh Vutla wrote:
> >>>
> >>>
> >>> On Wednesday 08 February 2017 06:26 PM, Tom Rini wrote:
On 02/08/2017 06:59 PM, Dinh Nguyen wrote:
>
>
> On 02/07/2017 07:32 PM, Marek Vasut wrote:
>> On 02/08/2017 02:21 AM, Marek Vasut wrote:
>>> On 01/31/2017 07:33 PM, Dinh Nguyen wrote:
The mpuclk register in the Altera group of the clock manager
divides the mpu_clk that is generated fro
On Tue, Jan 31, 2017 at 03:37:04PM -0600, Grygorii Strashko wrote:
> From: Mugunthan V N
>
> nand_info is used all over the file so abstract it with
> get_nand_dev_by_index() which will help for DM conversion.
>
> Signed-off-by: Mugunthan V N
> Signed-off-by: Grygorii Strashko
> Reviewed-by:
Hi York,
On 8 February 2017 at 14:58, york sun wrote:
> Simon,
>
> I stumped on this issue when I was rewriting the code to reserve secure
> memory. I didn't realize gd->ram_size was used in the driver. I made the
> top of memory secure so EL2 code wouldn't be able to access. All of the
> sudden
Simon,
I stumped on this issue when I was rewriting the code to reserve secure
memory. I didn't realize gd->ram_size was used in the driver. I made the
top of memory secure so EL2 code wouldn't be able to access. All of the
sudden my PCI device failed. By reducing the gd->ram_size, PCI works ag
On Tue, Feb 7, 2017 at 11:52 AM, Tom Rini wrote:
> On Mon, Feb 06, 2017 at 07:17:35PM -0800, Alexandru Gagniuc wrote:
>
>> From: "Andrew F. Davis"
>>
>> Signed-off-by: Andrew F. Davis
> [snip]
>> 756 files changed, 860 insertions(+), 579 deletions(-)
>
> So this shows we have some places where
On 02/08/2017 03:04 PM, Marek Vasut wrote:
> On 02/08/2017 06:59 PM, Dinh Nguyen wrote:
>>
>>
>> On 02/07/2017 07:32 PM, Marek Vasut wrote:
>>> On 02/08/2017 02:21 AM, Marek Vasut wrote:
On 01/31/2017 07:33 PM, Dinh Nguyen wrote:
> The mpuclk register in the Altera group of the clock man
On 02/08/2017 02:12 PM, Simon Glass wrote:
> Hi York,
>
> On 8 February 2017 at 14:58, york sun wrote:
>> Simon,
>>
>> I stumped on this issue when I was rewriting the code to reserve secure
>> memory. I didn't realize gd->ram_size was used in the driver. I made the
>> top of memory secure so EL2
On 02/08/2017 03:08 PM, Peter Newton wrote:
>> From: york sun
>>
>> It was for backward compatibility. Even I have pointed out numerous times
>> (internally) that cp.b should not be used for this case, and
>> even pointed out how to make a FIT image with load address, the board
>> maintainer(s)
On 02/08/2017 11:51 PM, Dinh Nguyen wrote:
>
>
> On 02/08/2017 03:04 PM, Marek Vasut wrote:
>> On 02/08/2017 06:59 PM, Dinh Nguyen wrote:
>>>
>>>
>>> On 02/07/2017 07:32 PM, Marek Vasut wrote:
On 02/08/2017 02:21 AM, Marek Vasut wrote:
> On 01/31/2017 07:33 PM, Dinh Nguyen wrote:
>>
Hi,
SoCFPGA PR for 2017.03 , I checked with Dinh and it should be OK.
The following changes since commit c83a824e62277162ad35f52879b2316902c0eff5:
Merge git://git.denx.de/u-boot-fsl-qoriq (2017-02-03 20:33:42 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-socfpga.g
On Fri, 2017-02-03 at 10:36 -0800, Dalon Westergreen wrote:
> From: Dalon Westergreen
>
> This adds support for the spl to seach for and boot from an arbitrary
> partition type rather then a specific partition number. When
> USE_PARTITION_TYPE is enabled, splwill search for the partition type b
On Fri, Jan 27, 2017 at 04:15:29PM +0900, Masahiro Yamada wrote:
> AArch64 has a zero register (xzr). Use it instead of x2.
>
> Signed-off-by: Masahiro Yamada
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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