On the raspberry pi, you can disable the serial port to gain dynamic frequency
scaling which can get handy at times.
However, in such a configuration the serial controller gets its rx queue filled
up with zero bytes which then happily get transmitted on to whoever calls
getc() today.
This patch a
Hi Tom,
On 2016年08月02日 08:39, Tom Rini wrote:
On Tue, Aug 02, 2016 at 08:37:19AM +0800, Ziyuan Xu wrote:
Hi Tom,
On 2016年08月02日 06:54, Tom Rini wrote:
As part of testing booting Linux kernels on Rockchip devices, it was
discovered by Ziyuan Xu and Sandy Patterson that we had multiple and fo
On Wed, 3 Aug 2016 19:16:57 -0600
Simon Glass wrote:
> Hi,
>
> On 3 August 2016 at 09:37, Stephen Warren wrote:
> > On 08/03/2016 03:35 AM, Alban Bedel wrote:
> >>
> >> For simplicity and backward compatibility automatically run 'pci enum'
> >> via preboot when PCI is enabled. As preboot is alr
On Wed, 3 Aug 2016 15:23:30 +
Marcel Ziswiler wrote:
> On Wed, 2016-08-03 at 15:51 +0200, Marek Vasut wrote:
> > On 08/03/2016 11:46 AM, Alban Bedel wrote:
> > >
> > > On Wed, 3 Aug 2016 09:00:42 +0200
> > > Marek Vasut wrote:
> > >
> > > >
> > > > On 08/03/2016 07:32 AM, Alban Bedel wrot
On 08/04/2016 11:07 AM, Alban Bedel wrote:
> On Wed, 3 Aug 2016 15:23:30 +
> Marcel Ziswiler wrote:
>
>> On Wed, 2016-08-03 at 15:51 +0200, Marek Vasut wrote:
>>> On 08/03/2016 11:46 AM, Alban Bedel wrote:
On Wed, 3 Aug 2016 09:00:42 +0200
Marek Vasut wrote:
>
> O
Enables dwc3 gadget driver support on LS1043QDS platform.
Signed-off-by: Rajat Srivastava
Signed-off-by: Rajesh Bhagat
Reviewed-by: Lukasz Majewski
---
Changes in v3:
- None
Changes in v2:
- None
include/configs/ls1043aqds.h | 15 +++
1 file changed, 15 insertions(+)
diff --gi
Adds helper functions to enable snooping and outstanding burst beat
settings.
Signed-off-by: Rajat Srivastava
Signed-off-by: Rajesh Bhagat
---
Changes in v3:
- Changed operator for code cleanup
Changes in v2:
- Removes SoC specific flags and added helper functions
drivers/usb/dwc3/core.c |
Implements the dwc3 gadget driver support for LS1043
platform, and performs below operations:
1. Enables snooping support for DWC3 controller.
2. Enables cache coherency in LS1043 platform.
Signed-off-by: Rajat Srivastava
Signed-off-by: Rajesh Bhagat
Reviewed-by: Lukasz Majewski
---
Changes in
From: Rajesh Bhagat
Adds a new field in fsg_common namely controller_index to support
multiple controllers usb gadget support.
Signed-off-by: Rajat Srivastava
Signed-off-by: Rajesh Bhagat
Acked-by: Lukasz Majewski
---
Changes in v3
- None
Changes for v2:
- Changes type of fsg_main_thread a
On 08/04/2016 11:26 AM, Rajat Srivastava wrote:
> Adds helper functions to enable snooping and outstanding burst beat
> settings.
>
> Signed-off-by: Rajat Srivastava
> Signed-off-by: Rajesh Bhagat
> ---
> Changes in v3:
> - Changed operator for code cleanup
>
> Changes in v2:
> - Removes SoC
On 1.8.2016 12:06, Paul Burton wrote:
> Previously ns16550 compatible UARTs probed via device tree have needed
> their device tree nodes to contain a clock-frequency property. An
> alternative to this commonly used with Linux is to reference a clock via
> a phandle. This patch allows U-Boot to supp
On 1.8.2016 12:06, Paul Burton wrote:
> This patch adds a driver for the Xilinx AXI bridge for PCI express, an
> IP block which can be used on some generations of Xilinx FPGAs. This is
> mostly a case of implementing PCIe ECAM specification, but with some
> quirks about what devices are valid to ac
On 04/08/16 10:50, Michal Simek wrote:
@@ -352,6 +353,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
{
struct ns16550_platdata *plat = dev->platdata;
fdt_addr_t addr;
+ struct clk clk;
+ int err;
/* try Processor Local Bus device first */
From: Rajesh Bhagat
Adds support for dwc3 gadget driver for ARM v8 platform of layerscape
series. Currently this patch has been tested for LS1043A
Rajat Srivastava (3):
usb: dwc3: Add helper functions to enable snooping and burst settings
armv8/fsl-layerscape: add dwc3 gadget driver support
On 1.8.2016 14:51, Paul Burton wrote:
> On 01/08/16 13:41, Michal Simek wrote:
>> On 1.8.2016 14:09, Paul Burton wrote:
>>> On 01/08/16 11:46, Michal Simek wrote:
On 1.8.2016 12:06, Paul Burton wrote:
> This series introduces initial support for the MIPS Boston, and FPGA
> based develo
On 4.8.2016 11:59, Paul Burton wrote:
> On 04/08/16 10:50, Michal Simek wrote:
>>> @@ -352,6 +353,8 @@ int ns16550_serial_ofdata_to_platdata(struct
>>> udevice *dev)
>>> {
>>> struct ns16550_platdata *plat = dev->platdata;
>>> fdt_addr_t addr;
>>> +struct clk clk;
>>> +int err;
>
On 04/08/16 11:00, Michal Simek wrote:
On 1.8.2016 14:51, Paul Burton wrote:
On 01/08/16 13:41, Michal Simek wrote:
On 1.8.2016 14:09, Paul Burton wrote:
On 01/08/16 11:46, Michal Simek wrote:
On 1.8.2016 12:06, Paul Burton wrote:
This series introduces initial support for the MIPS Boston, a
On 04/08/16 10:54, Michal Simek wrote:
On 1.8.2016 12:06, Paul Burton wrote:
This patch adds a driver for the Xilinx AXI bridge for PCI express, an
IP block which can be used on some generations of Xilinx FPGAs. This is
mostly a case of implementing PCIe ECAM specification, but with some
quirk
This series introduces initial support for the MIPS Boston, and FPGA
based development board & successor to the older Malta board. Further
peripheral work is needed but this introduces the basics.
This can be tested in a currently out-of-tree QEMU port if desired.
Please see the included doc/READM
The implementations of clk_get_by_index & clk_get_by_name are only
available when CONFIG_CLK is enabled. Provide the dummies when this is
not the case in order to avoid build failures.
Signed-off-by: Paul Burton
---
Changes in v6:
- New patch
Changes in v5: None
Changes in v4: None
Changes in
Previously ns16550 compatible UARTs probed via device tree have needed
their device tree nodes to contain a clock-frequency property. An
alternative to this commonly used with Linux is to reference a clock via
a phandle. This patch allows U-Boot to support that, retrieving the
clock frequency by pr
Import a copy of the dt-bindings/interrupt-controller/mips-gic.h header
from Linux, such that we can use device trees which include it without
modification.
Signed-off-by: Paul Burton
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
includ
This patch adds a driver for the Xilinx AXI bridge for PCI express, an
IP block which can be used on some generations of Xilinx FPGAs. This is
mostly a case of implementing PCIe ECAM specification, but with some
quirks about what devices are valid to access.
Signed-off-by: Paul Burton
Reviewed-by
In pci_uclass_pre_probe an attempt is made to detect whether the parent
of a device is a PCI device and that the device is thus a bridge. This
was being done by checking whether the parent of the device is of the
UCLASS_ROOT class. This causes problems if the PCI controller is a child
of some other
Reading the PCI BAR & converting the result to a physical address is not
safe across all architectures. For example on MIPS the virtual:physical
mapping is not 1:1, so we cannot directly make use of the physical
address.
Use the more generic BAR-mapping function dm_pci_map_bar to discover the
MMIO
The pch_gbe driver previously casted pointers to & from unsigned 32 bit
integers in many locations. This breaks the driver on 64 bit systems,
producing streams of compiler warnings about mismatched pointer &
integer sizes and then failing to keep track of addresses correctly at
runtime.
Fix the dr
The regmap_read & regmap_write functions were previously declared in
regmap.h but not implemented anywhere. The regmap implementation &
commit message of 6f98b7504f70 ("dm: Add support for register maps
(regmap)") indicate that only memory mapped accesses are supported for
now, so providing simple
Device model drivers have previously been matched to FDT nodes by virtue
of being the first driver in the driver list to be compatible with the
node. This ignores the fact that compatible strings in the device tree
are listed in order of priority - that is, if we have a node with 2
compatible strin
Provide a trivial syscon driver matching the generic "syscon" compatible
string, allowing for simple system controllers to be used without a
custom driver just as in Linux.
Signed-off-by: Paul Burton
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in
This patch introduces support for building U-Boot to run on the MIPS
Boston development board. This is a board built around an FPGA & an
Intel EG20T Platform Controller Hub, used largely as part of the
development of new CPUs and their software support. It is essentially
the successor to the older
Add a simple driver for the clocks provided by the MIPS Boston
development board. The system provides information about 2 clocks whose
rates are fixed by the bitfile flashed in the boards FPGA, and this
driver simply reads the rates of these 2 clocks.
Signed-off-by: Paul Burton
Reviewed-by: Simon
This might be useful to make sure relocation fixups really
happen. And since this info gets printed only in DEBUG
build it doesn't really hurt normal execution.
Signed-off-by: Alexey Brodkin
---
arch/arc/lib/relocate.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arc/lib/reloc
Initially IVT for ARCv2 was simply copypasted from ARCompact
with some selected fixes so basic stuff works.
Now we update it with more ARCv2 specific vectors like
* Software Interrupt
* Division by zero
* Data cache consistency error
* Misaligned access
Also normal interrupts are now implemen
Starting from arc-2016.03 GNU tools linker properly works with
symbols defined in linker script and so external declarations
are no longer required, dump them.
Signed-off-by: Alexey Brodkin
---
arch/arc/cpu/u-boot.lds | 51 +++--
arch/arc/include/asm/s
ARCangel was one of the main development boards back in the day but
now it's gone and replaced by other boards like ARC SDP.
But we also used to have simulation platform very similar to ARCangel4
in terms of CPU settings as well as basic IO like UART. Even though
ARCangel4 is long gone now we have
As of now we have 2 flavors of ARC SDP boards:
1) AXS101 - with ARC770 in ASIC
2) AXS103 - with ARC HS38 in FPGA
Both options share exactly the same base-board and only differ with
CPU-tiles in use. That means all peripherals are the same (they are
implemented in FPGA on the base-board) and so g
Hey guys,
I just started trying out my Pine64 1GB and mainline U-Boot and I've
found that:
commit 1a83fb4a17d959d7b037999ab7ed7e62429abe34
Author: Siarhei Siamashka
Date: Tue May 31 01:48:06 2016 +0300
sunxi: Move the SPL stack top to 0x1A000 on Allwinner A64/A80
is breaking boot for me.
On Thu, Aug 04, 2016 at 03:14:34PM +0300, Alexey Brodkin wrote:
> As of now we have 2 flavors of ARC SDP boards:
> 1) AXS101 - with ARC770 in ASIC
> 2) AXS103 - with ARC HS38 in FPGA
>
> Both options share exactly the same base-board and only differ with
> CPU-tiles in use. That means all perip
On Thu, Aug 04, 2016 at 03:02:44AM +, york sun wrote:
> (Resend)
>
> Tom,
>
> The following changes since commit ad6a303c578b0087749510d20c1c46ae13f20367:
>
> Merge git://git.denx.de/u-boot-fsl-qoriq (2016-08-02 20:45:24 -0400)
>
> are available in the git repository at:
>
> git:/
Hi Marek,
On Thu, 2016-08-04 at 07:34 +0200, Marek Vasut wrote:
> On 08/03/2016 05:17 PM, Chin Liang See wrote:
> > Add base address header file for Stratix10 SoC
> >
> > Signed-off-by: Chin Liang See
> > Cc: Marek Vasut
> > Cc: Dinh Nguyen
> > Cc: Ley Foon Tan
>
> Applied to the 01-arria10
On Wed, 2016-08-03 at 19:17 -0600, Simon Glass wrote:
> Hi,
>
Hi Simon,
> On 2 August 2016 at 21:24, Chin Liang See wrote:
> > Enable a simple malloc implementation which will minimize
> > memory usage prior relocation. This is essential as memory
> > available prior location is internal memory
On Thu, 2016-08-04 at 07:30 +0200, Marek Vasut wrote:
> On 08/03/2016 05:22 PM, Chin Liang See wrote:
>
> Hi,
Hi Marek,
>
> [...]
> > > > It's the fat driver which is utilizing the malloc.
> > >
> > > So fat is allocating stuff without freeing it ? I wonder if we
> > > should
> > > either fix
Hi,
On 04/08/16 16:01, Tom Rini wrote:
> Hey guys,
>
> I just started trying out my Pine64 1GB and mainline U-Boot and I've
> found that:
> commit 1a83fb4a17d959d7b037999ab7ed7e62429abe34
> Author: Siarhei Siamashka
> Date: Tue May 31 01:48:06 2016 +0300
>
> sunxi: Move the SPL stack top
On 08/04/2016 05:08 PM, Chin Liang See wrote:
> Hi Marek,
Hi,
> On Thu, 2016-08-04 at 07:34 +0200, Marek Vasut wrote:
>> On 08/03/2016 05:17 PM, Chin Liang See wrote:
>>> Add base address header file for Stratix10 SoC
>>>
>>> Signed-off-by: Chin Liang See
>>> Cc: Marek Vasut
>>> Cc: Dinh Nguyen
On Thu, 2016-08-04 at 17:27 +0200, Marek Vasut wrote:
> On 08/04/2016 05:08 PM, Chin Liang See wrote:
> > Hi Marek,
>
> Hi,
>
> > On Thu, 2016-08-04 at 07:34 +0200, Marek Vasut wrote:
> > > On 08/03/2016 05:17 PM, Chin Liang See wrote:
> > > > Add base address header file for Stratix10 SoC
> > >
On Thu, Aug 04, 2016 at 04:14:21PM +0100, Andre Przywara wrote:
> Hi,
>
> On 04/08/16 16:01, Tom Rini wrote:
> > Hey guys,
> >
> > I just started trying out my Pine64 1GB and mainline U-Boot and I've
> > found that:
> > commit 1a83fb4a17d959d7b037999ab7ed7e62429abe34
> > Author: Siarhei Siamashka
On Thu, Aug 04, 2016 at 11:36:01AM -0400, Tom Rini wrote:
> On Thu, Aug 04, 2016 at 04:14:21PM +0100, Andre Przywara wrote:
> > Hi,
> >
> > On 04/08/16 16:01, Tom Rini wrote:
> > > Hey guys,
> > >
> > > I just started trying out my Pine64 1GB and mainline U-Boot and I've
> > > found that:
> > > c
On 08/04/2016 05:12 PM, Chin Liang See wrote:
> On Thu, 2016-08-04 at 07:30 +0200, Marek Vasut wrote:
>> On 08/03/2016 05:22 PM, Chin Liang See wrote:
>>
>> Hi,
>
> Hi Marek,
>
>>
>> [...]
> It's the fat driver which is utilizing the malloc.
So fat is allocating stuff without freein
On 08/04/2016 05:32 PM, Chin Liang See wrote:
> On Thu, 2016-08-04 at 17:27 +0200, Marek Vasut wrote:
>> On 08/04/2016 05:08 PM, Chin Liang See wrote:
>>> Hi Marek,
>>
>> Hi,
>>
>>> On Thu, 2016-08-04 at 07:34 +0200, Marek Vasut wrote:
On 08/03/2016 05:17 PM, Chin Liang See wrote:
> Add ba
Hi Simon,
On Wed, Aug 3, 2016 at 8:17 PM, Simon Glass wrote:
> Hi Joe,
>
> On 3 August 2016 at 17:18, Joe Hershberger wrote:
>> On Tue, Aug 2, 2016 at 2:20 AM, Stefan Agner wrote:
>>> From: Stefan Agner
>>>
>>> Flush loaded data cacheline aligned. This avoids warnings such as
>>> CACHE: Misali
On Tue, Jul 12, 2016 at 4:52 PM, Chris Packham wrote:
> The __get_unaligned_le* functions may not be declared on all platforms.
> Instead, get_unaligned_le* should be used. On many platforms both of
> these are the same function.
>
> Signed-off-by: Chris Packham
Acked-by: Joe Hershberger
__
Hi Paul,
On Thu, Aug 4, 2016 at 5:29 AM, Paul Burton wrote:
> The pch_gbe driver previously casted pointers to & from unsigned 32 bit
> integers in many locations. This breaks the driver on 64 bit systems,
> producing streams of compiler warnings about mismatched pointer &
> integer sizes and the
On 04/08/16 17:23, Joe Hershberger wrote:
Hi Paul,
On Thu, Aug 4, 2016 at 5:29 AM, Paul Burton wrote:
The pch_gbe driver previously casted pointers to & from unsigned 32 bit
integers in many locations. This breaks the driver on 64 bit systems,
producing streams of compiler warnings about mis
On Wed, Aug 3, 2016 at 4:31 AM, Alban Bedel
wrote:
> When adding support for the driver model the SPI EEPROM feature had
> been ignored. Fix the build with both CONFIG_DM_ETH and
> CONFIG_E1000_SPI enabled.
>
> Signed-off-by: Alban Bedel
Acked-by: Joe Hershberger
___
On Thu, Aug 4, 2016 at 5:29 AM, Paul Burton wrote:
> The pch_gbe driver previously casted pointers to & from unsigned 32 bit
> integers in many locations. This breaks the driver on 64 bit systems,
> producing streams of compiler warnings about mismatched pointer &
> integer sizes and then failing
On Thu, Aug 4, 2016 at 5:29 AM, Paul Burton wrote:
> Reading the PCI BAR & converting the result to a physical address is not
> safe across all architectures. For example on MIPS the virtual:physical
> mapping is not 1:1, so we cannot directly make use of the physical
> address.
>
> Use the more g
On Tue, Aug 2, 2016 at 9:42 PM, Yaroslav K. wrote:
> Fix compile errors when enabling CONFIG_DM_ETH,
> CONFIG_CMD_E1000 and CONFIG_E1000_SPI.
>
> Signed-off-by: Yaroslav K.
Something about this patch email is malformed and not parsed by
patchwork properly.
Another patch with the same intent was
On Wed, Aug 3, 2016 at 4:31 AM, Alban Bedel
wrote:
> When adding support for the driver model the SPI EEPROM feature had
> been ignored. Fix the build with both CONFIG_DM_ETH and
> CONFIG_E1000_SPI enabled.
>
> Signed-off-by: Alban Bedel
This was also sent by Yaroslav K. :
https://patchwork.ozla
On Tue, Aug 2, 2016 at 9:42 PM, Yaroslav K. wrote:
> Fix compile errors when enabling CONFIG_DM_ETH,
> CONFIG_CMD_E1000 and CONFIG_E1000_SPI.
>
> Signed-off-by: Yaroslav K.
In the future please Cc me when sending network patches.
scripts/patman/patman can help you with this.
Also, please do not
On Tue, Aug 2, 2016 at 10:04 PM, Gong Qianyu wrote:
> The current code would always use the speed and mode set by
> CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using
> SPI driver model it should get the values from DT.
>
> Signed-off-by: Gong Qianyu
> Reviewed-by: Jagan Teki
Reviewed-
On Wed, Jul 27, 2016 at 7:57 PM, Max Filippov wrote:
> print_eth_ip_addr outputs eth configurations for up to 6 interfaces and
> configured IP address.
>
> Signed-off-by: Max Filippov
Acked-by: Joe Hershberger
___
U-Boot mailing list
U-Boot@lists.denx
On Tue, May 17, 2016 at 12:11 AM, Wenyou Yang wrote:
> Use the right phy_connect() prototype for CONFIGF_DM_ETH.
> Support to get the phy interface from dt and set GMAC_UR.
>
> Signed-off-by: Wenyou Yang
> ---
> This patch is based on the patch set,
> [PATCH 00/18] at91: Convert Ethernet and LCD
On 2016-08-04 09:14, Joe Hershberger wrote:
> Hi Simon,
>
> On Wed, Aug 3, 2016 at 8:17 PM, Simon Glass wrote:
>> Hi Joe,
>>
>> On 3 August 2016 at 17:18, Joe Hershberger wrote:
>>> On Tue, Aug 2, 2016 at 2:20 AM, Stefan Agner wrote:
From: Stefan Agner
Flush loaded data cachelin
Hi Tom,
On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> Hello,
>
> this series does the following improvements to the OpenCores 10/100 Mbps
> driver:
> - add Kconfig symbol for the driver;
> - add DM_ETH support;
> - add device tree support;
> - add optional phylib support;
> - add support
On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> Add Kconfig entry for the driver, remove #define CONFIG_ETHOC from the
> only board configuration that uses it and put it into that board's
> defconfig.
>
> Cc: Stefan Kristiansson
> Signed-off-by: Max Filippov
Acked-by: Joe Hershberger
___
On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> Don't use physical base address of registers directly, ioremap it first.
> Save pointer in private struct ethoc and use that struct in all internal
> functions.
>
> Signed-off-by: Max Filippov
Acked-by: Joe Hershberger
__
On Thu, Aug 04, 2016 at 12:10:33PM -0500, Joe Hershberger wrote:
> Hi Tom,
>
> On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> > Hello,
> >
> > this series does the following improvements to the OpenCores 10/100 Mbps
> > driver:
> > - add Kconfig symbol for the driver;
> > - add DM_ETH supp
On Wed, Aug 03, 2016 at 07:43:24PM -0700, Stefan Agner wrote:
> On 2016-08-03 16:18, Joe Hershberger wrote:
> > On Tue, Aug 2, 2016 at 2:20 AM, Stefan Agner wrote:
> >> From: Stefan Agner
> >>
> >> Flush loaded data cacheline aligned. This avoids warnings such as
> >> CACHE: Misaligned operation
On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> Extract reusable parts from ethoc_init, ethoc_set_mac_address,
> ethoc_send and ethoc_receive, move the rest under #ifdef CONFIG_DM_ETH.
> Add U_BOOT_DRIVER, eth_ops structure and implement required methods.
>
> Signed-off-by: Max Filippov
A
On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> Add .of_match table and .ofdata_to_platdata callback to allow for ethoc
> device configuration from the device tree.
>
> Signed-off-by: Max Filippov
Acked-by: Joe Hershberger
___
U-Boot mailing lis
On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> Addresses used in buffer descriptors and passed in platform data or
> device tree are physical. Addresses used by CPU to access packet data
> and registers are virtual. Don't mix these addresses and use virt_to_phys
> for translation.
>
> Signe
On 08/03/2016 07:16 PM, Simon Glass wrote:
Hi Stephen,
On 1 August 2016 at 09:22, Stephen Warren wrote:
On 07/31/2016 07:02 PM, Simon Glass wrote:
Hi Stephen,
On 27 July 2016 at 15:48, Stephen Warren wrote:
From: Stephen Warren
Tegra186 supports the new standard clock, reset, and power
On 08/03/2016 07:16 PM, Simon Glass wrote:
Hi Stephen,
On 1 August 2016 at 09:50, Stephen Warren wrote:
On 07/31/2016 08:20 PM, Simon Glass wrote:
Hi Stephen,
On 27 July 2016 at 15:24, Stephen Warren wrote:
From: Stephen Warren
Tegra186 supports the new standard clock and reset APIs. O
On 08/04/2016 01:11 AM, Alexander Graf wrote:
On the raspberry pi, you can disable the serial port to gain dynamic frequency
scaling which can get handy at times.
However, in such a configuration the serial controller gets its rx queue filled
up with zero bytes which then happily get transmitted
On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> The ethoc device can be configured to have a private memory region
> instead of having access to the main memory. In that case egress packets
> must be copied into that memory for transmission and pointers to that
> memory need to be passed to
On Thu, 4 Aug 2016 11:40:25 -0400
Tom Rini wrote:
> On Thu, Aug 04, 2016 at 11:36:01AM -0400, Tom Rini wrote:
> > On Thu, Aug 04, 2016 at 04:14:21PM +0100, Andre Przywara wrote:
> > > Hi,
> > >
> > > On 04/08/16 16:01, Tom Rini wrote:
> > > > Hey guys,
> > > >
> > > > I just started trying
On 04/08/16 20:58, Siarhei Siamashka wrote:
> On Thu, 4 Aug 2016 11:40:25 -0400
> Tom Rini wrote:
Hi,
thanks Siarhei for the answer and the explanation!
>
>> On Thu, Aug 04, 2016 at 11:36:01AM -0400, Tom Rini wrote:
>>> On Thu, Aug 04, 2016 at 04:14:21PM +0100, Andre Przywara wrote:
>>
Hi Max,
On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> Implement MDIO bus read/write functions, initialize the bus and scan for
> the PHY when phylib is enabled. Limit PHY speeds to 10/100 Mbps.
>
> Cc: Michal Simek
> Signed-off-by: Max Filippov
> ---
> drivers/net/ethoc.c | 152
>
On Thu, Aug 04, 2016 at 10:58:30PM +0300, Siarhei Siamashka wrote:
> On Thu, 4 Aug 2016 11:40:25 -0400
> Tom Rini wrote:
>
> > On Thu, Aug 04, 2016 at 11:36:01AM -0400, Tom Rini wrote:
> > > On Thu, Aug 04, 2016 at 04:14:21PM +0100, Andre Przywara wrote:
> > > > Hi,
> > > >
> > > > On 04/08/16
Hi Stephen,
On Tue, Aug 2, 2016 at 11:56 AM, Stephen Warren wrote:
> On 08/01/2016 09:20 PM, Peter Chubb wrote:
>>
>>
>> Hi Folks,
>>Since patch 96350f729c42 "dm: tegra: net: Convert tegra boards to
>>driver model for Ethernet" booting via dhcp has been broken on the
>>Jetson TK1.
>
>
On Thu, Aug 4, 2016 at 4:22 PM, Joe Hershberger
wrote:
> Hi Stephen,
>
> On Tue, Aug 2, 2016 at 11:56 AM, Stephen Warren wrote:
>> On 08/01/2016 09:20 PM, Peter Chubb wrote:
>>>
>>>
>>> Hi Folks,
>>>Since patch 96350f729c42 "dm: tegra: net: Convert tegra boards to
>>>driver model for Ethe
Stephen,
> -Original Message-
> From: Stephen Warren [mailto:swar...@wwwdotorg.org]
> Sent: Thursday, August 04, 2016 11:59 AM
> To: Simon Glass
> Cc: U-Boot Mailing List ; Tom Warren
> ; Stephen Warren ; Pantelis
> Antoniou
> Subject: Re: [PATCH 8/9] mmc: tegra: port to standard clock/r
On Thu, Aug 4, 2016 at 4:34 PM, Joe Hershberger
wrote:
> On Thu, Aug 4, 2016 at 4:22 PM, Joe Hershberger
> wrote:
>> Hi Stephen,
>>
>> On Tue, Aug 2, 2016 at 11:56 AM, Stephen Warren
>> wrote:
>>> On 08/01/2016 09:20 PM, Peter Chubb wrote:
Hi Folks,
Since patch 96350f729c
> On 04 Aug 2016, at 20:11, Stephen Warren wrote:
>
> On 08/04/2016 01:11 AM, Alexander Graf wrote:
>> On the raspberry pi, you can disable the serial port to gain dynamic
>> frequency
>> scaling which can get handy at times.
>>
>> However, in such a configuration the serial controller gets it
Add driver model support while retaining the existing legacy code.
This allows the driver to support boards that have converted to
driver model as well as those that have not.
Signed-off-by: Wenyou Yang
Acked-by: Simon Glass
---
Changes in v3:
- Change clk_client.h -> clk.h to adapt to clk API
Convert the driver to the driver model while retaining the existing
legacy code. This allows the driver to support boards that have
converted to driver model as well as those that have not.
Signed-off-by: Wenyou Yang
Reviewed-by: Simon Glass
Reviewed-by: Jaehoon Chung
Reviewed-by: Heiko Schoche
Hi Stefan,
On Thu, Aug 4, 2016 at 2:41 AM, Stefan Agner wrote:
> - mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
> +
> + /*
> +* Make sure range is cache line aligned
> +* Only CPU maintains page tables, hence it is save to always
s/save/safe
On 3 August 2016 at 23:41, Stefan Agner wrote:
> From: Stefan Agner
>
> The page table is maintained by the CPU, hence it is safe to always
> align cache flush to a whole cache line size. This allows to use
> mmu_page_table_flush for a single page table, e.g. when configure
> only small regions t
Hi Paul,
On 4 August 2016 at 04:29, Paul Burton wrote:
> Device model drivers have previously been matched to FDT nodes by virtue
> of being the first driver in the driver list to be compatible with the
> node. This ignores the fact that compatible strings in the device tree
> are listed in order
Hi Paul,
On 4 August 2016 at 04:29, Paul Burton wrote:
> Previously ns16550 compatible UARTs probed via device tree have needed
> their device tree nodes to contain a clock-frequency property. An
> alternative to this commonly used with Linux is to reference a clock via
> a phandle. This patch al
Hi Stephen,
On 25 July 2016 at 13:57, Stephen Warren wrote:
> On 07/22/2016 08:08 PM, Simon Glass wrote:
>>
>> Hi Stephen,
>>
>> On 18 July 2016 at 12:17, Stephen Warren wrote:
>>>
>>> From: Stephen Warren
>>>
>>> IVC (Inter-VM Communication) protocol is a Tegra-specific IPC (Inter
>>> Processo
Hi Paul,
On 4 August 2016 at 04:29, Paul Burton wrote:
> The implementations of clk_get_by_index & clk_get_by_name are only
> available when CONFIG_CLK is enabled. Provide the dummies when this is
> not the case in order to avoid build failures.
Where are the dummies?
>
> Signed-off-by: Paul Bu
Hi Stephen,
On 1 August 2016 at 09:46, Stephen Warren wrote:
> On 07/31/2016 07:02 PM, Simon Glass wrote:
>>
>> Hi Stephen,
>>
>> On 27 July 2016 at 15:24, Stephen Warren wrote:
>>>
>>> From: Stephen Warren
>>>
>>> In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP
>>> (B
Hi Paul,
On 4 August 2016 at 04:24, Paul Burton wrote:
>
>
> On 04/08/16 10:54, Michal Simek wrote:
>>
>> On 1.8.2016 12:06, Paul Burton wrote:
>>>
>>> This patch adds a driver for the Xilinx AXI bridge for PCI express, an
>>> IP block which can be used on some generations of Xilinx FPGAs. This i
Hi Gregory,
On 3 August 2016 at 21:21, Gregory Ray wrote:
> Hello,
>
> Is SecureBoot from the manufacturers u-boot distribution operational? When I
> try to sign the loader using the SBC it complains "Sign loader failed!"
>
> I did a standard make:
>
> CROSS_COMPILE=/Developer/arm-eabi-4.8/bin/ar
Hi Stephen,
On 4 August 2016 at 12:52, Stephen Warren wrote:
> On 08/03/2016 07:16 PM, Simon Glass wrote:
>>
>> Hi Stephen,
>>
>> On 1 August 2016 at 09:22, Stephen Warren wrote:
>>>
>>> On 07/31/2016 07:02 PM, Simon Glass wrote:
Hi Stephen,
On 27 July 2016 at 15:48, Ste
Hi Stephen,
On 1 August 2016 at 14:52, Stephen Warren wrote:
> From: Stephen Warren
>
> Some code may want to read reg values from DT, but from nodes that aren't
> associated with DM devices, so using dev_get_addr_index() isn't
> appropriate. In this case, fdtdec_get_addr_size_*() are the functi
On 3 August 2016 at 21:40, Kever Yang wrote:
> To compatible with distro boot, we need to add gpt and fs support,
> including gpt table and vfat, ext2, ext4 support.
>
> Signed-off-by: Kever Yang
> Reviewed-by: Simon Glass
> ---
>
> Changes in v2:
> - remove some re-defined MACRO, comments from
+Tom
On 4 August 2016 at 01:44, Wenbin song wrote:
> From: York Sun
>
> When FIT image is used, a single image provides kernel, device
> tree and optionally ramdisk. Argc and argv need to be adjusted
> to support this.
>
> Signed-off-by: York Sun
> ---
> cmd/pxe.c | 9 +
> 1 file chang
Recently I have seen mails not reaching mailing list many times. Not sure if it
was our email server issue.
York
Original Message
From: Simon Glass
Sent: Thursday, August 4, 2016 06:37 PM
To: Wenbin Song
Subject: Re: [PATCH] pxe: Fix pxe boot with FIT image
CC: Bin Meng ,Hei
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