On 2016-08-04 09:14, Joe Hershberger wrote: > Hi Simon, > > On Wed, Aug 3, 2016 at 8:17 PM, Simon Glass <s...@chromium.org> wrote: >> Hi Joe, >> >> On 3 August 2016 at 17:18, Joe Hershberger <joe.hershber...@gmail.com> wrote: >>> On Tue, Aug 2, 2016 at 2:20 AM, Stefan Agner <ste...@agner.ch> wrote: >>>> From: Stefan Agner <stefan.ag...@toradex.com> >>>> >>>> Flush loaded data cacheline aligned. This avoids warnings such as >>>> CACHE: Misaligned operation at range [81000000, 816d0fa8] >>>> >>>> Signed-off-by: Stefan Agner <stefan.ag...@toradex.com> >>>> --- >>> >>> This was already rejected once. >>> http://lists.denx.de/pipermail/u-boot/2012-April/121564.html >>> >>>> Why do we actually have to flush caches after load? It seems to >>>> have worked so far despite the caches did not get flushed (due to >>>> missalignment). >>> >>> I'm not sure that we do, but it's been there since as far back as the >>> git history goes. Maybe Wolfgang has memory of a reason. >> >> I think this is the correct solution. If you load something to memory >> you have to flush the cache. If someone is brave enough to load an >> image that finishes immediately before something where there is data >> that will be overwritten by the flush, then they deserve some pain. > > I'm not at all worried about the overwrite case. > >> Anytime we flush the cache we have to do it according the rules of the >> cache. One of those rules is that cache lines are larger than one >> byte. So either we don't flush or we do, and if we do, we must align. > > For sure... I was just wondering why we need this flush at all. > Stefan's comment as to why seems reasonable now, but that reasoning > surely wasn't a concern pre-2000. Maybe some early arch needed it for > a different reason? Maybe someone was planning to DMA directly from > the memory that was loaded, but in that case it seems like the code > starting the DMA would ensure the flush, not the code that is > memcpy'ing from somewhere.
Just to clarify my point on this: Non cache coherent (peripheral) CPU's was the only reason I could think of, but I don't think it is a reason to actually do it. IMHO it should be handled the same way as DMA gets handled: if a non cache coherent CPU is about to get started, that code should make sure to handle the cache flush... (e.g. the bootaux command in the i.MX 7 case). -- Stefan _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
