On Tue, 6 Dec 2016, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> The drivers is restructured such common functions, gen5 functions,
> and arria10 functions are moved to misc.c, misc_gen5 and misc_arria10
> respectively.
>
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
From: Dinh Nguyen
Update the pinmux and pll configuration for the Cyclone5 RevE or later devkit.
Signed-off-by: Dinh Nguyen
---
Hi Marek,
Without these pinmux and pll changes, DS-5 is unable to connect to my board
and Linux is stuck in a loop and eventually the watchdog will trigger a
reset.
From: Dinh Nguyen
Move common config options like these to socfpga_common.h:
CONFIG_SYS_NO_FLASH
CONFIG_DOS_PARTITION
CONFIG_FAT_WRITE
CONFIG_HW_WATCHDOG
CONFIG_CMD_ASKENV
CONFIG_CMD_BOOTZ
CONFIG_CMD_CACHE
CONFIG_CMD_DHCP
CONFIG_CMD_EXT4
CONFIG_CMD_EXT4_WRITE
CONFIG_CMD_FAT
CONFIG_CMD_FS_GENERI
From: Dinh Nguyen
For the case where an external VBUS is used, we should enable the external
VBUS comparator in the driver. This would prevent an unnecessary overcurrent
error which would then disable the host port.
The overcurrent condition was happening on the SoCFPGA Cyclone5 devkit, thus
USB
From: Dinh Nguyen
For the case where an external VBUS is used, we should enable the external
VBUS comparator in the driver. This would prevent an unnecessary overcurrent
error which would then disable the host port.
The overcurrent condition was happening on the SoCFPGA Cyclone5 devkit, thus
USB
From: Dinh Nguyen
The picoseconds to register value divisor(ps_to_regval) should be 60 and not
200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct
divisor because the 4-bit skew values are defined from 0x(-420ps) to
0x(480ps), increments of 60.
For example, a DTS
From: Dinh Nguyen
Add the DTS documentation for the Micrel KSZ90x1 binding.
The original document was from:
[commit 4b405efbe12de28b26289282b431323d73992381 from the Linux kernel]
This takes the original document and adds a clarification on how the skew
values are represented in the code.
Refe
From: Dinh Nguyen
On the Arria10, the EMAC phy mode configuration for each EMACs is located
in separate registers versus being in 1 register for the GEN5 devices. The
Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.
Update the dwmac_deassert_reset function to support both GEN5 and Ar
From: Dinh Nguyen
Add the Arria10 reset manager defines that is used in Linux. Change the
license to SPDX.
[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]
Signed-off-by: Dinh Nguyen
---
v2: Add commit hash-id for original commit from Linux kernel
---
include/dt-binding
From: Dinh Nguyen
There is no dependency on doing a separate clrbits first in the
dwmac_deassert_reset function. Combine them into a single
clrsetbits call.
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/misc.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/
From: Dinh Nguyen
The Arria10 device will not be able to re-use the GEN5 SDRAM controller,
so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig
option in drivers/ddr/altera/Kconfig.
Signed-off-by: Dinh Nguyen
---
drivers/Kconfig | 2 ++
drivers/ddr/Kconfig
From: Dinh Nguyen
These functions are already in arch/arm/mach-socfpga/board.c
Signed-off-by: Dinh Nguyen
---
board/altera/arria10-socdk/socfpga.c | 17 -
1 file changed, 17 deletions(-)
diff --git a/board/altera/arria10-socdk/socfpga.c
b/board/altera/arria10-socdk/socfpga.c
From: Dinh Nguyen
Hi,
This is another round of patches for the Arria10 device. There are still some
build failures that related to the clocking, FPGA manager, and bridge support.
Thanks,
Dinh Nguyen (6):
arm: socfpga: wrap system manager functions for A5/C5 devices
arm: socfpga: add reset
From: Dinh Nguyen
On the Arria10 device, the bridges are not mapped through the interconnect.
Signed-off-by: Dinh Nguyen
---
drivers/fpga/socfpga.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index 4448250..75368e6 100644
--- a/drivers/
From: Dinh Nguyen
On the Arria10, the EMAC phy mode configuration for each EMACs is located
in separate registers versus being in 1 register for the GEN5 devices. The
Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.
Update the dwmac_deassert_reset function to support both GEN5 and Ar
From: Dinh Nguyen
The system manager on Arria10 is not used for pin muxing duties, so wrap
these functions for GEN5 devices only.
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/system_manager.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-socfpga/system_manager.c
From: Dinh Nguyen
Add the Arria10 reset manager defines that is used in Linux. Change the
license to SPDX.
Signed-off-by: Dinh Nguyen
---
include/dt-bindings/reset/altr,rst-mgr-a10.h | 103 +++
1 file changed, 103 insertions(+)
create mode 100644 include/dt-bindings/re
From: Dinh Nguyen
We should be setting the FPGA Interface Group global bit that will correctly
disable all interfaces between the FPGA and HPS.
Signed-off-by: Dinh Nguyen
---
drivers/fpga/socfpga.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/fpga/socfpga.c b/dri
From: Dinh Nguyen
Now that the USB DWC2 probing is done from OF, remove this note to add
CONFIG_USB_DWC2_REG_ADDR.
Signed-off-by: Dinh Nguyen
---
include/configs/socfpga_common.h | 7 ---
1 file changed, 7 deletions(-)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpg
From: Dinh Nguyen
Replace__CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ with
__CONFIG_SOCFPGA_OMMON_H__ as the file is now called socfpga_common.h
Signed-off-by: Dinh Nguyen
---
include/configs/socfpga_common.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/configs/soc
From: Dinh Nguyen
On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that
the reading the bsel can generic.
Suggested-by: Marek Vasut
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/include/ma
From: Dinh Nguyen
Add the defines for the reset manager and some basic reset functionality.
Signed-off-by: Dinh Nguyen
---
v5: rename the mod_reest on A10 to match those in gen5
v4: rename mod_reset names to be used by both gen5 and a10
v3: remove duplicate reset function
use CONFIG_SOCFPGA
From: Dinh Nguyen
Move the macro into the socfpga_dwmci_clksel().
Signed-off-by: Dinh Nguyen
---
v2: add SYSMGR_SDMMC_DRVSEL_SHIFT
s/SYSMGR_SDMMC_SMPSEL_SHIFT/SYSMGR_SDMMC_SMPLSEL_SHIFT
---
arch/arm/mach-socfpga/include/mach/system_manager.h | 10 +++---
drivers/mmc/socfpga_dw_mmc.c
From: Dinh Nguyen
The scan manager is not needed for the Arria10. Edit the makefile to
build the scan manager for arria5 and cyclone5 only.
Signed-off-by: Dinh Nguyen
Acked-by: Marek Vasut
---
v4: use CONFIG_TARGET_SOCFPGA_GEN5 option for build
v3: use CONFIG_SOCFPGA_GEN5 option for build
---
From: Dinh Nguyen
Add a defconfig file for Arria10, which does not include enabling SPL.
Signed-off-by: Dinh Nguyen
Acked-by: Marek Vasut
---
v4: none
v3: align with u-boot-socfpga/master
v2: none
---
configs/socfpga_arria10_defconfig | 16
1 file changed, 16 insertions(+)
c
From: Dinh Nguyen
Signed-off-by: Dinh Nguyen
---
v4: reorder ARRIA10 below ARRIA5
v3: none
v2: none
---
arch/arm/Kconfig | 4 ++--
arch/arm/mach-socfpga/Kconfig | 10 ++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
ind
From: Dinh Nguyen
Add config for the Arria10 SoC Development Kit.
Signed-off-by: Dinh Nguyen
Acked-by: Marek Vasut
---
v4: none
v3: further clean up, remove extra defines, keep bare mininum options
v2: clean up socfpga_arria10_socdk.h to use socfpga_common.h
---
include/configs/socfpga_arria1
From: Dinh Nguyen
Add arch_early_init_r function. The Arria10 has a firewall protection
around the SDRAM and OCRAM. These firewalls are to be disabled in order
for U-Boot to function.
Signed-off-by: Dinh Nguyen
---
v4: be consistent and use #if->else throughout
v3: s/reset_assert_all_peripheral
From: Dinh Nguyen
In order to re-use as much Cyclone5 and Arria5 code as possible to support
the Arria10 platform, we need to wrap some of the code with #ifdef's. By
adding CONFIG_TARGET_SOCFPGA_GEN5, we can shorten the check by not having to
check
for both AV || AV.
Signed-off-by: Dinh Nguyen
From: Dinh Nguyen
Add the defines for the reset manager and some basic reset functionality.
Signed-off-by: Dinh Nguyen
---
v4: rename mod_reset names to be used by both gen5 and a10
v3: remove duplicate reset function
use CONFIG_SOCFPGA_GEN5
v2: integrate into a5/c5 reset manager
---
arch/
From: Dinh Nguyen
Add system manager defines for Arria10.
Signed-off-by: Dinh Nguyen
---
v4: none
v3: combine system_manager_a10.h into system_manager.h
v2: clean up parenthesis
---
.../arm/mach-socfpga/include/mach/system_manager.h | 122 +
1 file changed, 122 insertions(+
From: Dinh Nguyen
Hi,
This is v4 of the patch series that adds minimal support for Altera's Arria10
platform.
v4:
- s/CONFIG_SOCFPGA_GEN5/CONFIG_TARGET_SOCFPGA_GEN5
- rename mod_reset(s) in the gen5 reset manager to match a10
- clean up of #if-else throughout misc.c
- reorder CONFIG_TARGET_SOCF
From: Dinh Nguyen
The scan manager is not needed for the Arria10. Edit the makefile to
build the scan manager for arria5 and cyclone5 only.
Signed-off-by: Dinh Nguyen
---
v3: use CONFIG_SOCFPGA_GEN5 option for build
---
arch/arm/mach-socfpga/Makefile | 5 +++--
1 file changed, 3 insertions(+),
From: Dinh Nguyen
Add config for the Arria10 SoC Development Kit.
Signed-off-by: Dinh Nguyen
---
v3: further clean up, remove extra defines, keep bare mininum options
v2: clean up socfpga_arria10_socdk.h to use socfpga_common.h
---
include/configs/socfpga_arria10_socdk.h | 94 +
From: Dinh Nguyen
Signed-off-by: Dinh Nguyen
---
v2: none
---
arch/arm/Kconfig | 4 ++--
arch/arm/mach-socfpga/Kconfig | 10 ++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 408e4ff..c43c8b4 100644
--- a/arch/arm/
From: Dinh Nguyen
Add arch_early_init_r function. The Arria10 has a firewall protection
around the SDRAM and OCRAM. These firewalls are to be disabled in order
for U-Boot to function.
Signed-off-by: Dinh Nguyen
---
v3: s/reset_assert_all_peripherals_except_l4wd0_l4timer0/socfpga_per_reset_all
From: Dinh Nguyen
Move the macro into the socfpga_dwmci_clksel().
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/include/mach/system_manager.h | 8 +---
drivers/mmc/socfpga_dw_mmc.c| 5 +++--
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/
From: Dinh Nguyen
Add a defconfig file for Arria10, which does not include enabling SPL.
Signed-off-by: Dinh Nguyen
---
v3: align with u-boot-socfpga/master
v2: none
---
configs/socfpga_arria10_defconfig | 16
1 file changed, 16 insertions(+)
create mode 100644 configs/socfpg
From: Dinh Nguyen
Add the defines for the reset manager and some basic reset functionality.
Signed-off-by: Dinh Nguyen
---
v3: remove duplicate reset function
use CONFIG_SOCFPGA_GEN5
v2: integrate into a5/c5 reset manager
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 65
From: Dinh Nguyen
Add system manager defines for Arria10.
Signed-off-by: Dinh Nguyen
---
v3: combine system_manager_a10.h into system_manager.h
v2: clean up parenthesis
---
.../arm/mach-socfpga/include/mach/system_manager.h | 122 +
1 file changed, 122 insertions(+)
diff -
From: Dinh Nguyen
Hi,
This is v3 of the patch series that adds minimal support for Altera's Arria10
platform.
v3:
- Add CONFIG_SOCFPGA_GEN5 for building for Arria5 and Cyclone5
- Clean up socfpga_arria10_socdk
- Add patch to remove the macro SYSMGR_SDMMC_CTRL_SET
- Move system_manager_a10.h int
From: Dinh Nguyen
In order to re-use as much Cyclone5 and Arria5 code as possible to support
the Arria10 platform, we need to wrap some of the code with #ifdef's. By
adding CONFIG_SOCFPGA_GEN5, we can shorten the check by not having to check
for both AV || AV.
Signed-off-by: Dinh Nguyen
---
ar
From: Dinh Nguyen
Not sure what made this macro questionable, but edit the macro to be similar
to what is used in Linux.
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/include/mach/system_manager.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpg
From: Dinh Nguyen
Define SOCFPGA_GEN5 which applies to Arria5/Cyclone5 hardware, and
SOCFPGA_GEN10 for Arria10 hardware.
This would allow us to use the shorten define in the rest of code.
Signed-off-by: Dinh Nguyen
---
include/configs/socfpga_common.h | 5 +
1 file changed, 5 insertions(+
From: Dinh Nguyen
Signed-off-by: Dinh Nguyen
---
v2: none
---
arch/arm/Kconfig | 4 ++--
arch/arm/mach-socfpga/Kconfig | 10 ++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5ab0254..1d78e40 100644
--- a/arch/arm/
From: Dinh Nguyen
Add a defconfig file for Arria10, which does not include enabling SPL.
Signed-off-by: Dinh Nguyen
---
v2: none
---
configs/socfpga_arria10_defconfig | 11 +++
1 file changed, 11 insertions(+)
create mode 100644 configs/socfpga_arria10_defconfig
diff --git a/configs/
From: Dinh Nguyen
Add minimal support for the Arria10 SoCDK.
Signed-off-by: Dinh Nguyen
---
v2: Cleaned up copyright
---
board/altera/arria10-socdk/Kconfig | 18 ++
board/altera/arria10-socdk/Makefile | 7 +++
board/altera/arria10-socdk/socfpga.c | 24 ++
From: Dinh Nguyen
Add config for the Arria10 SoC Development Kit.
Signed-off-by: Dinh Nguyen
---
v2: clean up socfpga_arria10_socdk.h to use socfpga_common.h
---
include/configs/socfpga_arria10_socdk.h | 157
1 file changed, 157 insertions(+)
create mode 10064
From: Dinh Nguyen
The scan manager is not needed for the Arria10. Edit the makefile to
build the scan manager for arria5 and cyclone5 only.
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/Makefile | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-soc
From: Dinh Nguyen
Add the structures for the SDRAM controller on Arria10.
Signed-off-by: Dinh Nguyen
---
v2: Remove union bitfields
---
arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 +
1 file changed, 380 insertions(+)
create mode 100644 arch/arm/mach-socfpga/in
From: Dinh Nguyen
Add miscellaneous functions(arch_early_init_r, print_cpuinfo,
overwrite_console, enable_caches, and cpu_mmc_init). Also, the Arria10
has a firewall protection around the SDRAM and OCRAM. These firewalls
are to be disabled in order for U-Boot to function.
Signed-off-by: Dinh Ngu
From: Dinh Nguyen
Add system manager defines for Arria10.
Signed-off-by: Dinh Nguyen
---
v2: clean up parenthesis
---
.../mach-socfpga/include/mach/system_manager_a10.h | 157 +
1 file changed, 157 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/system_
From: Dinh Nguyen
Add the defines for the reset manager and some basic reset functionality.
Signed-off-by: Dinh Nguyen
---
v2: integrate into a5/c5 reset manager
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 66 ++
arch/arm/mach-socfpga/reset_manager.c
From: Dinh Nguyen
Hi,
This is v2 of the patch series that adds minimal support for Altera's Arria10
platform.
v2:
- Removes the need for a separate /mach-socfpga/arria10 directory
- Tries to re-use alot of the Arria5/Cyclone5 code
- Removes the usage of unions bitfields in the SDRAM defines
v1
From: Dinh Nguyen
Add remaining 3 I2C base addresses for the Arria10.
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
b/arch/arm/mach-socfpga/include/ma
From: Dinh Nguyen
When adding support for the Arria10 platform, we're going to name the file
base_addr_a10.h, so to be systematic about it, rename the socfpga_base_addr.h
to be base_addr_ac5.h for the Arria5 and Cyclone5 platform.
Suggested-by: Marek Vasut
Signed-off-by: Dinh Nguyen
---
.../m
From: Dinh Nguyen
Add the base address map for Arria10.
Signed-off-by: Dinh Nguyen
Reviewed-by: Marek Vasut
---
v2: renamed to base_addr_a10.h
---
arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 45 ++
1 file changed, 45 insertions(+)
create mode 100644 arch/arm/mach
From: Dinh Nguyen
Hi,
This patchset adds the foundation support for Arria10. The series builds for
the Altera Arria10 SoCDK, but is not entirely functional on the hardware yet.
This series really just add the defines, build and Kconfig layout for Arria10.
There are few TODO after this series:
-
From: Dinh Nguyen
Add the defines for the reset manager and some basic reset functionality.
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/arria10/reset_manager_a10.c | 83 +++
.../mach-socfpga/include/mach/reset_manager_a10.h | 162 +
2 files changed, 245
From: Dinh Nguyen
For now, sdram_a10.c will only have sdram_init() function, but this
will get populated in the near future with more functionality.
Also add the structures for the SDRAM controller on Arria10.
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/arria10/sdram_a10.c | 15
From: Dinh Nguyen
Update Makefile to build Arria 10.
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/Makefile | 7 +--
arch/arm/mach-socfpga/arria10/Makefile | 7 +++
2 files changed, 12 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-socfpga/arria10/Makefi
From: Dinh Nguyen
Add minimal support for the Arria10 SoCDK.
Signed-off-by: Dinh Nguyen
---
board/altera/arria10-socdk/Kconfig | 18 ++
board/altera/arria10-socdk/Makefile | 9 +
board/altera/arria10-socdk/socfpga.c | 24
3 files changed, 51
From: Dinh Nguyen
Add config for the Arria10 SoC Development Kit.
Signed-off-by: Dinh Nguyen
---
include/configs/socfpga_arria10_socdk.h | 292
1 file changed, 292 insertions(+)
create mode 100644 include/configs/socfpga_arria10_socdk.h
diff --git a/include/c
From: Dinh Nguyen
Signed-off-by: Dinh Nguyen
---
arch/arm/Kconfig | 4 ++--
arch/arm/mach-socfpga/Kconfig | 10 ++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5ab0254..1d78e40 100644
--- a/arch/arm/Kconfig
+++ b
From: Dinh Nguyen
Add a defconfig file for Arria10, which does not include enabling SPL.
Signed-off-by: Dinh Nguyen
---
configs/socfpga_arria10_defconfig | 11 +++
1 file changed, 11 insertions(+)
create mode 100644 configs/socfpga_arria10_defconfig
diff --git a/configs/socfpga_arria
From: Dinh Nguyen
Add system manager defines for Arria10.
Signed-off-by: Dinh Nguyen
---
.../mach-socfpga/include/mach/system_manager_a10.h | 157 +
1 file changed, 157 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_a10.h
diff --git a/a
From: Dinh Nguyen
Add the base address map for Arria10.
Signed-off-by: Dinh Nguyen
---
.../include/mach/socfpga_a10_base_addrs.h | 45 ++
1 file changed, 45 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/socfpga_a10_base_addrs.h
diff --git a/
From: Dinh Nguyen
The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register,
not the mpumodrst. So the bank for these reset bits should be 1, not 0.
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 6 +++---
1 file changed, 3 insertions(+), 3
From: Dinh Nguyen
Update the L2 AUX CTRL settings for the SoCFPGA.
Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.
Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has th
From: Dinh Nguyen
We need "u-boot,dm-pre-reloc" in the socfpga_cyclone5_socdk.dts file in
order for the SPL to use SD/MMC.
Signed-off-by: Dinh Nguyen
---
arch/arm/dts/socfpga_cyclone5_socdk.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts
b/ar
From: Dinh Nguyen
s/L310_SHARED_ATT_OVERRIDE_ENABLE/PL310_SHARED_ATT_OVERRIDE_ENABLE
Signed-off-by: Dinh Nguyen
---
arch/arm/imx-common/cache.c | 2 +-
arch/arm/include/asm/pl310.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/imx-common/cache.c b/arch/arm/im
From: Dinh Nguyen
Update the L2 AUX CTRL settings for the SoCFPGA.
Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.
Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has th
From: Dinh Nguyen
Enable the able to save the environment variables when SD/MMC is used.
Signed-off-by: Dinh Nguyen
---
v4: Move ENV_IS_NOWHERE to the mcvevk board config file
v3: Only define ENV_IS_NOWHERE if env is not in MMC, NAND, FAT, and SPI_FLASH
v2: Move this option to be on a per-board
From: Dinh Nguyen
Enable the able to save the environment variables when SD/MMC is used.
Signed-off-by: Dinh Nguyen
---
v3: Only define ENV_IS_NOWHERE if env is not in MMC, NAND, FAT, and SPI_FLASH
v2: Move this option to be on a per-board basis
Add config for socfpga_cyclone5 and socfpga_a
From: Dinh Nguyen
commit "arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files"
renames the configs files, so we should update the MAINTAINERS' entry. At
the same time, update the email for Dinh Nguyen.
Signed-off-by: Dinh Nguyen
---
board/altera/arria5-socdk/MAINTAINERS | 4
From: Dinh Nguyen
Enable the able to save the environment variables when SD/MMC is used.
Signed-off-by: Dinh Nguyen
---
v2: Move this option to be on a per-board basis
Add config for socfpga_cyclone5 and socfpga_arria5
---
include/configs/socfpga_arria5_socdk.h | 4
include/configs/
From: Dinh Nguyen
Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and
socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA
board config files.
Suggested-by: Marek Vasut
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/Kconfig
From: Dinh Nguyen
Enable the able to save the environment variables when SD/MMC is used.
Signed-off-by: Dinh Nguyen
---
include/configs/socfpga_common.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 38ae763..f
From: Dinh Nguyen
Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV
based board. The board can boot from SD/MMC. Ethernet is also supported.
Signed-off-by: Dinh Nguyen
---
v2: add ethernet support
moved board files to board/terasic/de0-nano-soc/
associate everythin
From: Dinh Nguyen
Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV
based board. The board can boot from SD/MMC. Ethernet is a bit different
because it has a KSZ9031 PHY, so for now, ethernet doesn't quite work yet,
as a few patches are needed to support the PHY.
Signed-off
From: Dinh Nguyen
Fix build error for socfpga_cyclone5_defconfig:
board/altera/socfpga/wrap_sdram_config.c:245:26: error:
‘RW_MGR_MEM_NUMBER_OF_RANKS’ undeclared here (not in a function)
make[2]: *** [spl/board/altera/socfpga/wrap_sdram_config.o] Error 1
Signed-off-by: Dinh Nguyen
---
Hi Mare
From: Dinh Nguyen
This patch enables the SDRAM controller that is used on Altera's SoCFPGA
family. This patch configures the SDRAM controller based on a configuration
file that is generated from the Quartus tool, sdram_config.h.
Signed-off-by: Dinh Nguyen
---
v4: none
v3: none
v2: clean up from
From: Dinh Nguyen
Enable the Altera SDRAM driver for the SoCFPGA platform.
Signed-off-by: Dinh Nguyen
Acked-by: Marek Vasut
---
include/configs/socfpga_common.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index c
From: Dinh Nguyen
Hi,
This is v4 of the patch series that adds the DDR controller driver for
Altera's SoCFPGA platform.
v4:
- Further cleanup by removing comments that do not apply for Cyclone5.
- Removed more unused functions
Thanks,
Dinh Nguyen (3):
driver/ddr/altera: Add DDR driver for A
From: Dinh Nguyen
Enable the Altera SDRAM driver for the SoCFPGA platform.
Signed-off-by: Dinh Nguyen
---
include/configs/socfpga_common.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index cae744d..9b52050 100644
From: Dinh Nguyen
This patch enables the SDRAM controller that is used on Altera's SoCFPGA
family. This patch configures the SDRAM controller based on a configuration
file that is generated from the Quartus tool, sdram_config.h.
Signed-off-by: Dinh Nguyen
---
v2: clean up from comments from Pav
From: Dinh Nguyen
Hi,
This is V3 of patch series that adds the DDR controller driver for Altera's
SoCFPGA platform.
V3:
- Clean up to address comments from Marek for the calibration portion.
V2:
- Clean up to address comments from Pavel
Thanks,
Dinh Nguyen (3):
driver/ddr/altera: Add DDR d
From: Dinh Nguyen
Signed-off-by: Dinh Nguyen
---
doc/git-mailrc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/doc/git-mailrc b/doc/git-mailrc
index f0470e6..88fb3f9 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -64,7 +64,7 @@ alias rmobileuboot, iwamatsu
ali
From: Dinh Nguyen
Enable the Altera SDRAM driver for the SoCFPGA platform.
Signed-off-by: Dinh Nguyen
---
include/configs/socfpga_common.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index cae744d..9b52050 100644
From: Dinh Nguyen
Hi,
This is V2 of patch series that adds the DDR controller driver for Altera's
SoCFPGA platform.
V2:
- Clean up to address comments from Pavel
Thanks,
Dinh Nguyen (3):
driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
driver/ddr/altera/: Add the sdram cali
From: Dinh Nguyen
This patch enables the SDRAM controller that is used on Altera's SoCFPGA
family. This patch configures the SDRAM controller based on a configuration
file that is generated from the Quartus tool, sdram_config.h.
Signed-off-by: Dinh Nguyen
---
v2: clean up with comments from Pav
From: Dinh Nguyen
Enable the Altera SDRAM driver for the SoCFPGA platform.
Signed-off-by: Dinh Nguyen
---
include/configs/socfpga_common.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index cae744d..9b52050 100644
From: Dinh Nguyen
This patch enables the SDRAM controller that is used on Altera's SoCFPGA
family. This patch configures the SDRAM controller based on a configuration
file that is generated from the Quartus tool, sdram_config.h.
Signed-off-by: Dinh Nguyen
---
Makefile
From: Dinh Nguyen
Hi,
This is a resend of the patch series that adds the DDR controller driver for
Altera's SoCFPGA platform. This resend contains a new patch:
arm: socfpga: enable the Altera SDRAM controller driver
This new patch is necessary for the driver to build against
u-boot-socfpga/ma
From: Dinh Nguyen
Add a stub s_init function in the board file. The reason why the stub function
is needed is that most of the work is now being done in board_init_f(), there
is no need for the SPL to do anything s_init(). However, since lowlevel_init()
is still branching to s_init(), we need stu
From: Dinh Nguyen
"commit 0d13a0051b2c arm: socfpga: Sync Cyclone V DK PLL configuration"
mistakenly changed CONFIG_HPS_MAINPLLGRP_VCO_NUMER to 39, the correct
value should be 79.
Signed-off-by: Dinh Nguyen
---
board/altera/socfpga/pll_config.h | 2 +-
1 file changed, 1 insertion(+), 1 deletio
From: Dinh Nguyen
Hello,
The following 3 patches are updates to SPL patches that Marek has already
applied to his tree. I have split out the DDR driver patches into a separate
patch series to make it more convenient to review.
Thanks,
Dinh Nguyen (3):
arm: socfpga: spl: Add s_init stub
arm
From: Dinh Nguyen
Remap SDRAM to 0x0, and clear OCRAM's ECC in board_init_f().
Signed-off-by: Dinh Nguyen
Reviewed-by: Marek Vasut
---
v4: remove CONFIG_SPL_BUILD and add a comment
v3: Move the code from s_init to board_init_f
---
arch/arm/cpu/armv7/socfpga/spl.c | 29
From: Dinh Nguyen
This patch enables the SDRAM controller that is used on Altera's SoCFPGA
family. This patch configures the SDRAM controller based on a configuration
file that is generated from the Quartus tool, sdram_config.h.
Signed-off-by: Dinh Nguyen
---
Makefile
From: Dinh Nguyen
Hello,
The following 2 patches adds the DDR controller driver that is in the Altera
SoCFPGA platform. This driver is needed for the SPL on the platform.
Thanks,
Dinh Nguyen (2):
driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
driver/ddr/altera/: Add the sd
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