From: Dinh Nguyen <dingu...@opensource.altera.com>
Add config for the Arria10 SoC Development Kit.
Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
---
include/configs/socfpga_arria10_socdk.h | 292 ++++++++++++++++++++++++++++++++
1 file changed, 292 insertions(+)
create mode 100644 include/configs/socfpga_arria10_socdk.h
diff --git a/include/configs/socfpga_arria10_socdk.h
b/include/configs/socfpga_arria10_socdk.h
new file mode 100644
index 0000000..68aa736
--- /dev/null
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -0,0 +1,292 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
+#define __CONFIG_SOCFGPA_ARRIA10_H__
+
+#include <asm/arch/socfpga_a10_base_addrs.h>
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_PING
+
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
+
+#define CONFIG_SYS_TEXT_BASE 0xFFE00000
+/* using linker to check all image sections fit OCRAM */
+#define CONFIG_U_BOOT_BINARY_MAX_SIZE (200 * 1024)
+
+/*
+ * Stack and malloc setup
+ */
+/* IRQ stack */
+#define CONFIG_STACKSIZE_IRQ (1 << 10)
+/* FIQ stack */
+#define CONFIG_STACKSIZE_FIQ (1 << 10)
+/* SP location before relocation, must use scratch RAM */
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_TEXT_BASE
+/* Reserving 0x400 space at back of scratch RAM for debug info */
+#define CONFIG_SYS_INIT_RAM_SIZE (256 * 1024)
+/* Stack pointer at on-chip RAM, leave 16kB behind for page table */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - 0x4000)
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x8000
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * Kernel Info
+ */
+/* flat device tree */
+#define CONFIG_OF_LIBFDT
+/* skip updating the FDT blob */
+#define CONFIG_FDT_BLOB_SKIP_UPDATE
+/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
+#define CONFIG_SYS_BOOTMAPSZ (32 * 1024 * 1024)
+
+/*
+ * Environment setup
+ */
+#define CONFIG_ENV_SIZE 4096
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * Can't poll in semihosting; so turn off automatic boot command
+ */
+#define CONFIG_BOOTCOMMAND "run callscript; run mmcload;" \
+ "run set_initswstate; run mmcboot"
+
+/*
+ * arguments passed to the bootz command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#define CONFIG_SYS_DTB_ADDR 0x100
+#define MAX_DTB_SIZE_IN_RAM 0x7f00
+#if ((CONFIG_SYS_DTB_ADDR + MAX_DTB_SIZE_IN_RAM) > CONFIG_SYS_LOAD_ADDR)
+#error "MAX_DTB_SIZE_IN_RAM is too big. It will overwrite zImage in memory."
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=y\0" \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "fdtaddr=" __stringify(CONFIG_SYS_DTB_ADDR) "\0" \
+ "bootimage=zImage\0" \
+ "bootimagesize=0x600000\0" \
+ "fdtimage=socfpga_arria10_socdk.dtb\0" \
+ "fdtimagesize=" __stringify(MAX_DTB_SIZE_IN_RAM) "\0" \
+ "fdt_high=0x2000000\0" \
+ "mmcloadcmd=fatload\0" \
+ "mmcloadpart=1\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "qspiloadcs=0\0" \
+ "qspibootimageaddr=0x120000\0" \
+ "qspifdtaddr=0x100000\0" \
+ "qspiroot=/dev/mtdblock1\0" \
+ "qspirootfstype=jffs2\0" \
+ "mmcload=mmc rescan;" \
+ "${mmcloadcmd} mmc 0:${mmcloadpart} ${loadaddr} ${bootimage};" \
+ "${mmcloadcmd} mmc 0:${mmcloadpart} ${fdtaddr} ${fdtimage}\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "fpgabr 1;" \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+ "netboot=dhcp ${bootimage} ; " \
+ "tftp ${fdtaddr} ${fdtimage} ; run ramboot\0" \
+ "qspiload=sf probe ${qspiloadcs};" \
+ "sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize};" \
+ "sf read ${fdtaddr} ${qspifdtaddr} ${fdtimagesize};\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+ "fpgabr 1;" \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+ "nandload=nand read ${loadaddr} ${nandbootimageaddr} ${bootimagesize};"\
+ "nand read ${fdtaddr} ${nandfdtaddr} ${fdtimagesize}\0" \
+ "nandboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${nandroot} rw rootfstype=${nandrootfstype};"\
+ "fpgabr 1;" \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+ "bootcmd=" CONFIG_BOOTCOMMAND "\0" \
+ "u-boot_swstate_reg=0xffd0620c\0" \
+ "u-boot_image_valid=0x49535756\0" \
+ "fpga=0\0" \
+ "fpgadata=0x2000000\0" \
+ "fpgadatasize=0x700000\0" \
+ "scriptfile=u-boot.scr\0" \
+ "callscript=if fatload mmc 0:1 $fpgadata $scriptfile;" \
+ "then source $fpgadata; " \
+ "else " \
+ "echo Optional boot script not found. " \
+ "Continuing to boot normally; " \
+ "fi;\0"
+
+/*
+ * Environment setup
+ */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+#undef CONFIG_CMD_IMPORTENV
+
+/*
+ * Console setup
+ */
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define PHYS_SDRAM_1_SIZE 0x2000000
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+/* always write in 32 bit manner */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS
+#define CONFIG_SYS_NS16550_CLK 10000000
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * L4 OSC1 Timer 0
+ */
+#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
+#define CONFIG_TIMER_CLOCK_HZ 100000000
+#define CONFIG_TIMER_CLOCK_KHZ (CONFIG_TIMER_CLOCK_HZ/1000)
+#define CONFIG_SYS_TIMER_RATE 100000000
+
+/*
+ * L4 Watchdog
+ */
+#ifdef CONFIG_HW_WATCHDOG
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000
+#define CONFIG_DW_WDT_CLOCK_KHZ 25000
+#endif
+
+/*
+ * network support
+ */
+#define CONFIG_DESIGNWARE_ETH
+#ifdef CONFIG_DESIGNWARE_ETH
+#define CONFIG_NET_MULTI
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_DW_SEARCH_PHY
+#define CONFIG_PHY_GIGE
+#define CONFIG_DW_AUTONEG
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+/* phy */
+#define CONFIG_EPHY0_PHY_ADDR 7
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+#endif /* CONFIG_DESIGNWARE_ETH */
+
+
+/*
+ * MMC support
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */
+#define CONFIG_ENV_OFFSET 512/* just after the MBR */
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+/* Enable FAT write support */
+#define CONFIG_FAT_WRITE
+
+/* configure a clustsize smaller than the default 64k */
+#define CONFIG_FS_FAT_MAX_CLUSTSIZE 16384
+/* MMC support */
+#define CONFIG_SDMMC_BASE (SOCFPGA_SDMMC_ADDRESS)
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
+#define CONFIG_DWMMC
+#define CONFIG_SOCFPGA_DWMMC
+#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
+#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
+/* using smaller max blk cnt to avoid flooding the limited stack we have */
+#define CONFIG_SOCFPGA_DWMMC_BUS_HZ CONFIG_HPS_CLK_SDMMC_HZ
+#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4
+/* requird for dw_mmc driver */
+#define CONFIG_BOUNCE_BUFFER
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif /* CONFIG_MMC */
+
+/*
+ * NAND
+ */
+#ifdef CONFIG_NAND_DENALI
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_REGS_BASE 0xff200000
+#define CONFIG_SYS_NAND_DATA_BASE 0xff300000
+#define CONFIG_SYS_NAND_BASE 0xff400000
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* The ECC size which either 512 or 1024 */
+#define CONFIG_NAND_DENALI_ECC_SIZE (512)
+#endif /* CONFIG_NAND_DENALI */
+
+/*
+ * FPGA support
+ */
+#define CONFIG_FPGA
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_COUNT 1
+#define CONFIG_CMD_FPGA_LOADFS
+#endif /* __CONFIG_H */
--
2.6.2
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