RE: [EXT] Re: Was plain U-Boot affected by CVE-2023-39902?

It is same bug also resolved by 6039e0edc8540bd2a ("imx: hab:Simplify the mechanism"). NXP Downstream uses different implementation with upstream. Best regards, Ye Li > -Original Message- > From: Tom Rini > Sent: Monday, June 23, 2025 11:14 PM > To: Rolf Eik

[PATCH] imx93_evk: Fix wrong VDDQ voltage setting for LPDDR4x

The default PCA9451 BUCK2 volt is 0.6v for LPDDR4x VDDQ. The codes are actually used for reworking to LPDDR4 which needs VDDQ at 1.1v. So remove it to avoid LPDDR4x issue. Signed-off-by: Ye Li --- board/freescale/imx93_evk/spl.c | 5 - 1 file changed, 5 deletions(-) diff --git a/board

Re: i.MX8/9: question about unused DDR PHY trained CSR board array

Hi Ahmad, On 12/20/2024 2:12 PM, Ahmad Fatoum wrote: [You don't often get email from a.fat...@pengutronix.de. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] Hello Ye Li, On 20.12.24 02:58, Ye Li wrote: On 12/19/2024 6:27 PM, Ahmad Fatoum wrote: On 30.

Re: i.MX8/9: question about unused DDR PHY trained CSR board array

global csr. But we agree this global csr is confused and waste some memory. It is better to switch to the board csr. Best regards, Ye Li The way things are, this is either a bug or a missed space saving opportunity for U-Boot. Thanks, Peng.

Re: [PATCH 1/2] net: fec_mxc: Fix clk_ref rate on iMX93

Hi Fabio, Primoz, Peng, On 9/24/2024 10:56 AM, Peng Fan wrote: Subject: Re: [PATCH 1/2] net: fec_mxc: Fix clk_ref rate on iMX93 Hi, On 23. 09. 24 15:14, Peng Fan (OSS) wrote: From: Ye Li Because iMX93 has a internal 1/2 divider before clock input to network controller, so have to set

[PATCH v3] mtd: spi-nor: Fix chip erase timeout issue

") to set new timeout for chip erase. Fixes: b91a0822d752 ("mtd: spi-nor: Add CHIP_ERASE optimization") Signed-off-by: Ye Li --- Changes in v3: - Replace spi_nor_wait_till_ready Changes in v2: - use do_div for u64 - Keep the variables in reverse xmas-tree - Add kernel commit in

[PATCH v2] mtd: spi-nor: Fix chip erase timeout issue

") to set new timeout for chip erase. Fixes: b91a0822d752 ("mtd: spi-nor: Add CHIP_ERASE optimization") Signed-off-by: Ye Li --- Changes in v2: - use do_div for u64 - Keep the variables in reverse xmas-tree - Add kernel commit info drivers/mtd/spi/spi-nor-core.c | 21 +

Re: [PATCH] mtd: spi-nor: Fix chip erase timeout issue

On 9/11/2024 7:05 PM, Marek Vasut wrote: On 9/11/24 12:45 PM, Ye Li wrote: Chip erase support was added to spi_nor_erase, but the timeout for polling SR ready is not updated and still for sector erase. So the timeout value is not enough for chip erase on some NOR flash. Follow kernel

[PATCH] mtd: spi-nor: Fix chip erase timeout issue

i-nor: Add CHIP_ERASE optimization") Signed-off-by: Ye Li --- drivers/mtd/spi/spi-nor-core.c | 21 - 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index aea611fef523..338e5856337e 100644 --- a/d

Re: [PATCH v3] imx: ele_ahab: Add HUK derivation support

-> char seed[] Rebase on top of u-boot next arch/arm/include/asm/mach-imx/ele_api.h | 2 + arch/arm/mach-imx/ele_ahab.c| 31 ++ drivers/misc/imx_ele/ele_api.c | 77 + 3 files changed, 110 insertions(+) Reviewed-by: Ye Li diff --gi

Re: [PATCH] imx: ele_ahab: Add HUK derivation support

_derive_huk(u8 *key, size_t key_size, u8 *seed) +{ + struct udevice *dev = gd->arch.ele_dev; + struct ele_msg msg; + int msg_size = sizeof(struct ele_msg); + const size_t seed_size = 16; Please try to pass seed size as a parameter, not hard code it. So users can set different seed.

Re: [PATCH] imx: hab: Make imx_hab_is_enabled dependent on FIELD_RETURN

{ +struct imx_fuse_t { Please make the struct renaming a separate patch. Peng Fan, Ye Li, Could you please help review this patch? Thanks Can you take a look iMX8MP FIELD_RETURN fuse, I think it does not have 1 bit but 8 bits which requires to burn a sequence. Only when the bits sequence is

Re: [PATCH] imx: hab: Make imx_hab_is_enabled dependent on FIELD_RETURN

separate patch. Peng Fan, Ye Li, Could you please help review this patch? Thanks Can you take a look iMX8MP FIELD_RETURN fuse, I think it does not have 1 bit but 8 bits which requires to burn a sequence. Only when the bits sequence is matched, the field return can work. So checking the bit 0 is

Re: [PATCH] imx: hab: Make imx_hab_is_enabled dependent on FIELD_RETURN

Hi Paul, On 6/24/2024 8:09 PM, Fabio Estevam wrote: Hi Paul, On Fri, Jun 21, 2024 at 10:06 AM Paul Geurts wrote: -struct imx_sec_config_fuse_t { +struct imx_fuse_t { Please make the struct renaming a separate patch. Peng Fan, Ye Li, Could you please help review this patch? Thanks

[PATCH v2 2/2] arm: imx9: Call imx9_probe_mu for DM post in board_r

This event callback imx9_probe_mu needs to be called in board_r as well, because many ELE APIs depending on this MU probed Signed-off-by: Ye Li --- No changes in v2 arch/arm/mach-imx/imx9/soc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx

[PATCH v2 1/2] arm: imx9: Correct imx9_probe_mu prototype

Since the event callback imx9_probe_mu is re-defined, update its prototype. Signed-off-by: Ye Li --- Changes in v2: Fix imx93_var_som and phycore_imx93 as well arch/arm/include/asm/arch-imx9/mu.h | 2 +- board/freescale/imx93_evk/spl.c | 2 +- board/phytec/phycore_imx93/spl.c| 2

[PATCH v2] arm: imx9: Correct imx9_probe_mu prototype

Since the event callback imx9_probe_mu is re-defined, update its prototype. Signed-off-by: Ye Li --- Changes in v2: Fix imx93_var_som and phycore_imx93 as well arch/arm/include/asm/arch-imx9/mu.h | 2 +- board/freescale/imx93_evk/spl.c | 2 +- board/phytec/phycore_imx93/spl.c| 2

[PATCH] net: fec_mxc: Avoid enable regulator failure

Change to regulator_set_enable_if_allowed to avoid enable failure, in case same phy supply shared by multiple FEC controllers. Signed-off-by: Ye Li --- drivers/net/fec_mxc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index

[PATCH] arm: imx: Fix incorrect return value

The spl_spi_get_uboot_offs weak function is defined unsigned int. Signed-off-by: Ye Li --- arch/arm/mach-imx/image-container.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index c9455fe..35da0ae

[PATCH] thermal: imx_tmu: Fix TMU error on iMX8MQ

imx_tmu_arch_init does not implement for iMX8MQ, error is returned Signed-off-by: Ye Li --- drivers/thermal/imx_tmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c index 4721cfb..ca775e5 100644 --- a/drivers/thermal/imx_tmu.c +++ b

[PATCH] arm: imx9: Fix MMU map table overlap

The size for flexspi AHB buffer space is wrong, so correct it. Signed-off-by: Ye Li --- arch/arm/mach-imx/imx9/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 15e87b8..2117489 100644 --- a/arch/arm/mach

[PATCH 2/2] arm: imx9: Call imx9_probe_mu for DM post in board_r

This event callback imx9_probe_mu needs to be called in board_r as well, because many ELE APIs depending on this MU probed Signed-off-by: Ye Li --- arch/arm/mach-imx/imx9/soc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index

[PATCH 1/2] arm: imx9: Correct imx9_probe_mu prototype

Since the event callback imx9_probe_mu is re-defined, update its prototype. Signed-off-by: Ye Li --- arch/arm/include/asm/arch-imx9/mu.h | 2 +- board/freescale/imx93_evk/spl.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-imx9/mu.h b/arch

[PATCH] arm: imx: imx8m: Enable the SError exception

To work with commit 2f3c920(imx8m: workaround ROM serror), we need to enable the SError exception and install vector in SPL. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx8m/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b

RE: [EXT] AW: FIELD_RETURN on i.MX8MNANOLPD4 EVK

Hi Thomas, It is due to ARMV8_SPL_EXCEPTION_VECTORS not enabled by default in upstream. I will send a patch Best regards, Ye Li > -Original Message- > From: Thomas Schaefer > Sent: Thursday, January 11, 2024 9:40 PM > To: Ye Li ; Peng Fan (OSS) ; > 'u-boot@

RE: FIELD_RETURN on i.MX8MNANOLPD4 EVK

I think there is no particular SW support needed for FIELD_RETURN on 8MN. From what you described, you have moved the part from closed to FIELD_RETURN. So are you able to boot into SPL without signature? Best regards, Ye Li > -Original Message- > From: Peng Fan (OSS) > Sent:

RE: [EXT] Re: [PATCH v2] mmc: fsl_esdhc: Do not set UHS_CAPS based on CONFIG_MMC_UHS_SUPPORT

MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK

[PATCH] power: pmic: Add NXP PCA9451A PMIC support

PCA9451A uses similar BUCKs and LDO regulators as PCA9450B/C but has LDO2 and LDO3 removed. So reuse pca9450 PMIC and regulator driver and add new type for PCA9451A. Signed-off-by: Ye Li --- drivers/power/pmic/pca9450.c | 1 + drivers/power/regulator/pca9450.c | 11 ++- include

[PATCH] imx: spl_imx_romapi: Get and print boot stage

Get and print boot stage through ROM API in SPL Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/include/asm/mach-imx/sys_proto.h | 7 +++ arch/arm/mach-imx/spl_imx_romapi.c| 22 +- 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/arm

[PATCH 22/23] imx8ulp_evk: disable overflow of port0 for LPAV

-by: Ye Li Signed-off-by: Peng Fan --- board/freescale/imx8ulp_evk/lpddr4_timing.c | 2 +- board/freescale/imx8ulp_evk/lpddr4_timing_266.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c b/board/freescale/imx8ulp_evk

[PATCH 23/23] imx8ulp_evk: Clear data at fdt_addr_r before booting kernel

o the fdt header check in above case will not pass. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- board/freescale/imx8ulp_evk/imx8ulp_evk.c | 8 1 file changed, 8 insertions(+) diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c index b5

[PATCH 21/23] imx8ulp_evk: Update DDR ports arbitration for DCNANO underrun

To resolve DCNANO underrun issue, change the DDR Port 0 arbitration from round robin fashion to fixed priority level 1, while other ports are not assigned any priority, so they will be serviced in round robin fashion if there is no active request from Port 0. Signed-off-by: Ye Li Acked-by: Peng

[PATCH 17/23] misc: fuse: Lock 8ULP ECC-protected fuse when programming

does not need the setting. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- drivers/misc/sentinel/fuse.c | 22 +- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/sentinel/fuse.c index aa691d3..99342d3 100644 --- a/dr

[PATCH 18/23] ddr: imx: Update the ddr init flow on imx8ulp

From: Jacky Bai Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai Reviewed-by: Ye Li --- drivers/ddr/imx/imx8ulp/ddr_init.c | 55 +- 1 file changed, 43 insertions(+), 12 deletions(-) diff --git a/drivers/ddr/imx

[PATCH 15/23] imx: sentinel: Update S400 API get info message structure

Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/include/asm/mach-imx/s400_api.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h index cb6e393..5582ff1 100644 --- a/arch/arm/include/asm/mach-imx/s4

[PATCH 16/23] misc: fuse: Update fuse mapping for 8ULP S400 API

Since new 8ULP A1 S400 FW (v0.0.8-e329b760) can support to read more fuses: like PMU trim, Test flow/USB, GP1-5, GP8-10. Update the u-boot driver for the new mapping. Signed-off-by: Ye Li Reviewed-by: Peng Fan Reviewed-by: Alice Guo --- drivers/misc/sentinel/fuse.c | 10 ++ 1 file

[PATCH 20/23] imx8ulp_evk: Change to use DDR driver

Remove the DDR initialization codes from board and enable the iMX8ULP DDR driver. Signed-off-by: Ye Li --- arch/arm/mach-imx/imx8ulp/Kconfig | 1 + board/freescale/imx8ulp_evk/Makefile | 2 +- board/freescale/imx8ulp_evk/ddr_init.c | 207 - 3 files

[PATCH 14/23] imx: imx8ulp: Update clocks to meet max rate restrictions

594M PLL4 PFD2: 792M -> 316.8M NIC_AP:96M (ND) -> 192M, 48M (LD) -> 96M NIC_LPAV: 198 (ND) -> 192M, 99M (LD) -> 96M USDHC0:PLL3 PFD3 DIV1, 389M (OD), 194M (ND/LD) USDHC1:PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD) USDHC2:PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD) Signed-of

[PATCH 19/23] imx8ulp_evk: Update the DDR timing

From: Jacky Bai Update the dram timing to support PLL bypass mode for F1. Signed-off-by: Jacky Bai Reviewed-by: Ye Li --- board/freescale/imx8ulp_evk/lpddr4_timing.c | 204 ++-- 1 file changed, 102 insertions(+), 102 deletions(-) diff --git a/board/freescale

[PATCH 10/23] imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers

ned-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/cgc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index d240aba..104109e 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx

[PATCH 08/23] ddr: imx8ulp: Change DRAM timing save area to 0x20055000

To align with ARM trusted firmware's change, adjust DRAM timing save area to new position 0x20055000. So we can release the space since 0x2006c000 for the NOBITS region of ARM trusted firmware Signed-off-by: Ye Li Reviewed-by: Jacky Bai --- drivers/ddr/imx/imx8ulp/Kconfig | 2 +- 1

[PATCH 09/23] imx: imx8ulp: Reconfigure MRC3 for SRAM0 access

Some space in SRAM0 will be protected by S400 to allow RX SecPriv mode access only for boot purpose. Since SW will reuse the SRAM0 as SCMI buffer and SPL container loading buffer, need to reconfigure MRC3. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/rdc.c | 15

[PATCH 07/23] imx: imx8ulp: configure XRDC for DRAM access from S400

Need to add DRAM access permission for S400, as S400 needs to access it When SPL calls image authentication Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/rdc.c | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach

[PATCH 02/23] imx: imx8ulp: Get chip revision from Sentinel

In both SPL and u-boot, after probing the S400 MU, get the chip revision, lifecycle and UID from Sentinel. Update get_cpu_rev to use the chip revision not hard coded it for A0 Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 1 + arch/arm/include

[PATCH 13/23] imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 only

PDAC and MSC for SPL before DDR initialization. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/include/asm/arch-imx8ulp/rdc.h | 1 + arch/arm/mach-imx/imx8ulp/rdc.c | 41 + board/freescale/imx8ulp_evk/spl.c | 8 --- 3 files changed, 47

[PATCH 12/23] imx: imx8ulp: upower: make code cleaner

From: Peng Fan To clean the upower codes by aligning codes format, check err_code and add detail bits list for the memory magic number Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 90 +++ 1 file changed, 78 insertions

[PATCH 11/23] imx: imx8ulp: upower: replace magic number with macro

. So remove MIPI_CSI here, let linux power domain driver to runtime enable the power domain. Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 22 +- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx

[PATCH 06/23] imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completion

, u-boot can't access SEC SIM and FSB. Signed-off-by: Ye Li Reviewed-by: Jacky Bai --- arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 1 + arch/arm/include/asm/global_data.h| 3 + arch/arm/mach-imx/imx8ulp/soc.c | 104 ++ board/free

[PATCH 04/23] imx: imx8ulp: Set XRDC MRC4/5 for access DDR from APD

iMX8ULP A1 S400 ROM removes the setting for MRC4/5. So we have to set them in SPL to allow access to DDR from A35 and APD PER masters Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/rdc.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-imx

[PATCH 03/23] imx: imx8ulp: Limit the eMMC ROM API workaround to A0.1 part

Since A1 ROM has fixed the ROM API eMMC issue, we should only use the workaround for A0.1 part. Add a SOC revision check. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/soc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx

[PATCH 05/23] imx: imx8ulp: Remove the TRDC configure from A35

As M33 is responsible for TRDC configuration, the settings for A35 nonsecure world access and DMA0 access are moved to M33 image. So remove the codes to release TRDC and configure it. Just keep the configurations for reference. Signed-off-by: Ye Li Reviewed-by: Jacky Bai --- arch/arm/mach-imx

[PATCH 01/23] imx: imx8ulp: Fix MU device probe failure

Since latest DTS has added multiple MU nodes, using compatible string to find the device node is not proper. It finds the first node with the compatible string matched even the node is disabled. Signed-off-by: Ye Li --- arch/arm/mach-imx/imx8ulp/soc.c | 6 ++ 1 file changed, 2 insertions

[PATCH 00/23] Add i.MX8ULP A1 revision support

): imx: imx8ulp: upower: replace magic number with macro imx: imx8ulp: upower: make code cleaner imx8ulp_evk: disable overflow of port0 for LPAV Ye Li (18): imx: imx8ulp: Fix MU device probe failure imx: imx8ulp: Get chip revision from Sentinel imx: imx8ulp: Limit the eMMC ROM API

[PATCH] watchdog: ulp_wdog: only compile the code of DM driver when CONFIG_WDT=y

From: Alice Guo DM watchdog timer driver and non-DM driver exist in ulp_wdog.c at the same time. Add a compilation restriction that only compile the DM driver part when CONFIG_WDT=y. Signed-off-by: Alice Guo Reviewed-by: Ye Li --- drivers/watchdog/ulp_wdog.c | 2 ++ 1 file changed, 2

[PATCH] env: mmc: Fix offset issue for env save

Fix the issue in commit 46c9016 (env: mcc: Drop unnecessary #ifdefs) If CONFIG_SYS_REDUNDAND_ENVIRONMENT is not defined, the offset value becomes undetermined, so write env to unexpected offset. Signed-off-by: Ye Li --- env/mmc.c | 8 1 file changed, 4 insertions(+), 4 deletions

[PATCH 6/6] imx: ele_ahab: Remove OEM Secure World Closed print

The OEM Secure World Closed is not a valid lifecycle on iMX8ULP/iMX9. So remove it from lifecycle print. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/ele_ahab.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c

[PATCH 5/6] imx: ele_ahab: confirm lifecycle before closing the part

Before moving the lifecycle to OEM closed, confirm the lifecycle is OEM open, otherwise cancel to move forward the lifecycle. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/ele_ahab.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-imx/ele_ahab.c

[PATCH 3/6] imx: ahab: Move imx9 and imx8ulp AHAB support together

Use common file ele_ahab.c for i.MX9 and iMX8ULP AHAB support, since both of them use same sentinel ELE APIs Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 2 + arch/arm/include/asm/arch-imx9/imx-regs.h| 2 + arch/arm/mach-imx/Makefile

[PATCH 4/6] misc: sentinel: s400_api: Use new command request definitions

Remove legacy command definitions, change to use new ELE_xxx command request. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/include/asm/mach-imx/s400_api.h | 15 --- arch/arm/mach-imx/imx8ulp/rdc.c | 2 +- arch/arm/mach-imx/imx9/trdc.c| 2

[PATCH 2/6] imx93: ahab: Get and decode AHAB events

For ahab_status command, support to get and decode AHAB events Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/include/asm/mach-imx/s400_api.h | 99 +++ arch/arm/mach-imx/imx9/ahab.c| 286 --- 2 files changed, 359 insertions(+), 26

[PATCH 1/6] misc: sentinel: s400_api: Add get_events API

Add get_events API to retrieve any singular events that has occurred since the FW has started from sentinel Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/include/asm/mach-imx/s400_api.h | 2 ++ drivers/misc/sentinel/s400_api.c | 45 2 files

Re: [EXT] Re: [PATCH] ARM: dts: imx8mm-evk: Fix wrong PMIC device for new EVK board

Hi Marcel, On Tue, 2023-01-17 at 09:16 +, Marcel Ziswiler wrote: > Caution: EXT Email > > Hi Ye Li > > On Tue, 2023-01-17 at 13:34 +0800, Ye Li wrote: > > > > In commit 48ddafd (imx8mm_evk: Switch to new imx8mm evk board), > > the iMX8MM EVK support was

[PATCH] ARM: dts: imx8ulp-evk: Fix iomuxc issue

The property fsl,mux_mask is deleted by commit ed7bda5 (imx8ulp: synchronise device tree with linux). This causes the pinctrl driver not work on 8ULP, so fail to print any log. Signed-off-by: Ye Li --- arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch

[PATCH] ARM: dts: imx8mm-evk: Fix wrong PMIC device for new EVK board

defconfig, then cause SPL boot failure. Signed-off-by: Ye Li --- arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 +- arch/arm/dts/imx8mm-evk.dtsi| 127 +++- 2 files changed, 68 insertions(+), 63 deletions(-) diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm

Re: [EXT] [PATCH] clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock

pll2_200m", "sys_pll1_40m", > "sys_pll2_100m", > "sys_pll1_800m", > "sys_pll2_500m", "clk_ext4", > "audio_pll2_out" }; > @@ -324,6 +336,8

[PATCH v2] mtd: rawnand: mxs_nand: Fix use_minimum_ecc for spl driver

Because mxs_nand_spl driver does not support DM, to use the minimum ECC layout, it needs to handle the CONFIG_NAND_MXS_USE_MINIMUM_ECC. Signed-off-by: Ye Li Reviewed-by: Han Xu --- Changes in v2: - Use IS_ENABLED to replace #ifdef drivers/mtd/nand/raw/mxs_nand.c | 3 +++ 1 file changed, 3

Re: [EXT] [PATCH] ARM: imx: romapi: Repair FlexSPI NOR boot offset

On Thu, 2022-03-31 at 00:27 +0200, Marek Vasut wrote: > Caution: EXT Email > > On 3/29/22 11:56, Ye Li wrote: > > Hi, > > > > > > > > > > > > > > But once you want to upgrade the > > > > flash.bin, flexspi configurations wi

Re: [EXT] [PATCH] ARM: imx: romapi: Repair FlexSPI NOR boot offset

On Tue, 2022-03-29 at 11:01 +0200, Marek Vasut wrote: > Caution: EXT Email > > On 3/29/22 04:49, Ye Li wrote: > > Hi, > > > > > > > > > > > > > > If you change the ROM API driver, that will break our design. > > > > You &g

[PATCH] mtd: rawnand: mxs_nand: Fix use_minimum_ecc for spl driver

Because mxs_nand_spl driver does not support DM, to use the minimum ECC layout, it needs to handle the CONFIG_NAND_MXS_USE_MINIMUM_ECC. Signed-off-by: Ye Li --- drivers/mtd/nand/raw/mxs_nand.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd

Re: [EXT] [PATCH] ARM: imx: romapi: Repair FlexSPI NOR boot offset

On Mon, 2022-03-28 at 16:54 +0200, Marek Vasut wrote: > Caution: EXT Email > > On 3/28/22 08:54, Ye Li wrote: > > > > Hi Marek, > Hi, > > [...] > > > > > > > > > > > > > > 2. Update the u-boot.itb offset in imx8mp-u-bo

[PATCH] mtd: nand: mxs_nand_spl: Remove the page aligned access

andle the page unaligned offset, but the spl_simple_fit_read can't do it. spl_simple_fit_read requires the FIT location at page aligned offset. Hence, remove the nand_get_mtd overwrite function from mxs_nand_spl to use page unaligned read by driver. Signed-off-by: Ye Li --- drivers/mt

[PATCH] usb_hub: Set DM_FLAG_DEFAULT_PD_CTRL_OFF to usb_hub driver

controller. So once removed usb_hub, the power domain is power off before removing USB controller. Signed-off-by: Ye Li --- common/usb_hub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/usb_hub.c b/common/usb_hub.c index ba11a18..990993a 100644 --- a/common/usb_hub.c

Re: [EXT] [PATCH] ARM: imx: romapi: Repair FlexSPI NOR boot offset

Hi Marek, On Wed, 2022-03-23 at 22:16 +0100, Marek Vasut wrote: > Caution: EXT Email > > On 3/23/22 03:42, Ye Li wrote: > > > > Hi Marek, > Hi, > > > > > > > > > > > > > > > > > > > > diff --git a/arch/arm

Re: [EXT] [PATCH] ARM: imx: romapi: Repair FlexSPI NOR boot offset

Hi Marek, On Mon, 2022-03-21 at 15:59 +0100, Marek Vasut wrote: > Caution: EXT Email > > On 3/21/22 04:35, Ye Li wrote: > > > > Hi Marek, > Hi, > > > > > > > > > diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach- > > &g

Re: [EXT] [PATCH] ARM: imx: romapi: Repair FlexSPI NOR boot offset

tion or boot partition. If you changed to "image_offset + (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000", the address for flexspi becomes 0x59000 (= 0x1000 + 0x6 - 0x8000) Best regards, Ye Li > >  static int is_boot_from_stream_device(u32 boot) > -- > 2.34.1 >

Re: [EXT] Re: [PATCH] imx: Revert "imx: mx6ull: fix REFTOP_VBGADJ setting" and fix comments

Hi Michael, On Fri, 2022-03-11 at 15:01 +0100, Dario Binacchi wrote: > Caution: EXT Email > > Hi, > > On Fri, Mar 11, 2022 at 1:26 PM Ye Li wrote: > > > > > > Hi Michael, > > > > On Fri, 2022-03-11 at 08:57 +0100, Michael Nazzareno Trimarc

Re: [EXT] Re: GPMI NAND Regression on i.MX6S

gt; > > I see the same issue here with IMX6Q/DL GPMI NAND. > > > > If I re-flash the ubi within U-Boot (tftpboot $loadaddr rootfs.ubi > > && > > nand erase.part rootfs && nand write $loadaddr rootfs $filesize) I > > find that U-Boot can attach and mount the ubi fine but Linux will > > have > > issues > Interesting! This sounds like U-Boot and Linux somehow diverge in how > they handle the ECC data in OOB. I'm pretty confident that Linux does > things "correctly" and U-Boot should match what Linux does in this > case. > > Does the patch (revert of 616f03dabacb) I mentioned before "solve" > the > issue for your case, too? > > @Han, Ye, Peng: As you signed-off the mentioned commit, do you have > any > ideas for a fix? The dt nand driver will check "fsl,legacy-bch-geometry" property to use legacy bch. If this can't work for you in case you don't use DM driver, I prefer adding a config to select the legacy bch not reverting the patch.  Best regards, Ye Li > > Thanks > Frieder

[PATCH] imx8ulp: Disable SPL exception vector

Disable SPL exception vector which causes issue to ROM patch execution when SPL calling ROM API. Signed-off-by: Ye Li --- arch/arm/mach-imx/imx8ulp/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig index 963fc93

Re: [EXT] Re: [PATCH] imx: Revert "imx: mx6ull: fix REFTOP_VBGADJ setting" and fix comments

Hi Michael, On Fri, 2022-03-11 at 08:57 +0100, Michael Nazzareno Trimarchi wrote: > Caution: EXT Email > > Hi > > On Tue, Mar 8, 2022 at 7:42 AM Ye Li wrote: > > > > > > The change in commit c1af358 (imx: mx6ull: fix REFTOP_VBGADJ > > setting) > >

[PATCH] imx: Revert "imx: mx6ull: fix REFTOP_VBGADJ setting" and fix comments

b100 '101" - set REFTOP_VBGADJ[2:0] to 3'b101 '110" - set REFTOP_VBGADJ[2:0] to 3'b110 '111" - set REFTOP_VBGADJ[2:0] to 3'b111 Signed-off-by: Ye Li --- arch/arm/mach-imx/mx6/soc.c | 20 +--- 1 file changed, 9 insertions(+), 11 deletions

Re: [EXT] [PATCH] crypto/fsl: Fallback to SW sha1/256 is misaligned buffers

  sha1_csum_wd(pbuf, buf_len, pout, > CHUNKSZ_SHA1); > +   else > +   sha256_csum_wd(pbuf, buf_len, pout, > CHUNKSZ_SHA256); > +   return 0; How about adding “#ifdef CONFIG_SHA1” and “#ifdef CONFIG_SHA256” here ?  Then it can depend on users’ selection to determine the fallback Best regards, Ye Li > } > > size = ALIGN(buf_len, ARCH_DMA_MINALIGN); > -- > 2.25.1 >

Re: [PATCH v2 01/15] crypto/fsl: Add support for CAAM Job ring driver model

t;   * 1200 clocks per sample generates better entropy. >   */ > -static void kick_trng(int ent_delay, uint8_t sec_idx) > +static void kick_trng(int ent_delay, ccsr_sec_t *sec) >  { > - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem > *)SEC_ADDR(sec_idx); >   struct rng4tst _

Re: [PATCH v2 02/15] crypto/fsl: Add CAAM support for bkek, random number generation

On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote: > added api and descriptor for blob key encryption key(bkek) > generation. > added api for random number generation. > > Signed-off-by: Gaurav Jain > Signed-off-by: Ji Luo Reviewed-by: Ye Li Best regards, Ye Li >

Re: [PATCH v2 09/15] crypto/fsl: i.MX8: Enable Job ring driver model in SPL and U-Boot.

On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote: > i.MX8(QM/QXP) - added support for JR driver model. > sec is initialized based on job ring information processed > from device tree. > > Signed-off-by: Gaurav Jain > Signed-off-by: Horia Geantă Reviewed-by: Ye Li B

Re: [PATCH v2 08/15] i.MX8: Add crypto node in device tree

On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote: > i.MX8(QM/QXP) - updated device tree for supporting DM in SPL. > > disabled use of JR1 in SPL and uboot, as JR1 is reserved > for SECO FW. > > Signed-off-by: Gaurav Jain Reviewed-by: Ye Li Best regards, Ye Li > --

Re: [PATCH v2 07/15] i.MX7ULP: Enable Job ring driver model in U-Boot.

On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote: > added crypto node in device tree. > sec is initialized based on job ring information processed > from device tree. > > Signed-off-by: Gaurav Jain Reviewed-by: Ye Li Best regards, Ye Li > --- >  arch/arm/Kconfig

Re: [PATCH v2 06/15] i.MX7: Enable Job ring driver model in U-Boot.

On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote: > i.MX7D - added support for JR driver model. > > removed sec_init() call, sec is initialized based on > job ring information processed from device tree. > > Signed-off-by: Gaurav Jain Reviewed-by: Ye Li Best regards, Ye

Re: [PATCH v2 05/15] i.MX6: Enable Job ring driver model in U-Boot.

; + select ARCH_MISC_INIT >   Can you also enable the JR driver for MX6SABREAUTO, MX6SABRESD and MX6UL_9X9_EVK? Best regards, Ye Li >  config TARGET_MX6UL_ENGICAM >   bool "Support Engicam GEAM6UL/Is.IoT" > diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach- >

Re: [PATCH v2 04/15] crypto/fsl: i.MX8M: Enable Job ring driver model in SPL and U-Boot.

On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote: > i.MX8MM/MN/MP/MQ - added support for JR driver model. > sec is initialized based on job ring information processed > from device tree. > > Signed-off-by: Gaurav Jain Reviewed-by: Ye Li Best regards, Ye Li > --- &

Re: [PATCH v2 03/15] i.MX8M: crypto: updated device tree for supporting DM in SPL

On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote: > disabled use of JR0 in SPL and uboot, as JR0 is reserved > for secure boot. > > Signed-off-by: Gaurav Jain Reviewed-by: Ye Li Best regards, Ye Li > --- >  arch/arm/dts/imx8mm-evk-u-boot.dtsi  | 18

[PATCH] mtd: nand: mxs_nand_spl: Add nand_spl_adjust_offset

Since the mxs_nand_spl has implemented adjust read offset in nand_spl_load_image, so we don't need to check the bad block in nand_spl_adjust_offset. Directly return the offset to continue read by nand_spl_load_image. Signed-off-by: Ye Li --- drivers/mtd/nand/raw/mxs_nand_spl.c | 5 + 1

[PATCH 2/2] mmc: fix device_remove when HS400_ES is enabled

HS400_ES is missed when down grade to HS mode during device_remove the mmc device Signed-off-by: Ye Li --- drivers/mmc/mmc.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index a1fd533..3cb6fda 100644 --- a/drivers/mmc/mmc.c

[PATCH 1/2] mmc: fix switch issue with send_status disabled

When send_status is false or wait_dat0 is not supported, the switch function should not send CMD13 but directly return. Signed-off-by: Ye Li --- drivers/mmc/mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 8078a89..a1fd533

[PATCH] arm: imx8m: Fix pad DSE issue for i.MX8MM/MN/MP

According to 8MM/MN/MP reference manual, their pad registers only have 4 valid DSE values. And DSE2 and DSE4 are different with current definitions in iomux-v3.h. Fix the issue to align with manual. Signed-off-by: Ye Li Acked-by: Peng Fan --- arch/arm/include/asm/mach-imx/iomux-v3.h | 21

[PATCH] mmc: fsl_esdhc_imx: Fix clock disable issue

x27;t become ready (ACMD14 timeout) due to the clock is enabled during power cycle. Signed-off-by: Ye Li Reviewed-by: Haibo Chen --- drivers/mmc/fsl_esdhc_imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index aa

[PATCH] arm: dts: imx8mp: Delete default clocks for clock controller node

Since SPL has initialized clocks for bus and core. We don't need to set the default clocks for clock controller node. Signed-off-by: Ye Li --- arch/arm/dts/imx8mp-u-boot.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot

[PATCH 7/7] imx8mp_evk: Enable the DWC EQoS iMX driver

Enable the EQoS i.MX driver in defconfig, also enable the PHYLIB to facilitate the case that only has FEC enabled. Signed-off-by: Ye Li --- configs/imx8mp_evk_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index

[PATCH 6/7] imx8mp_evk: Delete noncached memory config

DWC EQOS driver has removed to use noncached memory, so delete the configuration from iMX8MP EVK head file. Signed-off-by: Ye Li --- include/configs/imx8mp_evk.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index a6569d5

[PATCH 5/7] imx8mp_evk: Remove EQoS PHY reset codes

Since we uses the DTS and PHY reset gpio in EQoS driver to do the reset, remove the duplicated codes from board file. Signed-off-by: Ye Li --- board/freescale/imx8mp_evk/imx8mp_evk.c | 19 --- 1 file changed, 19 deletions(-) diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c

[PATCH 4/7] imx8mp_evk: Fix incorrect cascade for FEC and EQOS setup

The setup functions should be independent for two ethernet controllers Signed-off-by: Ye Li --- board/freescale/imx8mp_evk/imx8mp_evk.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c

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