On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> disabled use of JR0 in SPL and uboot, as JR0 is reserved
> for secure boot.
>
> Signed-off-by: Gaurav Jain <gaurav.j...@nxp.com>
Reviewed-by: Ye Li <ye...@nxp.com>
Best regards,
Ye Li
> ---
> arch/arm/dts/imx8mm-evk-u-boot.dtsi | 18 +++++++++++++++++-
> arch/arm/dts/imx8mm.dtsi | 1 +
> arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 18 +++++++++++++++++-
> arch/arm/dts/imx8mn.dtsi | 1 +
> arch/arm/dts/imx8mp-evk-u-boot.dtsi | 18 +++++++++++++++++-
> arch/arm/dts/imx8mp.dtsi | 1 +
> arch/arm/dts/imx8mq.dtsi | 1 +
> 7 files changed, 55 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> index f200afac9f..3c2502cbba 100644
> --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2019 NXP
> + * Copyright 2019, 2021 NXP
> */
>
> #include "imx8mm-u-boot.dtsi"
> @@ -72,6 +72,22 @@
> u-boot,dm-spl;
> };
>
> +&crypto {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr0 {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr1 {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr2 {
> + u-boot,dm-spl;
> +};
> +
> &usdhc1 {
> u-boot,dm-spl;
> };
> diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
> index b142b80734..009999bf3a 100644
> --- a/arch/arm/dts/imx8mm.dtsi
> +++ b/arch/arm/dts/imx8mm.dtsi
> @@ -824,6 +824,7 @@
> compatible = "fsl,sec-v4.0-
> job-ring";
> reg = <0x1000 0x1000>;
> interrupts = <GIC_SPI 105
> IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> sec_jr1: jr@2000 {
> diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> index 1d3844437d..b462d24eb2 100644
> --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2019 NXP
> + * Copyright 2019, 2021 NXP
> */
>
> / {
> @@ -104,6 +104,22 @@
> u-boot,dm-spl;
> };
>
> +&crypto {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr0 {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr1 {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr2 {
> + u-boot,dm-spl;
> +};
> +
> &usdhc1 {
> u-boot,dm-spl;
> };
> diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi
> index edcb415b53..1820a5af37 100644
> --- a/arch/arm/dts/imx8mn.dtsi
> +++ b/arch/arm/dts/imx8mn.dtsi
> @@ -822,6 +822,7 @@
> compatible = "fsl,sec-v4.0-
> job-ring";
> reg = <0x1000 0x1000>;
> interrupts = <GIC_SPI 105
> IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> sec_jr1: jr@2000 {
> diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> index 2abcf1f03d..5415d5b617 100644
> --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2019 NXP
> + * Copyright 2019, 2021 NXP
> */
>
> #include "imx8mp-u-boot.dtsi"
> @@ -67,6 +67,22 @@
> u-boot,dm-spl;
> };
>
> +&crypto {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr0 {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr1 {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr2 {
> + u-boot,dm-spl;
> +};
> +
> &i2c1 {
> u-boot,dm-spl;
> };
> diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
> index c2d51a46cb..57b01c3a57 100644
> --- a/arch/arm/dts/imx8mp.dtsi
> +++ b/arch/arm/dts/imx8mp.dtsi
> @@ -624,6 +624,7 @@
> compatible = "fsl,sec-v4.0-
> job-ring";
> reg = <0x1000 0x1000>;
> interrupts = <GIC_SPI 105
> IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> sec_jr1: jr@2000 {
> diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
> index a44f729d0e..ecab44ca13 100644
> --- a/arch/arm/dts/imx8mq.dtsi
> +++ b/arch/arm/dts/imx8mq.dtsi
> @@ -955,6 +955,7 @@
> compatible = "fsl,sec-v4.0-
> job-ring";
> reg = <0x1000 0x1000>;
> interrupts = <GIC_SPI 105
> IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> sec_jr1: jr@2000 {
