takenly incorrectly detect RAM size, in particular 2 or 4
GB RAM on the 1GB device.
Tested-by: Ryan Walklin
Regards,
Ryan
On Mon, 15 Jul 2024, at 11:38 AM, Andre Przywara wrote:
> On Sun, 14 Jul 2024 20:20:44 +1200
> "Ryan Walklin" wrote:
>
> Hi Ryan,
>
> I consider the fact that the AXP209 and the AXP717 use the same I2C
> address a sheer coincidence, so would like to keep the code re
obj-$(CONFIG_AXP313_POWER) += axp313.o
> +obj-$(CONFIG_AXP717_POWER) += axp_spl.o
> obj-$(CONFIG_AXP809_POWER) += axp809.o
> obj-$(CONFIG_AXP818_POWER) += axp818.o
> endif
> --
> 2.25.1
Tested with RG35XX-H and RG35XX-Plus boards (Allwinner H700 with AXP717).
Confirmed both DCDC2 and DCDC3 are set correctly in SPL, allowing successful
DRAM init and boot.
Tested-by: Ryan Walklin
Regards,
Ryan
d with an H700-based board and u-boot at the 512-sector/256KB offset.
Tested-by: Ryan Walklin
Regards,
Ryan
[AXP806_ID] = axp806_regulators,
> [AXP809_ID] = axp809_regulators,
> diff --git a/include/axp_pmic.h b/include/axp_pmic.h
> index aabafc8501b..ae62ef0d76d 100644
> --- a/include/axp_pmic.h
> +++ b/include/axp_pmic.h
> @@ -33,6 +33,7 @@ enum {
> AXP221_ID,
> AXP223_ID,
> AXP313_ID,
> + AXP717_ID,
> AXP803_ID,
> AXP806_ID,
> AXP809_ID,
> --
> 2.35.8
Confirmed working on H700 board with AXP717 PMIC and LPDDR4 DRAM controller
(Anbernic RG35XX-H). Registers and voltage ranges confirmed from datasheet.
Reviewed-by: Ryan Walklin
Regards,
Ryan
;
> +
> + return pmic_bus_setbits(AXP717_OUTPUT_CTRL1, 1U << (dcdc_num - 1));
> +}
> +
> +int axp_set_dcdc1(unsigned int mvolt)
> +{
> + return axp_set_dcdc(1, mvolt);
> +}
> +
> +int axp_set_dcdc2(unsigned int mvolt)
> +{
> + return axp_set_dcdc(2, mvolt);
> +}
&
ts corresponding DT node.
Fix by adding missing RGMII internal delay modes to list of
fall-through cases so that when configured with modes "rgmii-id",
"rgmii-txid" or "rgmii-rxid", the internal delay registers get
updated correctly in vsc8531_vsc8541_clk_skew_config()
0
+ d: 0
diff --git a/tools/buildman/requirements.txt b/tools/buildman/requirements.txt
index a1efcb9d4b..4a31e69e4c 100644
--- a/tools/buildman/requirements.txt
+++ b/tools/buildman/requirements.txt
@@ -1,2 +1,3 @@
jsonschema==4.17.3
pyyaml==6.0
+yamllint==1.26.3
--
2.34.1
--
Ryan Eatmonreat...@ti.com
-
Texas Instruments, Inc. - LCPD - MGTS
> -Original Message-
> From: Dylan Hung
> Sent: Thursday, July 27, 2023 9:58 AM
> To: Ryan Chen ; ChiaWei Wang
> ; BMC-SW ;
> j...@jms.id.au; joe.hershber...@ni.com; rfried@gmail.com;
> u-boot@lists.denx.de
> Cc: kobedy...@gmail.com; Dylan Hung
> Subj
On Sat, Sep 16, 2023 at 03:14:58PM +0200, Ryan Lahfa wrote:
> Currently, it seems like the `initrd_filesize` was uninitialized for a
> while.
>
> This is particularly problematic when attempting to `zboot` with a
> initrd with a size coming from `label->initrd`, because it will
the boot.
This fixes the issue and I confirmed it enable me booting a U-Boot on
QEMU x86_64 q35 with NixOS kernel and initrds.
Signed-off-by: Ryan Lahfa
Cc: Tom Rini
Cc: Simon Glass
Cc: Bin Meng
Cc: Zhaofeng Li
Cc: Heinrich Schuchardt
Cc: Ramon Fried
Cc: Artem Lapkin
---
boot/pxe_utils.c
The reason for this is that initrd_filesize is constantly equal to zero
or more specifically, potentially uninitialized memory.
I believe this was introduced in
085cbdafca9c3d7bc2f27523a343f61db82f2ccb ("pxe: simplify label_boot()"),
diff here:
diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c
ind
The oe-core class for assembling the fitImage includes the vendor
sub-directory (with the / changed to _) in the config sections of
the fitImage. Our env var settings for chosing which section to
boot from needs to be updated to agree with the fitImage.
Signed-off-by: Ryan Eatmon
---
include
The oe-core class for assembling the fitImage includes the vendor
sub-directory (with the / changed to _) in the config sections of
the fitImage. Our env var settings for chosing which section to
boot from needs to be updated to agree with the fitImage.
Signed-off-by: Ryan Eatmon
---
include
Enable defconfigs relevant for storing env on SPI flash.
Signed-off-by: Ryan Chen
---
configs/evb-ast2600_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 3440062156..7c09e846ac 100644
--- a/configs/evb
> -Original Message-
> From: Simon Glass
> Sent: Tuesday, January 24, 2023 2:44 AM
> To: Ryan Chen
> Cc: Heiko Schocher ; BMC-SW ;
> u-boot@lists.denx.de
> Subject: Re: [PATCH v2 1/1] i2c:aspeed:support ast2600 i2c new register mode
> driver
>
> Hi Ryan,
Add i2c new register mode driver to support AST2600 i2c
new register mode. AST2600 i2c controller have legacy and
new register mode. The new register mode have global register
support 4 base clock for scl clock selection, and new clock
divider mode.
Signed-off-by: Ryan Chen
---
MAINTAINERS
The i2c driver have global register that i2c bus use
ofnode_get_parent to get parent register address.
Signed-off-by: Ryan Chen
---
arch/arm/dts/ast2600.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index 8d91eedc17..beabcf14f8
This series add AST2600 i2c new register set driver. The i2c new
register set have new clock divider option for more flexiable generation.
Changes in v3:
-modify uclass_get_device_by_driver to ofnode_get_parent.
-Add i2c reg address in dtsi node.
-fix up git config name from ryan_chen to Ryan
> -Original Message-
> From: Simon Glass
> Sent: Saturday, January 21, 2023 5:58 AM
> To: Ryan Chen
> Cc: Heiko Schocher ; BMC-SW ;
> u-boot@lists.denx.de
> Subject: Re: [PATCH v2 1/1] i2c:aspeed:support ast2600 i2c new register mode
> driver
>
> Hi Ryan,
Hello Simon,
Sorry, do you have time to check v2 patch?
Ryan Chen
> -Original Message-
> From: Ryan Chen
> Sent: Wednesday, January 11, 2023 2:53 PM
> To: Heiko Schocher ; Ryan Chen ;
> BMC-SW ; u-boot@lists.denx.de
> Subject: [PATCH v2 1/1] i2c:aspeed:suppo
Hello,
I resend the v2 version here
https://www.mail-archive.com/u-boot@lists.denx.de/msg460560.html
Ryan Chen
> -Original Message-
> From: Simon Glass
> Sent: Thursday, January 12, 2023 5:08 AM
> To: Ryan Chen
> Cc: Heiko Schocher ; BMC-SW ;
> u-
Hello Simon,
Thank your feedback.
> -Original Message-
> From: Simon Glass
> Sent: Tuesday, January 10, 2023 3:47 AM
> To: Ryan Chen
> Cc: Heiko Schocher ; BMC-SW ;
> u-boot@lists.denx.de
> Subject: Re: [PATCH 1/1] i2c:aspeed:support ast2600 i2c new r
> -Original Message-
> From: Dylan Hung
> Sent: Friday, November 11, 2022 3:30 PM
> To: Ryan Chen ; ChiaWei Wang
> ; j...@jms.id.au; Dylan Hung
> ; u-boot@lists.denx.de
> Cc: BMC-SW
> Subject: [PATCH 3/3] ram: ast2600: Align the RL and WL setting
>
> Use ma
> -Original Message-
> From: Dylan Hung
> Sent: Friday, November 11, 2022 3:30 PM
> To: Ryan Chen ; ChiaWei Wang
> ; j...@jms.id.au; Dylan Hung
> ; u-boot@lists.denx.de
> Cc: BMC-SW
> Subject: [PATCH 2/3] ram: ast2600: Improve ddr4 timing and signal quality
&
> -Original Message-
> From: Dylan Hung
> Sent: Friday, November 11, 2022 3:30 PM
> To: Ryan Chen ; ChiaWei Wang
> ; j...@jms.id.au; Dylan Hung
> ; u-boot@lists.denx.de
> Cc: BMC-SW
> Subject: [PATCH 1/3] ram: ast2600: Fix incorrect statement of the register
>
> -Original Message-
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 20, 2022 3:25 PM
> To: Ryan Chen ; BMC-SW
> ; Heiko Schocher
> Cc: u-boot@lists.denx.de; Cédric Le Goater
> Subject: [PATCH 08/10] i2c/aspeed: Add AST2600 compatible
>
> -Original Message-
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 20, 2022 3:25 PM
> To: Ryan Chen ; BMC-SW
> ; Heiko Schocher
> Cc: u-boot@lists.denx.de; Cédric Le Goater
> Subject: [PATCH 07/10] i2c/aspeed: Fix reset control
>
> -Original Message-
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 20, 2022 3:25 PM
> To: Ryan Chen ; BMC-SW
> ; Heiko Schocher
> Cc: u-boot@lists.denx.de; Cédric Le Goater
> Subject: [PATCH 06/10] reset/aspeed: Implement status
> -Original Message-
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 20, 2022 3:25 PM
> To: Ryan Chen ; BMC-SW
> ; Heiko Schocher
> Cc: u-boot@lists.denx.de; Cédric Le Goater
> Subject: [PATCH 05/10] ARM: dts: ast2600-evb: Add I2C device
> -Original Message-
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 20, 2022 3:25 PM
> To: Ryan Chen ; BMC-SW
> ; Heiko Schocher
> Cc: u-boot@lists.denx.de; Cédric Le Goater
> Subject: [PATCH 04/10] ARM: dts: ast2500-evb: Add I2C device
> -Original Message-
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 20, 2022 3:25 PM
> To: Ryan Chen ; BMC-SW
> ; Heiko Schocher
> Cc: u-boot@lists.denx.de; Cédric Le Goater
> Subject: [PATCH 03/10] ARM: dts: ast2600: Dsiable I2C nodes
> -Original Message-
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 20, 2022 3:25 PM
> To: Ryan Chen ; BMC-SW
> ; Heiko Schocher
> Cc: u-boot@lists.denx.de; Cédric Le Goater
> Subject: [PATCH 02/10] ARM: dts: ast2600: Add I2C reset pro
> -Original Message-
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 20, 2022 3:25 PM
> To: Ryan Chen ; BMC-SW
> ; Heiko Schocher
> Cc: Eddie James ; u-boot@lists.denx.de; Cédric Le
> Goater
> Subject: [PATCH 01/10] ARM: dts: ast2600: A
n Wed, 1 Jun 2022 at 16:10, Eddie James wrote:
> >
> > Set the pinctrl groups for each I2C bus. These are essential to I2C
> > operating correctly.
> >
> > Signed-off-by: Eddie James
>
> Reviewed-by: Joel Stanley
>
Reviewed-by: Ryan Chen
> > ---
>
> -Original Message-
> From: Joel Stanley
> Sent: Thursday, May 19, 2022 8:28 AM
> To: Eddie James ; Ryan Chen
> ; BMC-SW
> Cc: U-Boot Mailing List ; h...@denx.de
> Subject: Re: [PATCH] i2c: ast_i2c: Remove SCL direct drive mode
>
> On Wed, 11 May 2022 at
> -Original Message-
> From: Billy Tsai
> Sent: Wednesday, April 13, 2022 1:35 PM
> To: Ryan Chen ; ChiaWei Wang
> ; BMC-SW ;
> and...@aj.id.au; Billy Tsai ;
> u-boot@lists.denx.de
> Subject: [PATCH] gpio: aspeed: Fix incorrect offset of read back register.
>
Hello Andrew,
This patch series are ok, Please help add Reviewed-by: Ryan Chen
> -Original Message-
> From: Andrew Jeffery
> Sent: Wednesday, February 16, 2022 7:57 AM
> To: u-boot@lists.denx.de
> Cc: max...@google.com; ChiaWei Wang ;
> Ryan Chen ; Troy Le
> -Original Message-
> From: Dylan Hung
> Sent: Tuesday, November 2, 2021 1:42 PM
> To: u-boot@lists.denx.de; joe.hershber...@ni.com; rfried@gmail.com;
> Ryan Chen ; ChiaWei Wang
>
> Cc: BMC-SW
> Subject: [PATCH] drivers: net: add Aspeed MDIO driver
>
> -Original Message-
> From: ChiaWei Wang
> Sent: Thursday, September 16, 2021 2:10 PM
> To: u-boot@lists.denx.de
> Cc: Ryan Chen
> Subject: [PATCH] ARM: dts: ast2600: Make WDT by default disabled
>
> The WDT devices described in the general .dtsi file should
I see that Tim was working to add a non-platform specific implementation of the
ECDSA algorithm to u-boot back in February. I would like to use this feature
as well and was wondering if this work has been completed and where I can find
the patch.
Thanks,
Ryan
> -Original Message-
> From: ChiaWei Wang
> Sent: Monday, December 14, 2020 1:54 PM
> To: tr...@konsulko.com; u-boot@lists.denx.de; Ryan Chen
>
> Cc: BMC-SW
> Subject: [PATCH 7/7] configs: aspeed: Add defconfig for AST2600 EVB
>
> Add the default config
> -Original Message-
> From: ChiaWei Wang
> Sent: Monday, December 14, 2020 1:54 PM
> To: tr...@konsulko.com; u-boot@lists.denx.de; Ryan Chen
>
> Cc: BMC-SW
> Subject: [PATCH 6/7] aspeed: Add AST2600 platform support
>
> Add low level platform initialization
> -Original Message-
> From: ChiaWei Wang
> Sent: Monday, December 14, 2020 1:54 PM
> To: tr...@konsulko.com; u-boot@lists.denx.de; Ryan Chen
>
> Cc: BMC-SW
> Subject: [PATCH 5/7] ARM: dts: aspeed: Add AST2600 SoC support
>
> AST2600 is the 7th generation o
> -Original Message-
> From: ChiaWei Wang
> Sent: Monday, December 14, 2020 1:54 PM
> To: tr...@konsulko.com; u-boot@lists.denx.de; Ryan Chen
>
> Cc: BMC-SW
> Subject: [PATCH 4/7] reset: aspeed: Add AST2600 reset support
>
> Add controller reset support thro
> -Original Message-
> From: ChiaWei Wang
> Sent: Monday, December 14, 2020 1:54 PM
> To: tr...@konsulko.com; u-boot@lists.denx.de; Ryan Chen
>
> Cc: BMC-SW
> Subject: [PATCH 3/7] wdt: aspeed: Add AST2600 watchdog support
>
> AST2600 has 8 watchdog timers
> -Original Message-
> From: ChiaWei Wang
> Sent: Monday, December 14, 2020 1:54 PM
> To: tr...@konsulko.com; u-boot@lists.denx.de; Ryan Chen
>
> Cc: BMC-SW ; Dylan Hung
>
> Subject: [PATCH 2/7] ram: aspeed: Add AST2600 DRAM control support
>
> From: Dyl
> -Original Message-
> From: ChiaWei Wang
> Sent: Monday, October 12, 2020 10:36 AM
> To: tr...@konsulko.com; u-boot@lists.denx.de; max...@google.com
> Cc: Ryan Chen ; BMC-SW
>
> Subject: [v2 2/2] cosmetic: reset: ast2500: Rename driver and configs
>
> 1.
> -Original Message-
> From: ChiaWei Wang
> Sent: Monday, October 12, 2020 10:36 AM
> To: tr...@konsulko.com; u-boot@lists.denx.de; max...@google.com
> Cc: Ryan Chen ; BMC-SW
>
> Subject: [v2 1/2] reset: ast2500: Use SCU for reset control
>
> The System Contr
> -Original Message-
> From: ChiaWei Wang
> Sent: Tuesday, September 8, 2020 3:21 PM
> To: Ryan Chen ; max...@google.com;
> u-boot@lists.denx.de
> Cc: BMC-SW
> Subject: [PATCH 1/2] reset: ast2500: Use SCU for reset control
>
> The System Control Unit (SCU
> -Original Message-
> From: ChiaWei Wang
> Sent: Tuesday, September 8, 2020 3:21 PM
> To: Ryan Chen ; max...@google.com;
> u-boot@lists.denx.de
> Cc: BMC-SW
> Subject: [PATCH 2/2] cosmetic: reset: ast2500: Rename driver and configs
>
> 1. Rename AST250
> -Original Message-
> From: Dylan Hung
> Sent: Monday, September 7, 2020 4:25 PM
> To: Ryan Chen ; u-boot@lists.denx.de
> Cc: BMC-SW
> Subject: [PATCH 2/2] ram: add ddr4 dual x8 configuration
>
> the aspeed ddr sdram controller needs to know if the memory chip m
> -Original Message-
> From: Dylan Hung
> Sent: Monday, September 7, 2020 4:25 PM
> To: Ryan Chen ; u-boot@lists.denx.de
> Cc: BMC-SW
> Subject: [PATCH 1/2] ram: move aspeed ram driver into drivers/ directory
>
> to improve the maintainability. It is more
> -Original Message-
> From: Thirupathaiah Annapureddy
> Sent: Wednesday, September 2, 2020 4:43 AM
> To: u-boot@lists.denx.de
> Cc: Maxim Sloyko ; Marek Vasut ;
> thir...@microsoft.com; thir...@linux.microsoft.com; Tom Rini
> ; ChiaWei Wang ;
> Ryan Chen
> S
This patch series refactor the exiting ASPEED clock name define sync with Linux
kernel. And also add SPDX-License
V2 : modify patch 2/3 title form "aspeed:clock:" -> "clock:aspeed:" description
Ryan Chen (3):
cosmetic: aspeed: ast2500: Rename clock header
clock:
Modify SPDX-License for furture patch warning
Signed-off-by: Ryan Chen
---
arch/arm/dts/ast2500-u-boot.dtsi | 1 +
include/dt-bindings/clock/aspeed-clock.h | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u
Rename the ast2500-scu.h to aspeed-clock.h.
Signed-off-by: Ryan Chen
---
arch/arm/dts/ast2500-u-boot.dtsi| 2 +-
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c| 2 +-
drivers/clk/aspeed/clk_ast2500.c| 2 +-
include/dt
v2: modify title description aspeed:clock -> clock:aspeed
Use kernel include/dt-bindings/clock/aspeed-clock.h define
for clock driver.
Signed-off-by: Ryan Chen
---
arch/arm/dts/ast2500-u-boot.dtsi | 20 +++
drivers/clk/aspeed/clk_ast2500.c | 38 +++--
include
> -Original Message-
> From: Cédric Le Goater
> Sent: Saturday, August 29, 2020 4:46 PM
> To: Ryan Chen ; ChiaWei Wang
> ; BMC-SW ;
> lu...@denx.de; eaja...@linux.ibm.com; s...@chromium.org;
> u-boot@lists.denx.de; Joel Stanley
> Subject: Re: [PATCH 0/3] Rena
Use kernel include/dt-bindings/clock/aspeed-clock.h define
for clock driver.
Signed-off-by: Ryan Chen
---
arch/arm/dts/ast2500-u-boot.dtsi | 20 +++
drivers/clk/aspeed/clk_ast2500.c | 38 +++--
include/dt-bindings/clock/aspeed-clock.h | 68 ++--
3
Modify SPDX-License for furture patch warning
Signed-off-by: Ryan Chen
---
arch/arm/dts/ast2500-u-boot.dtsi | 1 +
include/dt-bindings/clock/aspeed-clock.h | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u
Rename the ast2500-scu.h to aspeed-clock.h.
Signed-off-by: Ryan Chen
---
arch/arm/dts/ast2500-u-boot.dtsi| 2 +-
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c| 2 +-
drivers/clk/aspeed/clk_ast2500.c| 2 +-
include/dt
This patch series refactor the exiting ASPEED clock name define sync
with Linux kernel. And also add SPDX-License
Ryan Chen (3):
cosmetic: aspeed: ast2500: Rename clock header
aspeed:clock: Sync with Linux kernel clock header define
cosmetic: aspeed: Modify for SPDX-License
arch/arm/dts
All driver is use clk dm model, will not use this function call.
Signed-off-by: Ryan Chen
---
arch/arm/dts/ast2500-u-boot.dtsi| 2 +-
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c| 2 +-
drivers/clk/aspeed/clk_ast2500.c| 2
Hi
> -Original Message-
> From: Thirupathaiah Annapureddy [mailto:thir...@linux.microsoft.com]
> Sent: Thursday, August 20, 2020 8:16 AM
> To: u-boot@lists.denx.de
> Cc: Maxim Sloyko ; Marek Vasut ;
> ChiaWei Wang ; Ryan Chen
>
> Subject: Re: [PATCH] arm: dts: f
On Mon, 6 Apr 2020 at 19:25, Peter Collingbourne wrote:
> On Mon, Apr 6, 2020 at 10:40 AM Ryan Harkin
> wrote:
>
>> Hi Peter,
>>
>> This looks good to me, but I have a quick question below.
>>
>> On Sat, 4 Apr 2020 at 03:58, Peter Collingbourne wrote:
>
x27;broken' part and replace it the board becomes functional again.
Is there something different about these parts that require a slightly
different u-boot configuration that could cause the Flash to function initially
but later become corrupt?
Best Regards,
Ryan J. Russell
Hardware Designer
A
This reverts commit fc04b923541d984b1544056fd3bfa8129d4e5aac where the
FVP DRAM configuration was added.
Signed-off-by: Ryan Harkin
---
arch/arm/Kconfig | 10 ---
board/armltd/vexpress64/Kconfig| 2 +-
board/armltd/vexpress64/MAINTAINERS| 5
configs
On Thu, 22 Aug 2019 at 13:10, Sudeep Holla wrote:
> On Thu, Aug 22, 2019 at 12:38:31PM +0100, Ryan Harkin wrote:
> > On Thu, 22 Aug 2019 at 02:25, Peng Fan wrote:
> >
> > > > Subject: [U-Boot] [PATCH] ARM: vexpress_*_defconfig: replace
> ear
On Thu, 22 Aug 2019 at 02:25, Peng Fan wrote:
> > Subject: [U-Boot] [PATCH] ARM: vexpress_*_defconfig: replace earlyprintk
> > with earlycon
> >
> > earlyprintk no longer works on arm64 platforms. Replace it with earlycon
> > which works fine.
> >
> > Cc
lieve that u-boot wasn’t booting my kernel.
Thank you very much, Bin and Andy, for your assistance with this. I appreciate
it.
Best,
Ryan
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ng stages of boot process.
>
>
>
> --
> With Best Regards,
> Andy Shevchenko
Andy,
This worked for me and I was able to see that the kernel was booting but was
unable to mount the rootfs. It also told me that my framebuffer isn’t being
initialized properly so I wasn’t see
> On Aug 9, 2019, at 12:00 PM, Bin Meng wrote:
>
> +Simon, Andy,
>
> Hi Ryan,
>
>> On Fri, Aug 9, 2019 at 11:52 PM Ryan Wilkins
>> wrote:
>>
>> Hello,
>>
>> I’m trying to get u-boot 2019.04 to execute the Linux 4.19.55 kernel from
&
.
Ryan Wilkins
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[1] Thanks for all of your help BTW - Peng, there's no way this would be
> working without you giving direction on how.
>
> Bryan O'Donoghue (2):
> drivers/crypto/fsl: assign job-rings to non-TrustZone
> warp7 : run sec_init for CAAM RNG
>
This series:
Tested-b
Hi Simon,
On 22 January 2018 at 00:29, Simon Glass wrote:
> Hi Ryan,
>
> On 19 January 2018 at 06:21, Ryan Harkin wrote:
> > Hi Stefan,
> >
> > Thanks for looking so quickly.
> >
> > On 19 January 2018 at 12:23, Stefan Agner
> wrote:
> >>
>
Hi Stefan,
Thanks for looking so quickly.
On 19 January 2018 at 12:23, Stefan Agner wrote:
> Hi Ryan,
>
>
> On 19.01.2018 10:53, Ryan Harkin wrote:
> > Add DTE mode support via Kconfig on the MXC uart.
>
> Make use of the driver model, there DTE is supporte
Add support to route the serial console on the NXP WaRP7 board
to UART6 and the mikroBus.
To use UART6 on the WaRP7 board, I add the following lines to
configs/warp7_defconfig:
+CONFIG_MXC_CONSOLE_NUM=6
+CONFIG_SERIAL_MXC_DTE_MODE=y
Signed-off-by: Ryan Harkin
Reviewed-by: Bryan O'Don
Add DTE mode support via Kconfig on the MXC uart.
Signed-off-by: Ryan Harkin
Reviewed-by: Bryan O'Donoghue
---
drivers/serial/Kconfig | 7 +++
drivers/serial/serial_mxc.c | 10 --
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/Kconfig b/dr
This small series adds support for using the console on UART6 on
the WaRP7 board.
The board retains current functionality: UART6 is not used by
default and needs it needs to be enabled in defconfig.
[PATCH 1/2] serial: mxc: support DTE mode
[PATCH 2/2] warp7: add support for console on UART6 and
Hello,
I have 2 chips which are 512mb each connected to the AM33xx processor.
I want to check if the base address is configured for each chip in
u-boot or kernel.
If it is configured in u-boot can anyone point me to where it is configured.
The problem i am facing is i dont if i need to do a
mte
, rather than
the enumeration CMD_RET_FAILURE (which is also 1).
Signed-off-by: Ryan Harkin
---
arch/arm/lib/semihosting.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c
index e32ad90..415ac89 100644
--- a/arch/arm/lib
Hello,
I am using AM43XX based board. The bootloader is divided into spl
u-boot (MLO) and u-boot.bin
I wanted to check what variables are shared between them. How does MLO
a seperate binary
share the boot mode and mmcdev to u-boot so that it can use the
appropriate mmcdev to find the
kernel.
tha
platform.
>
> Signed-off-by: Masahiro Yamada
> Acked-by: Michal Simek
> Acked-by: Stefan Roese
Acked-by: Ryan Harkin
Tested-by: Ryan Harkin
Tested on TC2, FVP Foundation and AEMv8 models and Juno R0, R1 and R2.
> ---
>
> Changes in v3:
> - Fix a typo in Kconf
_el2 and armv8_switch_to_el1. The input argument 4 will
>> be set to the right value, such as zero.
>>
>> Signed-off-by: Alison Wang
Thanks Alison, this removes the warning for me now and still boots
fine. I tested with Juno R0/1/2 and FVP Foundation and AEMv8 models.
Tested-b
On 13 January 2017 at 14:19, Mark Rutland wrote:
> On Thu, Jan 12, 2017 at 01:47:32PM +0000, Ryan Harkin wrote:
>> On 12 January 2017 at 12:25, Mark Rutland wrote:
>> > On Tue, Jan 10, 2017 at 06:50:19PM +, Jon Medhurst (Tixy) wrote:
>> >> On Tue, 2017-01-1
Hi Alison,
I'll wait for a new version based on Alex's feedback before I test.
The change looks like it should work, so I'm happy to wait, unless you feel
thjere is a need to test it sooner.
Thanks for the quick response.
Regards,
Ryan.
On 13 Jan 2017 08:16, "Alison Wan
On 12 January 2017 at 12:25, Mark Rutland wrote:
> On Tue, Jan 10, 2017 at 06:50:19PM +, Jon Medhurst (Tixy) wrote:
>> On Tue, 2017-01-10 at 18:34 +, Mark Rutland wrote:
>> > Looking at the git log for arch/arm64/boot/dts/arm, most updates are
>> > simply adding new descriptions, so a DTB
first time. I'm not sure which one is causing the warning in the
kernel, but I guess we need to reset x3 to zero before jumping to the
kernel?
I'm happy to test any fixes if you wish to send them to me.
Thanks,
Ryan.
On 10 November 2016 at 02:49, Alison Wang wrote:
> To support l
On 10 January 2017 at 16:58, Alexander Graf wrote:
> On 01/10/2017 05:47 PM, Ryan Harkin wrote:
>>
>> On 10 January 2017 at 16:35, Alexander Graf wrote:
>>>
>>> On 01/10/2017 05:31 PM, york sun wrote:
>>>>
>>>> On 01/10/2017 05:02 AM,
On 10 January 2017 at 16:35, Alexander Graf wrote:
> On 01/10/2017 05:31 PM, york sun wrote:
>>
>> On 01/10/2017 05:02 AM, Alexander Graf wrote:
>>>
>>> On 01/10/2017 01:58 PM, Michal Simek wrote:
U-Boot configured via DTB can use the same DTB for booting the kernel.
When OF_CONTROL
Hi Tom,
On 5 December 2016 at 17:13, Tom Rini wrote:
> On Mon, Dec 05, 2016 at 04:11:45PM +0000, Ryan Harkin wrote:
>
>> The ARM AEMv8 FVP model can be run in Aarch64 or Aarch32 mode. Aarch32
>> support is enable per-CPU when launching the model, eg:
>>
>> -C clust
.
Signed-off-by: Ryan Harkin
---
Changes since v1:
This single patch replaces my earlier RFC series of two patches, where
the first modified generic code and the other added a new variant.
After Tom's suggestion that I review the Raspberry PI code, my original
[RFC PATCH 1/2] has been dr
On 5 December 2016 at 15:14, Andre Przywara wrote:
> Hi,
>
> On 02/12/16 19:20, Tom Rini wrote:
>> On Fri, Dec 02, 2016 at 04:25:37PM +, Ryan Harkin wrote:
>>> On 2 December 2016 at 15:41, Tom Rini wrote:
>>>> On Fri, Dec 02, 2016 at 11:51:07AM +, Rya
On 2 Dec 2016 19:20, "Tom Rini" wrote:
>
> On Fri, Dec 02, 2016 at 04:25:37PM +, Ryan Harkin wrote:
> > On 2 December 2016 at 15:41, Tom Rini wrote:
> > > On Fri, Dec 02, 2016 at 11:51:07AM +, Ryan Harkin wrote:
> > >
> > >> I'
On 2 December 2016 at 15:41, Tom Rini wrote:
> On Fri, Dec 02, 2016 at 11:51:07AM +0000, Ryan Harkin wrote:
>
>> I've been working with Soby Mathew to get U-Boot booting on ARM's
>> AEMv8 FVP model in Aarch32 mode.
>>
>> Soby worked out what needed to
core.
This patch is co-authored with Soby Mathew .
Signed-off-by: Ryan Harkin
---
Makefile | 5 +
arch/arm/Kconfig | 6 ++
arch/arm/cpu/armv7/virt-v7.c | 2 ++
arch/arm/cpu/armv8/u-boot-spl.lds | 5 +
arch/arm/cpu/armv8/u-boot.lds
.
Signed-off-by: Ryan Harkin
---
arch/arm/Kconfig | 10 ++
board/armltd/vexpress64/Kconfig | 2 +-
configs/vexpress_aemv8a_aarch32_defconfig | 30 ++
include/configs/vexpress_aemv8a.h | 28 ++--
4
I've been working with Soby Mathew to get U-Boot booting on ARM's
AEMv8 FVP model in Aarch32 mode.
Soby worked out what needed to be changed and I'm refining the changes
into patches that can be built for both Aarch64 and Aarch32 mode.
There are two patches for discussion:
[RFC PATCH 1/2] Add Aa
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