I assume a disk image is more common than a PE-COFF image, at least
in U-Boot? Or is it not?
> @@ -544,6 +533,14 @@ static efi_status_t try_load_from_uri_path(struct
> efi_device_path_uri *uridp,
>
> source_buffer = (void *)image_addr;
> source_size = image_size;
> + } else if (detect_disk_image_type((void *)image_addr, image_size)) {
> + ret = prepare_loaded_image(lo_label, image_addr, image_size,
> +&loaded_dp, &blk);
> + if (ret != EFI_SUCCESS)
> + goto err;
> +
> + source_buffer = NULL;
> + source_size = 0;
> } else {
> log_err("Error: file type is not supported\n");
> ret = EFI_UNSUPPORTED;
--
Thanking You
Neha Malcom Francis
ass Bintool:
> Returns:
> True, assuming it completes without error
> """
> -args = ['sudo', 'apt', 'install', '-y', package]
> +args = ['sudo', 'apt-get', 'install', '-y', package]
> print('- %s' % ' '.join(args))
> tools.run(*args)
> return True
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
ny confusion on which parts are
> supported in the future, remove the GP tiboo3.bin builds from binman.
>
> Signed-off-by: Bryan Brattlof
> ---
Reviewed-by: Neha Malcom Francis
> arch/arm/dts/k3-am62a-phycore-som-binman.dtsi | 182
> +-
> 1 file ch
nd to avoid any confusion of which parts are
> supported in the future, remove the GP tiboot3.bin builds from binman.
>
> Signed-off-by: Bryan Brattlof
> ---
As per the discussion, in the hope that no more of these are "in the wild":
Reviewed-by: Neha Malcom Francis
Is the
_qb_restore(dram_timing, fsp_id);
>>> +
>>> + /* excute the firmware */
>>> + dwc_ddrphy_apb_wr(0xd, 0x0);
>>> + dwc_ddrphy_apb_wr(0xc0080, 0x3);
>>> + dwc_ddrphy_apb_wr(0xd0031, 0x1);
>>> + dwc_ddrphy_apb_wr(0xd, 0x1);
>>> + dwc_ddrphy_apb_wr(0xd0099, 0x9);
>>> + dwc_ddrphy_apb_wr(0xd0099, 0x1);
>>> + dwc_ddrphy_apb_wr(0xd0099, 0x0);
>>> +
>>> + /* Wait for the quick boot firmware to complete */
>>
>> Is there a special firmware for this quick boot firmware?
>
> Yes.
>
>>
>> Please explain the details. It is not clear why or how someone should
>> enable this QuickBoot feature.
>
> I think needs to use B0 chip to use this feature. I could
> add more information in V2.
Also please add more information on the flow, I see you use the binman
symbol from the image to grab the offset of this Quick Boot f/w. Please
add the flow as to what is the expectation of your boot image as well.
>
> Regards
> Peng.
--
Thanking You
Neha Malcom Francis
9ecc24853f228b760229572e73aa48
> 100644
> --- a/drivers/ddr/imx/phy/ddrphy_utils.c
> +++ b/drivers/ddr/imx/phy/ddrphy_utils.c
> @@ -184,6 +184,6 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
> }
> }
>
> -void ddrphy_init_read_msg_block(enum fw_type type)
> +__weak void ddrphy_init_read_msg_block(enum fw_type type)
> {
> }
>
--
Thanking You
Neha Malcom Francis
le.
> /* Step14: Enable AXI ports by programming */
> reg32_write(DDRC_PCTRL_0(0), 0x1);
> /* Step15: Disable quasi-dynamic programming */
>
--
Thanking You
Neha Malcom Francis
K3 Inline ECC mechanism can support up to 3 regions of inline ECC, add
this support for single controller.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/k3-ddrss/k3-ddrss.c | 125 +---
1 file changed, 83 insertions(+), 42 deletions(-)
diff --git a/drivers/ram
The existing approach does not account for interleaving in the DDRs when
setting up regions. There is support for MSMC to calculate the regions
for each DDR, so modify k3_ddrss_probe to set the regions accordingly
for multi-DDR systems.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/k3
Add support for calculation of the protected regions for each DDR in
multi-DDR systems. Since MSMC is the parent node of the individual DDRs
as well as responsible for their interleaving, it only makes sense for
MSMC to contain the logic for dividing the regions.
Signed-off-by: Neha Malcom
In K3 multi-DDR systems, the MSMC is responsible for the interleave
mechanism across all the DDR controllers. Add support for MSMC to obtain
the number of controllers it's responsible for using the DT.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/k3-ddrss/k3-ddrss.c | 8
1
As we increase the functionalities that the K3 DDRSS sub-system support,
it is becoming more evident that the same logic cannot apply to both
single as well as multiple DDR controller devices. Add
CONFIG_K3_MULTI_DDR to be used to differentiate between the two.
Signed-off-by: Neha Malcom Francis
: protected@9e78 {
device_type = "ecc";
reg = <0x9e78 0x008>;
bootph-all;
};
Signed-off-by: Neha Malcom Francis
---
drivers/ram/k3-ddrss/k3-ddrss.c | 55 +++--
1 file changed, 52 insertions(+), 3 deletions(-)
diff --git
The reserved space needed for storing the parity remains the same no
matter the size of the region that is being protected. Add this as a
comment for better code understanding.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/k3-ddrss/k3-ddrss.c | 5 +
1 file changed, 5 insertions
To prevent checkpatch warning once we start using this macro more
frequently, shorten the length of it.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/k3-ddrss/k3-ddrss.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3
Let ecc_regions[x].start reflect the start of the ECC region in terms of
DDR addressing rather than system addressing. This will make it easier
to extend the usage of the same ecc_regions structure for multi-DDR
systems as well.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/k3-ddrss/k3
eader file since it created warnings (Wadim)
- Minor changes not affecting logic of the patch, but cleaning it up (Udit)
- Rebased on top of latest master
- Added support for multiple partial inline ECC regions (note that this
support is only for single DDR controllers and not multi-DDR yet)
Neha M
k3-j721s2-binman.dtsi | 6 +++---
> arch/arm/dts/k3-j722s-binman.dtsi | 4 ++--
> arch/arm/dts/k3-j784s4-binman.dtsi | 6 +++---
> 12 files changed, 34 insertions(+), 34 deletions(-)
>
[...]
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
gt; };
>
> +#ifdef CONFIG_SPL
> /* Generation in a static way */
> itb {
> filename = U_BOOT_ITB_FILENAME;
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
gt;clk_usb);
>> diff --git a/drivers/power/domain/imx8mp-mediamix.c
>> b/drivers/power/domain/imx8mp-mediamix.c
>> index
>> 78c32ca3d3a87febdefd5d128d39d817674b8d32..504c22f7d3631363d76eb21e43afd854258d4ea5
>> 100644
>> --- a/drivers/power/domain/imx8mp-mediamix.c
>> +++ b/drivers/power/domain/imx8mp-mediamix.c
>> @@ -143,9 +143,13 @@ static int imx8mp_mediamix_bind(struct udevice *dev)
>>
>> static int imx8mp_mediamix_probe(struct udevice *dev)
>> {
>> +struct power_domain_plat *plat = dev_get_uclass_plat(dev);
>> struct imx8mp_mediamix_priv *priv = dev_get_priv(dev);
>> int ret;
>>
>> +/* Definitions are in imx8mp-power.h */
>> +plat->subdomains = 9;
>> +
>> priv->base = dev_read_addr_ptr(dev);
>>
>> ret = clk_get_by_name(dev, "apb", &priv->clk_apb);
>>
>
--
Thanking You
Neha Malcom Francis
gt;dtr)
> - txlen += txlen & 1;
> -
> if (priv->dtr)
> opcode = op->cmd.opcode >> 8;
> else
After reading [0], makes sense.
Reviewed-by: Neha Malcom Francis
[0]
https://lore.kernel.org/u-boot/174963a1-bf6e-4e54-9946-bf3c42a72...@amd.com/
--
Thanking You
Neha Malcom Francis
Trigger all tests of PBIST and LBIST using appropriate calls to set the
core under test (MAIN R5 2_0) to it's required state.
Signed-off-by: Neha Malcom Francis
---
No change since v4
arch/arm/mach-k3/j784s4/j784s4_init.c | 52 +++
1 file changed, 52 insertions(+)
Add a driver for the BIST module that support triggering of both PBIST
(Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant
operations and functions that would be required for an end user to
trigger the tests.
Signed-off-by: Neha Malcom Francis
---
No change since v4
drivers
-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/lbist.html#introduction
[3]
https://lore.kernel.org/all/175205725858.918402.3771835070085533874.b4...@ti.com/
Neha Malcom Francis (2):
drivers: misc: k3_bist: Add K3 BIST driver
arm: mach-k3: j784s4_init: Trigger LBIST and PBIST on
Hi Bryan
On 07/07/25 22:06, Bryan Brattlof wrote:
> On July 4, 2025 thus sayeth Neha Malcom Francis:
>> Move to using the latest generated RM YAML configuration files generated
>> by the K3 Resource Partitioning Tool which updates them to have standard
>> formatting with r
Hi Udit
On 02/07/25 19:44, Kumar, Udit wrote:
> Hello Neha,
>
> Thanks for updating these yaml
>
> On 7/2/2025 4:25 PM, Neha Malcom Francis wrote:
>> Latest update to the K3 Resource Partitioning Tool updates the YAML
>> configuration files to have standard
--
> base-commit: 59e6462d7c08eeba744afa0f17846c398b8ef9e1
> change-id: 20250625-doc-ti-am69-d20d1529f376
>
> Best regards,
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
On 09/06/25 17:56, Manorit Chawdhry wrote:
> Hi Neha,
>
> On 15:57-20250609, Neha Malcom Francis wrote:
>> Trigger all tests of PBIST and LBIST using appropriate calls to set the
>> core under test (MAIN R5 2_0) to it's required state.
>>
>> Signed-off-by: Ne
Hi Manorit
On 09/06/25 17:56, Manorit Chawdhry wrote:
> Hi Neha,
>
> On 15:57-20250609, Neha Malcom Francis wrote:
>> Add a driver for the BIST module that support triggering of both PBIST
>> (Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant
>> op
Add DT node for PBIST_14 that is responsible for triggering the PBIST
self-tests for the MAIN_R5_2_x cores.
Signed-off-by: Neha Malcom Francis
---
Changes since v3:
- move from ti,bist-under-test to ti,sci-dev-id
.../src/arm64/ti/k3-j784s4-j742s2-main-common.dtsi| 11 +++
1 file
Trigger all tests of PBIST and LBIST using appropriate calls to set the
core under test (MAIN R5 2_0) to it's required state.
Signed-off-by: Neha Malcom Francis
---
No change since v3
arch/arm/mach-k3/j784s4/j784s4_init.c | 52 +++
1 file changed, 52 insertions(+)
Add a driver for the BIST module that support triggering of both PBIST
(Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant
operations and functions that would be required for an end user to
trigger the tests.
Signed-off-by: Neha Malcom Francis
---
Changes since v2 and v3:
- code
-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/pbist.html#introduction
[2]
https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/lbist.html#introduction
Neha Malcom Francis (3):
drivers: misc
On 05/06/25 11:43, Moteen Shah wrote:
> Hey Neha,
>
> On 03/06/25 11:43, Neha Malcom Francis wrote:
>> On 28/05/25 13:35, Moteen Shah wrote:
>>> Introduce response and request structs to receive and request
>>> information regarding DM version, etc from TI SCI.
&
void disable_linefill_optimization(void);
> void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size);
> int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr);
> void k3_sysfw_print_ver(void);
> +void k3_dm_print_ver(void);
> void spl_enable_cache(void);
> void mmr_unlock(uintptr_t base, u32 partition);
> bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
791,7 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
> fwl_ops->get_fwl_region = ti_sci_cmd_get_fwl_region;
> fwl_ops->change_fwl_owner = ti_sci_cmd_change_fwl_owner;
>
> + fw_ops->get_dm_version = ti_sci_cmd_get_dm_version;
> fw_ops->query_dm_cap = ti_sci_cmd_query_dm_cap;
> }
>
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
f (IS_ENABLED(CONFIG_ARM64))
> + k3_dm_print_ver();
> }
>
> static void k3_mem_init(void)
> diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c
> b/arch/arm/mach-k3/j784s4/j784s4_init.c
> index 787cf6261e4..ccf29810849 100644
> --- a/arch/arm/mach-k3/j784s4/j784s4_init.c
> +++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
> @@ -208,6 +208,10 @@ void k3_spl_init(void)
>
> /* Output System Firmware version info */
> k3_sysfw_print_ver();
> +
> + /* Output DM Firmware version info */
> + if (IS_ENABLED(CONFIG_ARM64))
> + k3_dm_print_ver();
> }
>
> void k3_mem_init(void)
--
Thanking You
Neha Malcom Francis
ti_sci_rm_core_ops *rm_core_ops = &ops->rm_core_ops;
> struct ti_sci_proc_ops *pops = &ops->proc_ops;
> struct ti_sci_rm_ringacc_ops *rops = &ops->rm_ring_ops;
> @@ -2694,6 +2737,8 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
> fwl_o
; int (*query_dm_cap)(struct ti_sci_handle *handle,
> u64 *dm_cap);
> + int (*get_dm_version)(struct ti_sci_handle *handle,
> + struct ti_sci_dm_version_info *get_dm_version);
> };
>
> #define TI_SCI_MSG_FLAG_FW_CAP_DM0x100
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
Processor specific operations.
> *
> @@ -609,6 +620,7 @@ struct ti_sci_ops {
> struct ti_sci_dev_ops dev_ops;
> struct ti_sci_clk_ops clk_ops;
> struct ti_sci_core_ops core_ops;
> + struct ti_sci_firmware_ops fw_ops;
> struct ti_sci_proc_ops proc_ops;
> struct ti_sci_rm_core_ops rm_core_ops;
> struct ti_sci_rm_ringacc_ops rm_ring_ops;
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
artitions=name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}
> +
> rproc_fw_binaries= 0 /lib/firmware/am62a-mcu-r5f0_0-fw 1
> /lib/firmware/am62a-c71_0-fw
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
combined;
> dm-data;
> + core-opts = <2>;
> sysfw-inner-cert;
> keyfile = "custMpk.pem";
> sw-rev = <1>;
> @@ -68,6 +69,7 @@
> <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
> combined;
> dm-data;
> + core-opts = <2>;
> sysfw-inner-cert;
> keyfile = "custMpk.pem";
> sw-rev = <1>;
> @@ -117,6 +119,7 @@
> <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
> combined;
> dm-data;
> + core-opts = <2>;
> content-sbl = <&u_boot_spl_unsigned>;
> load = <0x41c0>;
> content-sysfw = <&ti_fs_gp>;
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
c71_0-fw 9
> /lib/firmware/j742s2-c71_1-fw 10 /lib/firmware/j742s2-c71_2-fw
> +rproc_fw_binaries= 1 /lib/firmware/j742s2-mcu-r5f0_1-fw 2
> /lib/firmware/j742s2-main-r5f0_0-fw 3 /lib/firmware/j742s2-main-r5f0_1-fw 4
> /lib/firmware/j742s2-main-r5f1_0-fw 5 /lib/firmware/j742s2-main
+
> /* Make sure Local reset is asserted. Redundant? */
> reset_assert(&core->reset);
> +
> + ti_sci_proc_release(&core->tsp);
> }
>
> ret = k3_r5f_rproc_configure(core);
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
();
> }
> diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c
> b/arch/arm/mach-k3/j784s4/j784s4_init.c
> index 787cf6261e4..2756accbe12 100644
> --- a/arch/arm/mach-k3/j784s4/j784s4_init.c
> +++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
> @@ -206,6 +206,13 @@ void k3_spl_init(void)
>
> writel(AUDIO_REFCLK1_DEFAULT,
> (uintptr_t)CTRL_MMR_CFG0_AUDIO_REFCLK1_CTRL);
>
> + /* Shutdown MCU_R5 Core 1 in Split mode at A72 SPL Stage */
> + if (IS_ENABLED(CONFIG_ARM64)) {
> + ret = shutdown_mcu_r5_core1();
> + if (ret)
> + printf("Unable to shutdown MCU R5 core 1, %d\n", ret);
> + }
> +
> /* Output System Firmware version info */
> k3_sysfw_print_ver();
> }
--
Thanking You
Neha Malcom Francis
gt; --- a/arch/arm/mach-k3/include/mach/j784s4_hardware.h
> +++ b/arch/arm/mach-k3/include/mach/j784s4_hardware.h
> @@ -41,19 +41,20 @@
>
> #define J784S4_DEV_MCU_RTI0 367
> #define J784S4_DEV_MCU_RTI1 368
> -#define J784S4_DEV_MCU_ARMSS0_CPU0 346
> -#define J784S4_DEV_MCU_ARMSS0_CPU1 347
>
> static const u32 put_device_ids[] = {
> J784S4_DEV_MCU_RTI0,
> J784S4_DEV_MCU_RTI1,
> };
>
> +#endif
> +
> +#define J784S4_DEV_MCU_ARMSS0_CPU0 346
> +#define J784S4_DEV_MCU_ARMSS0_CPU1 347
> +
> static const u32 put_core_ids[] = {
> J784S4_DEV_MCU_ARMSS0_CPU1,
> J784S4_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
> };
>
> -#endif
> -
> #endif /* __ASM_ARCH_J784S4_HARDWARE_H */
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
clude/mach/am62_hardware.h | 19 +
> arch/arm/mach-k3/include/mach/hardware.h | 1 +
> 4 files changed, 70 insertions(+)
>
--
Thanking You
Neha Malcom Francis
4 +163,5 @@ U_BOOT_DRIVER(sandbox_scmi_devices) = {
> .priv_auto = sizeof(struct sandbox_scmi_device_priv),
> .remove = sandbox_scmi_devices_remove,
> .probe = sandbox_scmi_devices_probe,
> + .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
> };
[...]
Thanks for working on this quickly, I've booted it on j784s4-evm and
works fine! And I am good with this approach using subdomains.
Tested-by: Neha Malcom Francis
(on j784s4-evm)
--
Thanking You
Neha Malcom Francis
> "envboot=mmc dev ${mmcdev}; " \
> "if mmc rescan; then " \
> "echo SD/MMC found on device ${mmcdev};" \
Are there any other boards that use .h instead of .env other than AM57x?
Would they break with this change?
--
Thanking You
Neha Malcom Francis
erfaces, as they have a similar pattern as on k3 platform: a
> single power domain node and one cell for figuring out which PD to
> enable.
>
> The uclass does not save any data, so I don't have an immediate fix to
> propose. Let me dig a bit more into that and find a solution.
>
Thanks!
Meanwhile, could we revert this patch to keep the platforms from breaking?
> Thanks,
> Miquèl
--
Thanking You
Neha Malcom Francis
er_domain *power_domain)
>> +static inline int power_domain_off_lowlevel(struct power_domain
>> *power_domain)
>> {
>> return -ENOSYS;
>> }
>> #endif
>>
>> +/**
>> + * power_domain_off - Disable power to a power domain (ignores the actual
>> state
>> + *of the power domain)
>> + *
>> + * @power_domain: A power domain struct that was previously successfully
>> + * requested by power_domain_get().
>> + * Return: a negative error code upon error during the transition, 0
>> otherwise.
>> + */
>> +static inline int power_domain_off(struct power_domain *power_domain)
>> +{
>> +int ret;
>> +
>> +ret = power_domain_off_lowlevel(power_domain);
>> +if (ret == -EALREADY || ret == -EBUSY)
>> +ret = 0;
>> +
>> +return ret;
>> +}
>> +
>> /**
>> * dev_power_domain_on - Enable power domains for a device .
>> *
>> diff --git a/test/dm/power-domain.c b/test/dm/power-domain.c
>> index
>> 896cf5b2ae9d26701150fad70e888f8b135a22b0..8a95f6bdb903be9d1993528d87d5cae0075a83e4
>> 100644
>> --- a/test/dm/power-domain.c
>> +++ b/test/dm/power-domain.c
>> @@ -27,7 +27,7 @@ static int dm_test_power_domain(struct unit_test_state
>> *uts)
>>
>> ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "power-domain-test",
>>&dev_test));
>> -ut_asserteq(1, sandbox_power_domain_query(dev_power_domain,
>> +ut_asserteq(0, sandbox_power_domain_query(dev_power_domain,
>>TEST_POWER_DOMAIN));
>> ut_assertok(sandbox_power_domain_test_get(dev_test));
>>
>>
>
--
Thanking You
Neha Malcom Francis
On 15/04/25 18:13, Miquel Raynal wrote:
> On 15/04/2025 at 15:29:09 +0530, Neha Malcom Francis wrote:
>
>> Hi Miquel
>>
>> On 15/04/25 15:20, Miquel Raynal wrote:
>>>>> Francesco, are you also testing on K3 platforms?
>>>>>
>>>
al driver probe
(ns16550_serial_probe) tries to do a readb() and fails, this could
possibly be because the device was not powered on to begin with. Whereas
in another case (what Francesco is seeing), this issue is not run into.
>
> Thanks,
> Miquèl
--
Thanking You
Neha Malcom Francis
now what board/SoC was used for the test, so I
> can look the relevant driver up.
Booted on j784s4_evm
https://gist.github.com/nehamalcom/b09687a523bec89f9df3537fdd99b6f3
Currently debugging on my build where I hang in console_init itself, I
think the path for failure is different here, will confirm.
>
> Thanks for your help,
> Miquèl
>
> ---
>
--
Thanking You
Neha Malcom Francis
; which is this patch.
>>
>> And assuming it's the same failure I got reported this morning by one of
>> my coworkers, we just get:
>> U-Boot SPL 2025.04-01050-ga40fc5afaec0 (Apr 14 2025 - 07:31:32 +)
>> SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.7--v09.02.07 (Kool Koala)')
This is not the failure I am seeing, we hang before console comes up so
no prints. Looks like the different failure signature is due to TIFS
(SYSFW) firmware being different (v9.2.7 vs. 11.0.4)
> I have not tried reverting that commit yet, but I do have the same
> failure.
>
> Francesco
>
--
Thanking You
Neha Malcom Francis
52,7 +152,7 @@ int fdt_fixup_reserved(void *blob, const char *name,
>> }
>> }
>> -add_carveout:
>> +add_carveout: ;
>> struct fdt_memory carveout = {
>> .start = new_address,
>> .end = new_address + new_size - 1,
>
> My suggestion will be to move this struct at start of function.
>
> and change only size here
>
> carveout.end = new_address + new_size - 1;
>
>
--
Thanking You
Neha Malcom Francis
On 28/03/25 19:48, Nishanth Menon wrote:
> On 18:01-20250328, Neha Malcom Francis wrote:
>> Add DT node for PBIST_14 that is responsible for triggering the PBIST
>> self-tests for the MAIN_R5_2_x cores.
>>
>> Signed-off-by: Neha Malcom Francis
>> ---
&
# Information about an EFL symbol:
> +# Information about an ELF symbol:
> # section (str): Name of the section containing this symbol
> # address (int): Address of the symbol (its value)
> # size (int): Size of the symbol in bytes
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
Add DT node for PBIST_14 that is responsible for triggering the PBIST
self-tests for the MAIN_R5_2_x cores.
Signed-off-by: Neha Malcom Francis
---
Linux dt-binding patch
https://lore.kernel.org/all/20250328111439.374748-1-n-fran...@ti.com/
Changes since v2:
- s/ti,bist-instance/ti,bist-under
Trigger all tests of PBIST and LBIST using appropriate calls to set the
core under test (MAIN R5 2_0) to it's required state.
Signed-off-by: Neha Malcom Francis
---
Changes since v2:
- move MCU4_0 BIST code into a separate function
arch/arm/mach-k3/j784s4/j784s4_init.c
Add a driver for the BIST module that support triggering of both PBIST
(Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant
operations and functions that would be required for an end user to
trigger the tests.
Signed-off-by: Neha Malcom Francis
---
Changes since v2:
- code
/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/pbist.html#introduction
[2]
https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/lbist.html#introduction
Neha Malcom Francis (3):
drivers: misc: k3_bist: Add K3 BIST
register. For N bit wide bitfields, there will be 2^N possible
> + multiplexer states.
> +
> config MUX_MMIO
> bool "MMIO register bitfield-controlled Multiplexer"
> depends on MULTIPLEXER && SYSCON
--
Thanking You
Neha Malcom Francis
nly depends on a couple of configs (is not selecting them)
and I don't see it doing anything in the code.
--
Thanking You
Neha Malcom Francis
Include spl.h to avoid definition errors in custom builds.
Fixes: commit bc07851897bd ("board: ti: Pull redundant DDR functions to a
common location and Fixup DDR size when ECC is enabled")
Signed-off-by: Neha Malcom Francis
---
arch/arm/mach-k3/include/mach/k3-ddr.h | 2 ++
1 file
This short series is an ongoing effort to make RAM utilization clearer for
easier debugging and understanding of code. Intention is for users to quickly
be able to identify the CONFIGs needed to modify for their RAM usecase.
Neha Malcom Francis (2):
board_f: Modify DRAM message
doc: memory
The message "DRAM: 2 GiB (effective 32 GiB)" can be a little confusing,
modify the message s/effective/total to make it more evident.
Signed-off-by: Neha Malcom Francis
---
common/board_f.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/board_f.c b/common
721S2_R5_EVM=y
>
> CONFIG_ESM_K3=n
> -CONFIG_K3_AVS0=n
> CONFIG_ESM_PMIC=n
> CONFIG_DM_REGULATOR_TPS65941=n
> CONFIG_PMIC_TPS65941=n
--
Thanking You
Neha Malcom Francis
Malcom Francis
---
Sanity boot log:
https://gist.github.com/nehamalcom/ef40be06080cb5bc4d1be881690aaebb
Changes since v1:
- updated commit message with version and explanation
- added sanity boot log
board/ti/j784s4/rm-cfg.yaml | 24
board/ti/j784s4/tifs-rm-cfg.yaml
would not be enough for all such use
cases for RTOS and Linux, thus sharing of resources in needed.
Signed-off-by: Vaishnav Achath
[n-fran...@ti.com: rebased and sent on behalf]
Signed-off-by: Neha Malcom Francis
---
board/ti/j784s4/rm-cfg.yaml | 24
board/ti
clk_clk"),
> @@ -400,7 +452,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
>
> const struct ti_k3_clk_platdata j721s2_clk_platdata = {
> .clk_list = clk_list,
> - .clk_list_cnt = 105,
> + .clk_list_cnt = ARRAY_SIZE(clk_list),
> .soc_dev_clk_data = soc_dev_clk_data,
> - .soc_dev_clk_data_cnt = 124,
> + .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data),
> };
> diff --git a/arch/arm/mach-k3/r5/j721s2/dev-data.c
> b/arch/arm/mach-k3/r5/j721s2/dev-data.c
> index df70c5e5d7c..b78550707c5 100644
> --- a/arch/arm/mach-k3/r5/j721s2/dev-data.c
> +++ b/arch/arm/mach-k3/r5/j721s2/dev-data.c
> @@ -5,7 +5,7 @@
> * This file is auto generated. Please do not hand edit and report any issues
> * to Dave Gerlach .
> *
> - * Copyright (C) 2020-2021 Texas Instruments Incorporated -
> https://www.ti.com/
> + * Copyright (C) 2020-2025 Texas Instruments Incorporated -
> https://www.ti.com/
> */
>
> #include "k3-dev.h"
> @@ -47,6 +47,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
> };
>
> static struct ti_dev soc_dev_list[] = {
> + PSC_DEV(29, &soc_lpsc_list[0]),
> PSC_DEV(35, &soc_lpsc_list[0]),
> PSC_DEV(108, &soc_lpsc_list[0]),
> PSC_DEV(109, &soc_lpsc_list[0]),
--
Thanking You
Neha Malcom Francis
Hi Tom,
On 13/02/25 03:53, Tom Rini wrote:
> With a newer pylint, we get a warning that 'br' could be used before
> assignment. Fix this by declaring br first as an empty bytearray.
>
> Signed-off-by: Tom Rini
> ---
> Cc: Neha Malcom Francis
> Cc: Simon Gla
_LDO_VOLT_MASK 0x7E
> #define TPS65941_LDO_VOLT_MAX_HEX0x3A
> #define TPS65941_LDO_VOLT_MIN_HEX0x4
> #define TPS65941_LDO_VOLT_MAX330
> +#define TPS65941_LDO_VOLT_MIN60
> #define TPS65941_LDO_MODE_MASK 0x1
> #define TPS65941_LDO_BYPASS_EN 0x80
> #define TP65941_BUCK_CONF_SLEW_MASK 0x7
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
On 04/02/25 19:38, Kumar, Udit wrote:
>
> On 2/4/2025 6:01 PM, Neha Malcom Francis wrote:
>> Add a driver for the BIST module that support triggering of both PBIST
>> (Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant
>> operations and functions that woul
On 05/02/25 11:38, Manorit Chawdhry wrote:
> Hi Neha,
>
> On 18:01-20250204, Neha Malcom Francis wrote:
>> Trigger all tests of PBIST and LBIST using appropriate calls to set the
>> core under test (MAIN R5 2_0) to it's required state.
>>
>> Signed-off-by: Ne
Trigger all tests of PBIST and LBIST using appropriate calls to set the
core under test (MAIN R5 2_0) to it's required state.
Signed-off-by: Neha Malcom Francis
---
arch/arm/mach-k3/j784s4/j784s4_init.c | 47 +++
1 file changed, 47 insertions(+)
diff --git a/arc
-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/pbist.html#introduction
[2]
https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/lbist.html#introduction
Neha Malcom Francis (3):
drivers: misc: k3_bist: Add
Add DT node for PBIST_14 that is responsible for triggering the PBIST
self-tests for the MAIN_R5_2_x cores.
Signed-off-by: Neha Malcom Francis
---
Link to kernel DT upstreaming:
https://lore.kernel.org/all/20241128140825.263216-1-n-fran...@ti.com/
Will be following up on its v2.
dts/upstream
Add a driver for the BIST module that support triggering of both PBIST
(Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant
operations and functions that would be required for an end user to
trigger the tests.
Signed-off-by: Neha Malcom Francis
---
drivers/misc/Kconfig
On 28-Jan-25 11:23 AM, Kumar, Udit wrote:
On 1/27/2025 7:52 PM, Neha Malcom Francis wrote:
Instead of defaulting to choosing the entire DDR region when enabling
inline ECC, allow picking of a range within the DDR space using DT to
enable.
It expects such a node within the memory node, in the
Hi Udit
On 28-Jan-25 11:23 AM, Kumar, Udit wrote:
On 1/27/2025 7:52 PM, Neha Malcom Francis wrote:
Instead of defaulting to choosing the entire DDR region when enabling
inline ECC, allow picking of a range within the DDR space using DT to
enable.
It expects such a node within the memory node
Hi Wadim
On 28-Jan-25 10:32 AM, Wadim Egorov wrote:
Hi Neha,
Am 27.01.25 um 21:22 schrieb Neha Malcom Francis:
This header file is not in use in these arch/board specific files,
remove them.
Signed-off-by: Neha Malcom Francis
---
arch/arm/mach-k3/k3-ddr.c | 1 -
board/ti/common/k3-ddr.c
Hi Wadim
On 28-Jan-25 10:43 AM, Wadim Egorov wrote:
Am 27.01.25 um 21:22 schrieb Neha Malcom Francis:
Instead of defaulting to choosing the entire DDR region when enabling
inline ECC, allow picking of a range within the DDR space using DT to
enable.
It expects such a node within the memory
uot;;
};
+
+&dmsc {
+ bootph-pre-ram;
+
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ bootph-pre-ram;
+ };
+};
--
Thanking You
Neha Malcom Francis
This header file is not in use in these arch/board specific files,
remove them.
Signed-off-by: Neha Malcom Francis
---
arch/arm/mach-k3/k3-ddr.c | 1 -
board/ti/common/k3-ddr.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/arch/arm/mach-k3/k3-ddr.c b/arch/arm/mach-k3/k3-ddr.c
index
The existing approach does not account for interleaving in the DDRs when
setting up regions. There is support for MSMC to calculate the regions
for each DDR, so modify k3_ddrss_probe to set the regions accordingly
for multi-DDR systems.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/k3
As we increase the functionalities that the K3 DDRSS sub-system support,
it is becoming more evident that the same logic cannot apply to both
single as well as multiple DDR controller devices. Add
CONFIG_K3_MULTI_DDR to be used to differentiate between the two.
Signed-off-by: Neha Malcom Francis
In K3 multi-DDR systems, the MSMC is responsible for the interleave
mechanism across all the DDR controllers. Add support for MSMC to obtain
the number of controllers it's responsible for using the DT.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/k3-ddrss/k3-ddrss.c | 8
1
Add support for calculation of the protected regions for each DDR in
multi-DDR systems. Since MSMC is the parent node of the individual DDRs
as well as responsible for their interleaving, it only makes sense for
MSMC to contain the logic for dividing the regions.
Signed-off-by: Neha Malcom
Let ecc_regions[x].start reflect the start of the ECC region in terms of
DDR addressing rather than system addressing. This will make it easier
to extend the usage of the same ecc_regions structure for multi-DDR
systems as well.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/k3-ddrss/k3
: protected@9e78 {
device_type = "ecc";
reg = <0x9e78 0x008>;
bootph-all;
};
Signed-off-by: Neha Malcom Francis
---
drivers/ram/k3-ddrss/k3-ddrss.c | 52 +++--
1 file changed, 49 insertions(+), 3 deletions(-)
diff --git
The reserved space needed for storing the parity remains the same no
matter the size of the region that is being protected. Add this as a
comment for better code understanding.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/k3-ddrss/k3-ddrss.c | 4
1 file changed, 4 insertions(+)
diff
b.com/nehamalcom/e5a76bece133c1ec716e2ed94d60ce74
Neha Malcom Francis (8):
k3-ddr.c: Remove unwanted header files
ram: k3-ddrss: Use DDR address instead of system address for
ecc_regions
ram: k3-ddrss: Add comment about ecc_reserved_space
ram: k3-ddrss: Add support for a partial inlin
truct udevice *dev)
k3_lpddr4_start(ddrss);
- k3_ddrss_ddr_bank_base_size_calc(ddrss);
-
if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) {
if (!ddrss->ddrss_ss_cfg) {
printf("%s: ss_cfg is required if ecc is enabled but not
provided.",
Reviewed-by: Neha Mal
t's at a better time for other parts of
the world.
Thanks for initiating this, I think it will be helpful for most of us. For folks
in the IST region, this is a pretty okay time in the evening so sounds good at
least for me.
--
Thanking You
Neha Malcom Francis
--
Acked-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
--
Acked-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
Management Response UPIU structure */
+ struct utp_upiu_header rsp_header;
+ __be32 output_param1;
+ __be32 output_param2;
+ __be32 __reserved2[3];
+};
+
+#endif
Acked-by: Neha Malcom Francis
--
Thanking You
Neha Malcom
hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
}
-int ufs_start(struct ufs_hba *hba)
+static int ufs_start(struct ufs_hba *hba)
{
struct ufs_dev_desc card = {0};
int ret;
--
Thanking You
Neha Malcom Francis
PRGTUNING UNIPRO_CB_OFFSET(0x00FB)
-#define UNIPRO_CB_OFFSET(x) (0x8000 | x)
+#define UNIPRO_CB_OFFSET(x) (0x8000 | (x))
/*
* PHY Adpater attributes
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
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