d/nand/raw/octeontx_bch.h
delete mode 100644 drivers/mtd/nand/raw/octeontx_bch_regs.h
delete mode 100644 drivers/mtd/nand/raw/octeontx_nand.c
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
_
= io_op.oobretlen;
> }
>
> + if (benchmark && bench_start) {
> + bench_end = timer_get_us();
> + printf("%s speed: %lukiB/s\n",
> + read ? "Read" : "Write",
> +
On Fri, Jul 11, 2025 at 5:19 PM Tom Rini wrote:
> As no platforms use this driver anymore let's go ahead and remove it.
>
> Signed-off-by: Tom Rini
> ---
> drivers/mtd/nand/raw/Kconfig | 16 -
> drivers/mtd/nand/raw/Makefile|2 -
> drivers/mtd/nand/raw/octeontx_bch
"Unable to get free DMA channel for NAND
> transfers\n");
> - return -1;
> - }
> - dmachan = (unsigned int)ret;
> -#endif
> -
> - lpc32xx_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
> - lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
> -
> - /*
> -* The implementation of these functions is quite common, but
> -* they MUST be defined, because access to data register
> -* is strictly 32-bit aligned.
> -*/
> - lpc32xx_chip->read_byte = lpc32xx_read_byte;
> - lpc32xx_chip->write_byte = lpc32xx_write_byte;
> -
> -#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD)
> - /* Hardware ECC calculation is supported when DMA driver is
> selected */
> - lpc32xx_chip->ecc.mode = NAND_ECC_HW;
> -
> - lpc32xx_chip->read_buf = lpc32xx_dma_read_buf;
> - lpc32xx_chip->write_buf = lpc32xx_dma_write_buf;
> -
> - lpc32xx_chip->ecc.calculate = lpc32xx_ecc_calculate;
> - lpc32xx_chip->ecc.correct = lpc32xx_correct_data;
> - lpc32xx_chip->ecc.hwctl = lpc32xx_hwecc_enable;
> - lpc32xx_chip->chip_delay= 2000;
> -
> - lpc32xx_chip->ecc.read_page = lpc32xx_read_page_hwecc;
> - lpc32xx_chip->ecc.write_page= lpc32xx_write_page_hwecc;
> - lpc32xx_chip->options |= NAND_NO_SUBPAGE_WRITE;
> -#else
> - /*
> -* Hardware ECC calculation is not supported by the driver,
> -* because it requires DMA support, see LPC32x0 User Manual,
> -* note after SLC_ECC register description (UM10326, p.198)
> -*/
> - lpc32xx_chip->ecc.mode = NAND_ECC_SOFT;
> -
> - /*
> -* The implementation of these functions is quite common, but
> -* they MUST be defined, because access to data register
> -* is strictly 32-bit aligned.
> -*/
> - lpc32xx_chip->read_buf = lpc32xx_read_buf;
> - lpc32xx_chip->write_buf = lpc32xx_write_buf;
> -#endif
> -
> - /*
> -* These values are predefined
> -* for both small and large page NAND flash devices.
> -*/
> - lpc32xx_chip->ecc.size = CFG_SYS_NAND_ECCSIZE;
> - lpc32xx_chip->ecc.bytes= CFG_SYS_NAND_ECCBYTES;
> - lpc32xx_chip->ecc.strength = 1;
> -
> - if (CONFIG_SYS_NAND_PAGE_SIZE != NAND_LARGE_BLOCK_PAGE_SIZE)
> - lpc32xx_chip->ecc.layout = &lpc32xx_nand_oob_16;
> -
> -#if defined(CONFIG_SYS_NAND_USE_FLASH_BBT)
> - lpc32xx_chip->bbt_options |= NAND_BBT_USE_FLASH;
> -#endif
> -
> - /* Initialize NAND interface */
> - lpc32xx_nand_init();
> -
> - return 0;
> -}
> --
> 2.43.0
>
>
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com
r_err("pxa3xx driver supports single CS only\n");
> + kfree(pdata);
> return -EINVAL;
> }
>
Reviewed-by: MIchael Trimarchi
>
>
> --
> 2.39.5
>
>
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M.
L);
> + if (err)
> goto err_free_buffers;
>
> - if (mxs_nand_setup_ecc(mtd))
> + err = mxs_nand_setup_ecc(mtd);
> + if (err)
> goto err_free_buffers;
>
> nand->ecc.read_page = mxs_nand_ecc_read_page;
>
>
Reviewed-
waiting for irq 0x%x\n",
> + irq_mask);
> + return 0;
> }
>
>
Reviewed-by: Michael Trimarchi
> static uint32_t denali_check_irq(struct denali_nand_info *denali)
>
> --
> 2.39.5
>
>
--
Michael Nazzareno Trimarchi
Co-Founder & Ch
CA_DMA_DESC_NUM));
> + if (!info->rx_desc) {
> printf("Fail to alloc DMA descript!\n");
> kfree(info->tx_desc);
> return -ENOMEM;
>
>
Reviewed-by: Michael Trimarchi
>
gt;
> ret = sunxi_nand_ecc_init(mtd, &nand->ecc);
> if (ret) {
> dev_err(dev, "ECC init failed: %d\n", ret);
> + kfree(chip);
> return ret;
> }
>
> ret = nand_scan_tail(mtd);
> if
gt; -{
> - struct mxic_nand_ctrl *nfc = dev_get_priv(dev);
> - struct nand_chip *nand_chip = &nfc->nand_chip;
> - struct mtd_info *mtd;
> - ofnode child;
> - int err;
> -
> - nfc->regs = dev_read_addr_ptr(dev);
> -
> - n
Hi
Could be html for my mobile. Some comments inline.
Il ven 11 lug 2025, 11:44 Anshul Dalal ha scritto:
> On Thu Jul 10, 2025 at 10:41 PM IST, Judith Mendez wrote:
> > This removes support from booting from UDA when in eMMC boot.
> >
> > When user selects eMMC boot [0], that is, boot from eMMC
Hi
On Fri, Jul 4, 2025 at 3:33 PM Fabio Estevam wrote:
>
> Hi Michael,
>
> On Fri, Jul 4, 2025 at 5:37 AM Michael Nazzareno Trimarchi
> wrote:
>
> > We have problems that our board crashes with display enabled when this
> > series is applied but we can boot
> &g
223
> >> ++-
> >> common/board_r.c | 247
> >> +++-------
> >> include/initcall.h| 49 +++---
> >> lib/Makefile | 1 -
> &g
int do_mtd_io(struct cmd_tbl *cmdtp, int flag,
> int argc,
> io_op.oobbuf += io_op.oobretlen;
> }
>
> + if (benchmark && bench_start) {
> + bench_end = timer_get_us();
> + printf("%s speed: %lukiB/s\n",
> +
Hi Fabio
Are you going to pick up my last series?
Michael
On Mon, May 26, 2025 at 10:01 PM Michael Nazzareno Trimarchi
wrote:
>
> Hi Fabio
>
> On Mon, May 26, 2025 at 9:58 PM Fabio Estevam wrote:
> >
> > Hi Michael,
> >
> > On Mon, May 26, 2025 at
MAL_DRIVERS=y
> >
> > -obj-y += nand.o
> > -obj-y += nand_bbt.o
> > -obj-y += nand_ids.o
> > -obj-y += nand_util.o
> > -obj-y += nand_ecc.o
> > -obj-y += nand_base.o
> > -obj-y += nand_amd.o
> > -obj-y += nand_hynix.o
> > -obj-y += nand_macronix.o
> > -obj-y += nand_micron.o
> > -obj-y += nand_samsung.o
> > -obj-y += nand_toshiba.o
> > -obj-y += nand_timings.o
> > +obj-y += $(nand-framework-objs)
> >
> > endif # not spl
>
> Did you world build this change? At first it looks like we're dropping a
> lot of objects from other configs.
>
> --
> Tom
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com
Hi
On Wed, Jun 4, 2025 at 8:48 AM Michael Nazzareno Trimarchi
wrote:
>
> Hi Patrice
>
> On Wed, Jun 4, 2025 at 8:46 AM Patrice CHOTARD
> wrote:
> >
> >
> >
> > On 6/4/25 08:14, Michael Nazzareno Trimarchi wrote:
> > > Hi
> > >
> >
Hi Patrice
On Wed, Jun 4, 2025 at 8:46 AM Patrice CHOTARD
wrote:
>
>
>
> On 6/4/25 08:14, Michael Nazzareno Trimarchi wrote:
> > Hi
> >
> > On Wed, Jun 4, 2025 at 8:02 AM Patrice CHOTARD
> > wrote:
> >>
> >>
> >>
> >&g
nline bool clk_dev_binded(struct clk *clk)
> > {
> > return false;
> > }
> > +
> > +static inline ulong clk_get_id(const struct clk *clk)
> > +{
> > + return 0;
> > +}
> > #endif /* CONFIG_IS_ENABLED(CLK) */
> >
> > /**
>
Hi
Il ven 30 mag 2025, 20:14 Christoph Niedermaier <
cniederma...@dh-electronics.com> ha scritto:
> Hello,
>
> From: Michael Nazzareno Trimarchi
> Sent: Friday, May 30, 2025 5:12 PM
> Subject: Re: [PATCH v3 1/4] clk: imx: add i.MX6UL clk driver
>
> [...]
>
&
quot;uart_podf", base + 0x74,
> > 2));
> > + clk_dm(IMX6UL_CLK_UART6_IPG,
> > + imx_clk_gate2(dev, "uart6_ipg", "ipg", base + 0x74, 6));
> > + clk_dm(IMX6UL_CLK_UART6_SERIAL,
> > + imx_clk_gate2(dev, "uart6_ser
IMX6UL_CLK_ECSPI3,
> > +imx_clk_gate2(dev, "ecspi3", "ecspi_podf", base + 0x6c, 4));
> > + clk_dm(IMX6UL_CLK_ECSPI4,
> > +imx_clk_gate2(dev, "ecspi4", "ecspi_podf", base + 0x6c, 6));
> > +
> > + clk_d
:mailto:korg.su...@gmail.com
ATTENDEE;CUTYPE=INDIVIDUAL;ROLE=REQ-PARTICIPANT;PARTSTAT=ACCEPTED;RSVP=TRUE
;CN=Michael Nazzareno Trimarchi;X-NUM-GUESTS=0:mailto:michael@amarulasoluti
ons.com
ATTENDEE;CUTYPE=INDIVIDUAL;ROLE=REQ-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=
TRUE;CN=s...@chromium.org;X-NUM-GUESTS=0
:mailto:korg.su...@gmail.com
ATTENDEE;CUTYPE=INDIVIDUAL;ROLE=REQ-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=
TRUE;CN=Michael Nazzareno Trimarchi;X-NUM-GUESTS=0:mailto:michael@amarulaso
lutions.com
ATTENDEE;CUTYPE=INDIVIDUAL;ROLE=REQ-PARTICIPANT;PARTSTAT=NEEDS-ACTION;RSVP=
TRUE;CN=s...@chromium.org;X-NUM
r being used?
The downstream driver I made 2 years ago before this change was around
3/3.5mB/sec, if I remember correctly.
One point all the IMX6 platforms can then be migrated but I don't have
any board with me.
Michael
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Offi
he kernel and I don't know if is english wrong
>
> > +*/
> > + if (IS_ENABLED(CONFIG_MX6ULL)) {
> > + clk_disable(nand_info->gpmi_clk);
> > + }
>
> Please remove { } for single-line statements.
Done
>
> > +
> >
Hi Peng
On Mon, May 26, 2025 at 9:42 AM Michael Nazzareno Trimarchi
wrote:
>
> Hi Peng
>
> On Mon, May 26, 2025 at 9:38 AM Michael Nazzareno Trimarchi
> wrote:
> >
> > Hi Peng
> >
> > On Mon, May 26, 2025 at 9:34 AM Peng Fan wrote:
> > >
> &g
ret = clk_enable_bulk(&clk_bulk);
>
> You enable clk bulk and together with a standalone gpmi_io clk?
>
I need to get and refer to the gpmi_io because it is used then by the
driver. I think
that this does not change what was before. Am I missing?
Michael
> Regards,
> Peng
>
>
> > if (ret < 0) {
> >- debug("Can't enable gpmi_bch_apb clk: %d\n", ret);
> >+ debug("Can't enable gpmi clks: %d\n", ret);
> > return ret;
> > }
> > }
> >--
> >2.43.0
> >
> >base-commit: df2ed552f0b05591090369a7fe7ddc92439dea5c
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com
Hi Peng
On Mon, May 26, 2025 at 9:38 AM Michael Nazzareno Trimarchi
wrote:
>
> Hi Peng
>
> On Mon, May 26, 2025 at 9:34 AM Peng Fan wrote:
> >
> > On Sun, May 25, 2025 at 02:23:10PM +0200, Michael Trimarchi wrote:
> > >Make simple the clock registration and e
ddrc_cfg++;
> + }
> +}
> +
> +static void spl_dram_init(void)
> +{
> + struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
> +
> + clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
> + clrbits_le32(&mmdc
Hi
On Sat, May 17, 2025 at 10:50 PM Fabio Estevam wrote:
>
> On Sat, May 17, 2025 at 5:46 PM Michael Nazzareno Trimarchi
> wrote:
>
> > > I was on master except this commit
> > >
> > > commit 128d997a8772cc174f38d529d8b25f90b3aa8ad8
> > > Author:
Hi Fabio
On Sat, May 17, 2025 at 10:44 PM Michael Nazzareno Trimarchi
wrote:
>
> Hi
>
> On Sat, May 17, 2025 at 10:28 PM Fabio Estevam wrote:
> >
> > On Sat, May 17, 2025 at 5:15 PM Michael Nazzareno Trimarchi
> > wrote:
> >
> > > Can you pl
Hi
On Sat, May 17, 2025 at 10:28 PM Fabio Estevam wrote:
>
> On Sat, May 17, 2025 at 5:15 PM Michael Nazzareno Trimarchi
> wrote:
>
> > Can you please point me to an example of a tested board?
>
> I have just tested the top-of-tree U-Boot on an imx8mn evk board:
>
>
Hi Fabio
On Sat, May 17, 2025 at 9:56 PM Fabio Estevam wrote:
>
> Hi Michael,
>
> On Thu, May 15, 2025 at 5:12 PM Michael Nazzareno Trimarchi
> wrote:
>
> > The serial is not up at that time so we need to buffer the error and print
> > later. Right now
>
to understand but even we need working boards
> Does the failure come from clk_get_bulk() or clk_enable_bulk()?
>
The serial is not up at that time so we need to buffer the error and print
later. Right now
we are working on other fixes
Michael
>
> Please investigate.
>
--
Mi
marchi
> Met vriendelijke groet / kind regards,
>
> Mike Looijmans
> System Expert
>
>
> TOPIC Embedded Products B.V.
> Materiaalweg 4, 5681 RJ Best
> The Netherlands
>
> T: +31 (0) 499 33 69 69
> E: mike.looijm...@topic.nl
> W: www.topic.nl
>
> Please
Hi
Il lun 7 apr 2025, 22:03 Fabio Estevam ha scritto:
> On Mon, Apr 7, 2025 at 4:58 PM Michael Nazzareno Trimarchi
> wrote:
>
> > Can you review it and pick if needed?
>
> This is not assigned to me in patchwork as it is not i.MX related.
>
> Someone else needs to h
T_SIZ_FULL)
> > + size = master->size - offset;
> >
> > part.name = ofnode_read_string(child, "label");
> > if (!part.name)
>
>
> --
> Mike Looijmans
> System Expert
>
> TOPIC Embedded Products
>
> > list_for_each_entry(child_dev, &clk->dev->child_head,
> sibling_node) {
> > + if (device_get_uclass_id(child_dev) != UCLASS_CLK)
> > + continue;
> > +
> > clkp = dev_get_clk_ptr(child_dev);
> > clk_clea
llthrough;
> case NAND_ECC_SOFT:
> ecc->calculate = nand_calculate_ecc;
> ecc->correct = nand_correct_data;
> --
> 2.25.1
>
Reviewed-by: Michael Trimrachi
I think I will apply the relative patches on mtd tree
Michael
Hi
Applied and sent the pull request
Would be nice to have sometime board sample to work with
Michael
On Wed, Mar 5, 2025 at 5:05 PM Maniyam, Dinesh
wrote:
>
>
>
>
> *From:* Michael Nazzareno Trimarchi
> *Sent:* Wednesday, 5 March 2025 5:27 pm
> *To:* Maniyam, D
-
> - if (oob_required)
> - meson_nfc_set_user_byte(chip, chip->oob_poi);
> + meson_nfc_set_user_byte(chip, chip->oob_poi);
>
> return meson_nfc_write_page_sub(chip, page, false);
> }
>
Applied and sent already the pull request
Michael
The following changes since commit 15d6518c942f0da13f9a7ceeadbd925c3317ec8d:
ARM: dts: imx: Drop bogus regulator extras on DH i.MX6 DHCOM DRC02
(2025-03-13 15:22:48 -0600)
are available in the Git repository at:
git://source.denx.de:u-boot/custodians/u-boot-nand-flash.git nand-next
for you
clkp = dev_get_clk_ptr(child_dev);
> clk_clean_rate_cache(clkp);
> }
>
Reviewed-by: Michael Trimarchi
Michael
> --
> 2.48.1
>
>
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulaso
Hi
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com
-nand-flash/-/commits/nand-next?ref_type=heads
Michael
On Wed, Feb 26, 2025 at 5:36 PM Maniyam, Dinesh
wrote:
>
>
> > -Original Message-
> > From: Maniyam, Dinesh
> > Sent: Wednesday, 26 February 2025 11:37 am
> > To: 'Michael Nazzareno Trimarchi&#x
Hi
On Mon, Mar 3, 2025 at 1:54 PM Adam Ford wrote:
> On Mon, Mar 3, 2025 at 6:34 AM Michael Nazzareno Trimarchi
> wrote:
> >
> > Hi Adam
> >
> > On Sun, Mar 2, 2025 at 5:53 PM Adam Ford wrote:
> >>
> >> The ECSPI clock has the ability to se
cspi_root", "pll3_60m", base + 0x38, 19,
> 6));
> -
> + if (clk_on_imx6qp()) {
> + clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
> + imx_clk_divider("ecspi_root", "ecspi_sel", base +
> 0x38, 19, 6));
> + } else {
> +
Hi
On Fri, Feb 28, 2025 at 5:02 AM Maniyam, Dinesh
wrote:
>
>
>
> > -Original Message-
> > From: Michael Nazzareno Trimarchi
> > Sent: Friday, 28 February 2025 5:30 am
> > To: Maniyam, Dinesh
> > Cc: u-boot@lists.denx.de; Marek ; Simon
> > ;
icron.o \
> + nand_samsung.o nand_toshiba.o
> +
> ifdef CONFIG_SPL_BUILD
>
> +ifdef CONFIG_SPL_NAND_FRAMEWORK
> +obj-y += $(nand-framework-objs)
> +NORMAL_DRIVERS=y
> +endif
> +
> ifdef CONFIG_SPL_NAND_DRIVERS
> NORMAL_DRIVERS=y
> endif
>
529
> include/linux/mtd/rawnand.h | 12 +
> 13 files changed, 3278 insertions(+), 26 deletions(-)
> create mode 100644 configs/socfpga_agilex5_nand2_defconfig
> create mode 100644 doc/device-tree-bindings/mtd/cadence,nand.yaml
> create mode
; @@ -1133,7 +1133,7 @@ static int atmel_smc_nand_prepare_smcconf(struct
> >>>>> atmel_nand *nand,
> >>>>>const struct nand_data_interface
> >>>>> *conf,
> >>>>>
s not paassing the CI. I will test it again today
Michael
> > -Original Message-
> > From: Maniyam, Dinesh
> > Sent: Tuesday, 17 December 2024 3:41 pm
> > To: Michael Nazzareno Trimarchi
> > Cc: u-boot@lists.denx.de; Marek ; Simon
> > ; Tom Rini ; Dario
_info *c, int lnum,
> void ubifs_end_scan(const struct ubifs_info *c, struct ubifs_scan_leb *sleb,
> int lnum, int offs)
> {
> - lnum = lnum;
> dbg_scan("stop scanning LEB %d at offset %d", lnum, offs);
> ubifs_assert(offs % c-
are the running notes
> > <https://docs.google.com/document/d/1YBOMsbM19uSFyoJWnt7-PsOLBaevzQUgV-hiR88a5-o/edit?tab=t.0>
> > from the previous series.
>
> Meeting minutes are good, but perhaps we should send them out via email
> so they're more accessible.
>
+
aster' or something
> along those lines, which further complicates things as people might think
> their code got merged.
>
Me too. I don't have that time and for the moment how the project is
progressive is fine.
Michael
> I think we s
Hi
Il ven 27 dic 2024, 14:17 Ayrton Leyssens ha scritto:
> Hi
>
> I am having troubles booting an iMX8M Nano board.
> I compiled U-Boot and flashed it to an SD-card using Buildroot.
>
> The board starts my SPL, does the DRAM init, goes back to BOOTROM and
> eventually goes to the SPL stage where
Hi
Yes
Michael
On Tue, Dec 24, 2024 at 8:55 AM Arseniy Krasnov
wrote:
>
>
>
> On 23.12.2024 15:57, Michael Nazzareno Trimarchi wrote:
> > On Sun, Dec 22, 2024 at 10:23 PM Arseniy Krasnov
> > wrote:
> >>
> >> If 'oob_required' is not set by
red)
> - meson_nfc_set_user_byte(chip, chip->oob_poi);
> + meson_nfc_set_user_byte(chip, chip->oob_poi);
>
Reviewed-by: Michael Trimarchi
I will queue it
> return meson_nfc_write_page_sub(chip, page, false);
> }
> --
> 2.30.1
--
Michael Nazzareno
Hi Tom
The following changes since commit 9452fb7484118822b878ad445237d111b7b1a28d:
Merge branch 'master' of
https://source.denx.de/u-boot/custodians/u-boot-sh (2024-12-11
12:50:29 -0600)
are available in the Git repository at:
g...@source.denx.de:u-boot/custodians/u-boot-nand-flash.git
mik
| 14 +
> 13 files changed, 3293 insertions(+), 25 deletions(-)
> create mode 100644 configs/socfpga_agilex5_nand2_defconfig
> create mode 100644 doc/device-tree-bindings/mtd/cadence,nand.yaml
> create mode 100644 drivers/mtd/nand/raw/cadence_nand.c
> create mode 100644 drivers/mtd/
rporation
> + *
Drop here
> * Info:
> * Contains standard defines and IDs for NAND flash devices
> *
> @@ -131,6 +133,17 @@ void nand_wait_ready(struct mtd_info *mtd);
>
> #define NAND_DATA_IFACE_CHECK_ONLY -1
>
> +/*
> + * There are different places where the manufacturer stores the factory bad
> + * block markers.
> + *
> + * Position within the block: Each of these pages needs to be checked for a
> + * bad block marking pattern.
> + */
> +#define NAND_BBM_FIRSTPAGE BIT(24)
> +#define NAND_BBM_SECONDPAGEBIT(25)
> +#define NAND_BBM_LASTPAGE BIT(26)
> +
> /*
> * Constants for ECC_MODES
> */
> --
> 2.19.0
>
Reviewed-by: Michael Trimarchi
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com
Hi
Il mar 10 dic 2024, 08:08 Marcus Folkesson ha
scritto:
> Hello Michael,
>
> On Fri, Aug 30, 2024 at 09:05:27AM +0200, Michael Nazzareno Trimarchi
> wrote:
> > Hi Marcus
> >
> > On Fri, Aug 30, 2024 at 8:59 AM Marcus Folkesson
> > wrote:
> > >
&
Hi
Il gio 5 dic 2024, 10:36 Maniyam, Dinesh ha
scritto:
>
>
> > -Original Message-
> > From: Maniyam, Dinesh
> > Sent: Thursday, 5 December 2024 5:23 pm
> > To: u-boot@lists.denx.de
> > Cc: Marek ; Simon ; Tom
> > Rini ; Dario Binacchi
> > ; Michael Trimarchi
> > ; Johan Jonker ; Michal
Hi Tom
The following changes since commit 3881c6b90350b0b04085ad46ef64989b43967eef:
configs: Resync with savedefconfig (2024-11-26 08:17:35 -0600)
are available in the Git repository at:
g...@source.denx.de:u-boot/custodians/u-boot-nand-flash.git
mike/u-boot-nand-20241126
for you to fetch
* In cases where ops->datbuf != NULL, mtd->_read_oob() has semantics
> +* similar to mtd->_read(), returning a non-negative integer
> +* representing max bitflips. In other cases, mtd->_read_oob() may
> +* return -EUCLEAN. In all cases, perform similar logic to mtd_read().
> +*/
> + ret_code = mtd->_read_oob(mtd, from, ops);
> + if (unlikely(ret_code < 0))
> + return ret_code;
> + if (mtd->ecc_strength == 0)
> + return 0; /* device lacks ecc */
> + return ret_code;
> +}
> +EXPORT_SYMBOL_GPL(mtd_read_oob_bf);
> +
> int mtd_write_oob(struct mtd_info *mtd, loff_t to,
> struct mtd_oob_ops *ops)
> {
> diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
> index 09f52698877..28afbb86ea9 100644
> --- a/include/linux/mtd/mtd.h
> +++ b/include/linux/mtd/mtd.h
> @@ -413,6 +413,7 @@ int mtd_panic_write(struct mtd_info *mtd, loff_t to,
> size_t len, size_t *retlen,
> const u_char *buf);
>
> int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops);
> +int mtd_read_oob_bf(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops
> *ops);
> int mtd_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops);
>
> int mtd_get_fact_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen,
> --
> 2.34.1
>
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com
ions(+), 26 deletions(-)
> >>
> >
> > Coming back to these patches I had a look and except a typo , it looks good.
> > I can take these through at91 tree or maybe Michael you want to have a
> > look as they touch the MTD/NAND drivers ?
> >
>
ts
> delete mode 100644 arch/arm/dts/bcm96756.dts
> delete mode 100644 arch/arm/dts/bcm96813.dts
> delete mode 100644 arch/arm/dts/bcm96855.dts
> delete mode 100644 arch/arm/dts/bcm96856.dts
> delete mode 100644 arch/arm/dts/bcm96858.dts
> delete mode 100644 arch/arm/dts/bcm9687
existing
> brcmnand_read_data_bus.
>
> We are working on a better solution and will update.
>
> > Yours,
> > Linus Walleij
I'm thinking of applying this series for a general cleanup. What would
like to have in cover letter, is what board
this series was tested, due the fact that some of the code is not
necessary anymore
Michael
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com
Hi
On Thu, Nov 7, 2024 at 10:27 AM Heinrich Schuchardt wrote:
>
> On 11/3/24 00:36, Michael Nazzareno Trimarchi wrote:
> > Hi Tom
> >
> > On Sun, Nov 3, 2024 at 12:26 AM Tom Rini wrote:
> >>
> >> On Sat, 26 Oct 2024 08:40:43 +0200, Heinrich Schuchardt
Hi Tom
On Sun, Nov 3, 2024 at 9:21 AM Michael Nazzareno Trimarchi
wrote:
>
> Hi
>
> Il dom 3 nov 2024, 00:53 Tom Rini ha scritto:
>>
>> On Sun, Nov 03, 2024 at 12:36:38AM +0100, Michael Nazzareno Trimarchi wrote:
>> > Hi Tom
>> >
>> &
Hi
On Mon, Nov 4, 2024 at 6:17 PM Adam Ford wrote:
>
> On Mon, Nov 4, 2024 at 11:04 AM Michael Nazzareno Trimarchi
> wrote:
> >
> > Hi Adam
> >
> > On Mon, Nov 4, 2024 at 6:01 PM Adam Ford wrote:
> > >
> > > On Mon, Nov 4, 2024 a
Hi Adam
On Mon, Nov 4, 2024 at 6:01 PM Adam Ford wrote:
>
> On Mon, Nov 4, 2024 at 10:29 AM Michael Nazzareno Trimarchi
> wrote:
> >
> > Hi Adam
> >
> > On Mon, Nov 4, 2024 at 5:11 PM Adam Ford wrote:
> > >
> > > On Sun, Ju
; > + if (ret)
> > + return ret;
> > + clk_dm(IMX8MN_CLK_24M, dev_get_clk_ptr(osc_24m_clk.dev));
> > +
>
> These four lines appear to have introduced a regression on the
> imx8mn-beacon board. In the SPL phase, I get an error message
> indicating it
Hi
Il dom 3 nov 2024, 00:53 Tom Rini ha scritto:
> On Sun, Nov 03, 2024 at 12:36:38AM +0100, Michael Nazzareno Trimarchi
> wrote:
> > Hi Tom
> >
> > On Sun, Nov 3, 2024 at 12:26 AM Tom Rini wrote:
> > >
> > > On Sat, 26 Oct 2024 08:40:43 +0200, Hei
free(dirs);
}
if (dir)
ext4fs_free_node(dir, &ext4fs_root->diropen);
return ret;
}
Should not be like this?
> --
> Tom
>
>
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
.uuid = ext4fs_uuid,
> - .opendir = fs_opendir_unsupported,
> + .opendir = ext4fs_opendir,
> + .readdir = ext4fs_readdir,
> + .closedir = ext4fs_closedir,
> .unlink = fs_unlink_unsupported,
> .mkdir
le1(filename, &ext4fs_root->diropen, &dirnode,
> + &filetype);
> + if (dirnode)
> + ext4fs_free_node(dirnode, &ext4fs_root->diropen);
> +
> + return ret;
> }
>
Reviewed-by: Michael Trimarchi
> int ext4f
> dirent.inode),
> +
> &fdiro->inode);
> if (status == 0) {
> free(fdiro);
>
Hi Marek
On Wed, Oct 23, 2024 at 10:41 AM Marek Vasut wrote:
>
> On 10/23/24 5:18 AM, Abbarapu, Venkatesh wrote:
> > Hi Marek,
> > There was some issue and fix is sent
> > https://lore.kernel.org/u-boot/20241018082644.22495-1-venkatesh.abbar...@amd.com/T/#u
>
> Is this one fix or three fixes for
Hi
On Fri, Oct 11, 2024 at 9:54 PM Michael Nazzareno Trimarchi
wrote:
>
> Hi
>
> On Fri, Oct 11, 2024 at 4:49 PM Linus Walleij
> wrote:
> >
> > This adds support for the NAND controller on the Broadcom
> > BCA (Broadband Access) platforms.
> >
> >
Hi
On Wed, Oct 9, 2024 at 10:24 AM Michael Nazzareno Trimarchi
wrote:
>
> Hi
>
> On Mon, Jul 29, 2024 at 10:07 AM Eugen Hristev
> wrote:
> >
> > On 7/25/24 12:41, Michael Nazzareno Trimarchi wrote:
> > > Hi
> > >
> > > On Thu, Jul 25,
bcmbca_nand.c | 152 +++
8 files changed, 182 insertions(+), 134 deletions(-)
delete mode 100644 arch/arm/dts/bcm6846.dtsi
delete mode 100644 arch/arm/dts/bcm96846.dts
create mode 100644 drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c
--
Michael Nazzareno Trimarchi
Co-Founder & C
1167c3c91367e8194a69d1b
> change-id: 20240930-bcmbca-nand-support-4447e176bbbd
>
> Best regards,
> --
> Linus Walleij
>
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com
al mode]";
> connector_mode = m2_manual_config;
> @@ -429,6 +431,8 @@ int board_late_init(void)
> /* change CTRL_MMR register to let serdes0 not output USB3.0 signals.
> */
> writel(0x3, SERDES0_LANE_SELECT);
>
> + enable_pcie_connector
config:sw," \
> + "m2_manual_config:sw," \
> "eth1addr:mw,eth2addr:mw,watchdog_timeout_ms:dw,boot_targets:sw"
> #endif
>
Reviewed-by: Michael Trimarchi
> --
>
Hi
On Mon, Jul 29, 2024 at 10:07 AM Eugen Hristev
wrote:
>
> On 7/25/24 12:41, Michael Nazzareno Trimarchi wrote:
> > Hi
> >
> > On Thu, Jul 25, 2024 at 11:36 AM
> > wrote:
> >>
> >> Acked-by: Balamanikandan Gunasundar
> >>
> >>
Hi
On Wed, Oct 9, 2024 at 10:22 AM Zixun LI wrote:
>
> Hi, sorry to bother, it seems like the patch is not picked up yet ?
>
> Zixun
I will pick up today and prepare for next pull request
Michael
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 3
gt; >>> atmel_nand *nand,
> >>> ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
> >>>
> >>> /*
> >>> - * Read pulse timing directly matches tRP:
> >>> +* Read pulse timing would dire
quot;Broadcom 6846 Reference Board"
> depends on ARCH_BCMBCA
> + imply MTD_RAW_NAND
> + imply NAND_BRCMNAND
> + imply NAND_BRCMNAND_BCMBCA
>
> config SYS_SOC
> default "bcm6846"
>
Reviewed-by: Michael Trimarchi
> --
> 2.4
rcm,nand-bcm63138",
> + },
> + { /* sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(bcmbca_nand) = {
> + .name = "bcmbca-nand",
> + .id = UCLASS_MTD,
> + .of_match = bcmbca_nand_dt_ids,
> + .probe = bcmbca_nand_probe,
> + .
Hi
On Mon, Oct 7, 2024 at 4:23 AM Maniyam, Dinesh wrote:
>
> > -Original Message-
> > From: Tom Rini
> > Sent: Saturday, 5 October 2024 11:21 pm
> > To: Michael Nazzareno Trimarchi
> > Cc: Maniyam, Dinesh ; u-boot@lists.denx.de;
> > Marek ; Si
Hi
On Mon, Sep 30, 2024 at 2:54 PM Linus Walleij wrote:
>
> On Sat, Sep 28, 2024 at 2:51 AM Michael Nazzareno Trimarchi
> wrote:
>
> > I have already seen all of them and I follow the thread
> >
> > We will pick them up
>
> Thanks Michael, I will send out
(+), 45 deletions(-)
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions
hang();
> +
> + sector_align_offset = sector & (~(mtd->erasesize - 1));
> +
> + sector_align_end_offset = (sector + offs) & (~(mtd->erasesize - 1));
> +
> + while (sector_align_offset <= sector_align_end_offset) {
> + if (nand_block_isbad(mtd, sector_align_offset)) {
>
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
> +CONFIG_SPL_STACK=0x73000
> +CONFIG_SYS_SPL_MALLOC=y
> +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
> +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xbfa0
> +CONFIG_SYS_SPL_MALLOC_SIZE=0x50
> +CONFIG_SPL_BSS_MAX_SIZE=0x10
>
t take in account. Is somenthing that we
should care? and if not we should
warning the user?
Apart of that
Reviewed-by: Michael Trimarchi
michael
> }
>
> --
> 2.45.2
>
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2
n
> > this.
>
> I'm sorry I don't fully understand your answer. I assume you agree with
> the generic approach quoted above.
>
> > If a clock is enabled by another stage and we don't aware about
> > it we need to mark
> > as enabled.
renting.
> >
> > That's exactly the link above, whose diff is pasted here for reference:
> >
> > @@ -595,6 +595,10 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
> > if (!ops->set_parent)
> > return -ENOSYS;
> >
>
patch, which is more
> future and platform agnostic, fixed it:
>
> https://lore.kernel.org/u-boot/20240910101344.110633-3-miquel.ray...@bootlin.com/
>
The clock patches are not specific at all. You need to have it working
for the parent for each component.
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