Hi Eugen,
> On 05.06.2020 10:49, Gregory CLEMENT wrote:
>> Hi Eugen,
>>
>>> On 10.01.2020 08:32, Stefan Roese wrote:
>>>
>>>> On 09.01.20 17:30, Gregory CLEMENT wrote:
>>>>> According to the linker script for both armv7 and arm926ejs
Now that CONFIG_SPL_SEPARATE_BSS is selected for all the AT91 based
boards, cleanups the defconfigs by removing it.
Reviewed-by: Stefan Roese
Signed-off-by: Gregory CLEMENT
---
configs/gardena-smart-gateway-at91sam_defconfig | 1 -
configs/sama5d27_som1_ek_mmc1_defconfig | 1 -
configs
: Stefan Roese
Signed-off-by: Gregory CLEMENT
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 21df1c415f..3ba7e338b6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -532,6 +532,7 @@ choice
config ARCH_AT91
bool
- modify a new defconfig sama5d3_xplained_nandflash_defconfig
Thanks,
Gregory
Gregory CLEMENT (2):
ARM: at91: Enable SPL_SEPARATE_BSS by default
configs: atmel: cleanup CONFIG_SPL_SEPARATE_BSS
arch/arm/Kconfig| 1 +
configs/gardena-smart-gateway
Hi Eugen,
> On 10.01.2020 08:32, Stefan Roese wrote:
>
>> On 09.01.20 17:30, Gregory CLEMENT wrote:
>>> According to the linker script for both armv7 and arm926ejs based SoC,
>>> BSS section was all the time separated for SPL but this symbol was
>>> only
Now that CONFIG_SPL_SEPARATE_BSS is selected for all the AT91 based
boards, cleanups the defconfigs by removing it.
Signed-off-by: Gregory CLEMENT
---
configs/gardena-smart-gateway-at91sam_defconfig | 1 -
configs/sama5d27_som1_ek_mmc1_defconfig | 1 -
configs
: Gregory CLEMENT
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f9dab073ea..e558024652 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -492,6 +492,7 @@ choice
config ARCH_AT91
bool "Atmel AT91"
work as expected.
Signed-off-by: Gregory CLEMENT
---
arch/arm/cpu/arm926ejs/lpc32xx/timer.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
b/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
index 404ccbb716..b3ca686040 100644
--- a/arch/arm/cpu/arm926ejs/lp
: Gregory CLEMENT
---
drivers/net/lpc32xx_eth.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c
index 2d15fc8db2..ec5184edf8 100644
--- a/drivers/net/lpc32xx_eth.c
+++ b/drivers/net/lpc32xx_eth.c
@@ -373,7 +373,8
Miquel Raynal writes:
Hi Miquel,
> Hi Gregory,
>
> Gregory CLEMENT wrote on Wed, 17 Apr 2019
> 11:09:42 +0200:
>
>> The purpose of "mtd: nand: raw: allow to disable unneeded ECC layouts"
>> was to allow disabling the default ECC layouts if a driver is k
l the NAND drivers not providing their own ECC layout this
patch fix this situation.
It was tested with the lpc32xx_nand_slc driver.
Fixes: a38c3af868 ("mtd: nand: raw: allow to disable unneeded ECC layouts")
Reviewed-by: Miquel Raynal
Signed-off-by: Gregory CLEMENT
---
Changelog:
v1 ->
the driver nand that not providing their ecc layout, this
patch fix this sitution.
It was tested with the lpc32xx_nand_slc driver.
Fixes: a38c3af868 ("mtd: nand: raw: allow to disable unneeded ECC layouts")
Signed-off-by: Gregory CLEMENT
---
drivers/mtd/nand/raw/nand_base.c | 4 ++-
ort10" },
> + { PORT11, "port11" },
> + { PORT12, "port12" },
> + { PORT13, "port13" },
> + { PORT14, "port14" },
> + { PORT15, "port15" },
> + { PORT16, "port16" },
> + { PORT17, "port17" },
> + { PORT18, "port18" },
> + { PORT19, "port19" },
> + { PORT20, "port20" },
> + { PORT21, "port21" },
> + { PORT22, "port22" },
> + { PORT23, "port23" },
> + { SYS, "sys" },
> + { ANA, "ana" },
> + { REW, "rew" },
> + { GCB, "gcb" },
> + { QS, "qs" },
> + { HSIO, "hsio" },
> + };
> +
> + if (!priv)
> + return -EINVAL;
> +
> + for (i = 0; i < ARRAY_SIZE(reg); i++) {
> + priv->regs[reg[i].id] = dev_remap_addr_name(dev, reg[i].name);
> + if (!priv->regs[reg[i].id]) {
> + debug
> + ("Error can't get regs base addresses for %s\n",
> + reg[i].name);
> + return -ENOMEM;
> + }
> + }
> +
> + /* Release reset in the CU-PHY */
> + writel(0, priv->regs[GCB] + GCB_DEVCPU_RST_SOFT_CHIP_RST);
> +
> + /* Ports with ext phy don't need to reset clk */
> + for (i = PORT0; i < MAX_INT_PORT; i++) {
> + if (i < PORT10)
> + clrbits_le32(priv->regs[i] + DEV_GMII_PORT_MODE_CLK,
> + DEV_GMII_PORT_MODE_CLK_PHY_RST);
> + else
> + clrbits_le32(priv->regs[i] + DEV_PORT_MODE_CLK,
> + DEV_PORT_MODE_CLK_PHY_RST);
> + }
> +
> + /* Wait for internal PHY to be ready */
> + if (wait_for_bit_le32(priv->regs[GCB] + GCB_MISC_STAT,
> + GCB_MISC_STAT_PHY_READY, true, 500, false))
> + return -EACCES;
> +
> + priv->bus[INTERNAL] = luton_mdiobus_init(dev, INTERNAL);
> +
> + for (i = 0; i < MAX_INT_PORT; i++) {
> + phy_connect(priv->bus[INTERNAL], i, dev,
> + PHY_INTERFACE_MODE_NONE);
> + }
> +
> + /*
> + * coma_mode is need on only one phy, because all the other phys
> + * will be affected.
> + */
> + mscc_miim_write(priv->bus[INTERNAL], 0, 0, 31, 0x10);
> + mscc_miim_write(priv->bus[INTERNAL], 0, 0, 14, 0x800);
> + mscc_miim_write(priv->bus[INTERNAL], 0, 0, 31, 0);
> +
> + return 0;
> +}
> +
> +static int luton_remove(struct udevice *dev)
> +{
> + struct luton_private *priv = dev_get_priv(dev);
> + int i;
> +
> + for (i = 0; i < NUM_PHY; i++) {
> + mdio_unregister(priv->bus[i]);
> + mdio_free(priv->bus[i]);
> + }
> +
> + return 0;
> +}
> +
> +static const struct eth_ops luton_ops = {
> + .start= luton_start,
> + .stop = luton_stop,
> + .send = luton_send,
> + .recv = luton_recv,
> + .write_hwaddr = luton_write_hwaddr,
> +};
> +
> +static const struct udevice_id mscc_luton_ids[] = {
> + {.compatible = "mscc,vsc7527-switch", },
> + { /* Sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(luton) = {
> + .name = "luton-switch",
> + .id = UCLASS_ETH,
> + .of_match = mscc_luton_ids,
> + .probe= luton_probe,
> + .remove = luton_remove,
> + .ops = &luton_ops,
> + .priv_auto_alloc_size = sizeof(struct luton_private),
> + .platdata_auto_alloc_size = sizeof(struct eth_pdata),
> +};
> --
> 2.7.4
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
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This patch adds support for the Microsemi Ethernet switch present on
Ocelot SoCs.
Signed-off-by: Gregory CLEMENT
---
MAINTAINERS | 1 +
drivers/net/Kconfig | 7 +
drivers/net/Makefile| 1 +
drivers/net/ocelot_switch.c | 765
On some ocelots platform a workaround is needed in order to be able to
reset the switch without resetting the DDR.
Signed-off-by: Gregory CLEMENT
---
board/mscc/ocelot/ocelot.c | 24
1 file changed, 24 insertions(+)
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc
Now that network support is added for the ocelot platform, let's add it
in the default configuration.
Signed-off-by: Gregory CLEMENT
---
configs/mscc_ocelot_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig
Import Ethernet related nodes from Linux
Signed-off-by: Gregory CLEMENT
---
arch/mips/dts/mscc,ocelot.dtsi | 97 +
arch/mips/dts/ocelot_pcb123.dts | 20 +++
2 files changed, 117 insertions(+)
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc
- Use wait_for_bit_le32() (suggested by Stefan Roese)
- Use debug() instead of printf() for the debug messages in
mscc_switch_reset.
Gregory CLEMENT (4):
MIPS: mscc: ocelot: Add ethernet nodes for Ocelot
net: add MSCC Ocelot switch support
MIPS: mscc: ocelot: add switch reset support
c
Hi Daniel,
On mer., janv. 16 2019, Daniel Schwierzeck
wrote:
> Am 16.01.19 um 14:07 schrieb Gregory CLEMENT:
>> On some ocelots platform a workaround is needed in order to be able to
>> reset the switch without resetting the DDR.
>>
>> Signed-off-by: Gregory CLE
faddr);
>> +plat->phy_size[INTERNAL][i] = res.end - res.start;
>> +}
>> +
>> +return 0;
>> +}
>> +
>> +static int ocelot_probe(struct udevice *dev)
>> +{
>> +struct ocelot_private *priv = dev_get_priv(dev);
>> +int i;
>> +
&g
This patch adds support for the Microsemi Ethernet switch present on
Ocelot SoCs.
Signed-off-by: Gregory CLEMENT
---
MAINTAINERS | 1 +
drivers/net/Kconfig | 7 +
drivers/net/Makefile| 1 +
drivers/net/ocelot_switch.c | 837
Now that network support is added for the ocelot platform, let's add it
in the default configuration.
Signed-off-by: Gregory CLEMENT
---
configs/mscc_ocelot_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig
On some ocelots platform a workaround is needed in order to be able to
reset the switch without resetting the DDR.
Signed-off-by: Gregory CLEMENT
---
board/mscc/ocelot/ocelot.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/board/mscc/ocelot/ocelot.c b/board
Import Ethernet related nodes from Linux
Signed-off-by: Gregory CLEMENT
---
arch/mips/dts/mscc,ocelot.dtsi | 97 +
arch/mips/dts/ocelot_pcb123.dts | 20 +++
2 files changed, 117 insertions(+)
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc
to the DDR reset is part of the
switch subsystem. So we need ensure that the DDR is not reset during
the switch reset.
Gregory
Changelog:
v1 -> v2:
- Use wait_for_bit_le32() (suggested by Stefan Roese)
- Use debug() instead of printf() for the debug messages in
mscc_switch_reset.
Greg
Import Ethernet related nodes from Linux
Signed-off-by: Gregory CLEMENT
---
arch/mips/dts/mscc,ocelot.dtsi | 97 +
arch/mips/dts/ocelot_pcb123.dts | 20 +++
2 files changed, 117 insertions(+)
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc
of the
switch subsystem. So we need ensure that the DDR is not reset during
the switch reset.
Gregory
Gregory CLEMENT (4):
MIPS: mscc: ocelot: Add ethernet nodes for Ocelot
net: add MSCC Ocelot switch support
MIPS: mscc: ocelot: add switch reset support
configs: mscc_ocelot: add network
Now that network support is added for the ocelot platform, let's add it
in the default configuration.
Signed-off-by: Gregory CLEMENT
---
configs/mscc_ocelot_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig
This patch adds support for the Microsemi Ethernet switch present on
Ocelot SoCs.
Signed-off-by: Gregory CLEMENT
---
MAINTAINERS | 1 +
drivers/net/Kconfig | 7 +
drivers/net/Makefile| 1 +
drivers/net/ocelot_switch.c | 837
On some ocelots platform a workaround is needed in order to be able to
reset the switch without resetting the DDR.
Signed-off-by: Gregory CLEMENT
---
board/mscc/ocelot/ocelot.c | 28
1 file changed, 28 insertions(+)
diff --git a/board/mscc/ocelot/ocelot.c b/board
_match_ptr(jr2_pinctrl_of_match),
> + .probe = jr2_pinctrl_probe,
> + .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
> + .ops = &mscc_pinctrl_ops,
> +};
> diff --git a/drivers/pinctrl/mscc/pinctrl-luton.c
> b/drivers/pinctrl/mscc/pinctrl-luton.c
> index 7166588..8c636ff 100644
> --- a/drivers/pinctrl/mscc/pinctrl-luton.c
> +++ b/drivers/pinctrl/mscc/pinctrl-luton.c
> @@ -123,6 +123,19 @@ static const struct mscc_pin_data luton_pins[] = {
> LUTON_PIN(31),
> };
>
> +const unsigned long luton_gpios[] = {
> + [MSCC_GPIO_OUT_SET] = 0x00,
> + [MSCC_GPIO_OUT_CLR] = 0x04,
> + [MSCC_GPIO_OUT] = 0x08,
> + [MSCC_GPIO_IN] = 0x0c,
> + [MSCC_GPIO_OE] = 0x10,
> + [MSCC_GPIO_INTR] = 0x14,
> + [MSCC_GPIO_INTR_ENA] = 0x18,
> + [MSCC_GPIO_INTR_IDENT] = 0x1c,
> + [MSCC_GPIO_ALT0] = 0x20,
> + [MSCC_GPIO_ALT1] = 0x24,
> +};
> +
> static int luton_gpio_probe(struct udevice *dev)
> {
> struct gpio_dev_priv *uc_priv;
> @@ -146,7 +159,8 @@ int luton_pinctrl_probe(struct udevice *dev)
> int ret;
>
> ret = mscc_pinctrl_probe(dev, FUNC_MAX, luton_pins,
> - ARRAY_SIZE(luton_pins), luton_function_names);
> + ARRAY_SIZE(luton_pins), luton_function_names,
> + luton_gpios);
>
> if (ret)
> return ret;
> diff --git a/drivers/pinctrl/mscc/pinctrl-ocelot.c
> b/drivers/pinctrl/mscc/pinctrl-ocelot.c
> index 10f9b90..fb02061 100644
> --- a/drivers/pinctrl/mscc/pinctrl-ocelot.c
> +++ b/drivers/pinctrl/mscc/pinctrl-ocelot.c
> @@ -138,6 +138,19 @@ static const struct mscc_pin_data ocelot_pins[] = {
> OCELOT_PIN(21),
> };
>
> +const unsigned long ocelot_gpios[] = {
> + [MSCC_GPIO_OUT_SET] = 0x00,
> + [MSCC_GPIO_OUT_CLR] = 0x04,
> + [MSCC_GPIO_OUT] = 0x08,
> + [MSCC_GPIO_IN] = 0x0c,
> + [MSCC_GPIO_OE] = 0x10,
> + [MSCC_GPIO_INTR] = 0x14,
> + [MSCC_GPIO_INTR_ENA] = 0x18,
> + [MSCC_GPIO_INTR_IDENT] = 0x1c,
> + [MSCC_GPIO_ALT0] = 0x20,
> + [MSCC_GPIO_ALT1] = 0x24,
> +};
> +
> static int ocelot_gpio_probe(struct udevice *dev)
> {
> struct gpio_dev_priv *uc_priv;
> @@ -162,7 +175,8 @@ int ocelot_pinctrl_probe(struct udevice *dev)
>
> ret = mscc_pinctrl_probe(dev, FUNC_MAX, ocelot_pins,
>ARRAY_SIZE(ocelot_pins),
> - ocelot_function_names);
> + ocelot_function_names,
> + ocelot_gpios);
>
> if (ret)
> return ret;
> --
> 2.7.4
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
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pins = "GPIO_24", "GPIO_25";
> + function = "uart2";
> + };
> + };
> +
> + sgpio: gpio@1010150 {
> + compatible = "mscc,ocelot-sgpio";
> +
e & SPI_CPOL)
> + plat->sclk.flags |= GPIOD_ACTIVE_LOW;
> +
> + return 0;
> +}
> +
> static const struct udevice_id soft_spi_ids[] = {
> { .compatible = "spi-gpio" },
> { }
> @@ -254,5 +263,6 @@ U_BOOT_DRIVER(soft_spi) = {
> .ofdata_to_platdata
Hi Daniel,
On lun., déc. 17 2018, Daniel Schwierzeck wrote:
> Am 17.12.18 um 10:55 schrieb Gregory CLEMENT:
>> Hi Daniel,
>>
>> On dim., déc. 16 2018, Gregory CLEMENT wrote:
>>
>>> Hi Daniel,
>>>
>>> On sam., déc. 15 2018, Daniel
Hi Daniel,
On dim., déc. 16 2018, Gregory CLEMENT wrote:
> Hi Daniel,
>
> On sam., déc. 15 2018, Daniel Schwierzeck
> wrote:
>
>> Am 14.12.18 um 16:16 schrieb Gregory CLEMENT:
>>> Adding the support for the Luton boards PCB91 which share common code with
>
Hi Daniel,
On sam., déc. 15 2018, Daniel Schwierzeck wrote:
> Am 14.12.18 um 16:16 schrieb Gregory CLEMENT:
>> Adding the support for the Luton boards PCB91 which share common code with
>> the Ocelots boards, including board code, device tree and configuration.
>>
>
.
However, like yamon, they expect that rd_start and rd_size was passed by
the bootloader in the command line of the kernel.
Signed-off-by: Gregory CLEMENT
---
arch/mips/Kconfig | 4 +++
arch/mips/lib/bootm.c | 76 +++
2 files changed, 60 insertions
This family of SoCs are found in the Microsemi Switches solution and have
already a support in the linux kernel.
Signed-off-by: Gregory CLEMENT
---
MAINTAINERS | 7 +
arch/mips/Kconfig | 6 +
arch/mips/Makefile
Adding the support for 2 boards sharing common code for Ocelot chip:
PCB120 and PCB123
Signed-off-by: Gregory CLEMENT
---
MAINTAINERS | 5 +
arch/mips/dts/mscc,ocelot.dtsi | 152 +++
arch/mips/dts/mscc,ocelot_pcb.dtsi | 42
Adding the support for the Luton boards PCB91 which share common code with
the Ocelots boards, including board code, device tree and configuration.
Signed-off-by: Gregory CLEMENT
---
MAINTAINERS| 1 +
arch/mips/dts/luton_pcb091.dts | 36 ++
arch/mips/dts/mscc
As the Ocelots SoCs, this family of SoCs are found in the Microsemi
Switches solution.
Signed-off-by: Gregory CLEMENT
---
arch/mips/mach-mscc/Kconfig | 13 +
arch/mips/mach-mscc/Makefile | 1 +
arch/mips/mach-mscc/cpu.c | 14 +-
arch
This path add a new helper allowing to prefetch and lock instructions
into cache. This is useful very early in the boot when no RAM is
available yet.
Signed-off-by: Gregory CLEMENT
---
arch/mips/include/asm/cacheops.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch
Export create_tlb() as an inline function in mipsregs.h. It allows to
remove the declaration of the function from the board files.
Then it will allow also to use this function very early in the boot when
the stack is not usable.
Signed-off-by: Gregory CLEMENT
---
arch/mips/cpu/cpu.c
interrupt disabling
- fix the ddr init for luton
Gregory CLEMENT (7):
MIPS: move create_tlb() in an proper header: mipsregs.h
MIPS: Allow to prefetch and lock instructions into cache
MSCC: add support for Ocelot SoCs
MSCC: add support for Luton SoCs
MSCC: add board support for the Ocel
Hi Daniel,
On lun., déc. 10 2018, Daniel Schwierzeck wrote:
> Am 05.12.18 um 18:10 schrieb Gregory CLEMENT:
>> The kernels built for the Vcore III linux kernel have different
>> expectation in the way the data were passed.
>>
>> Unlike with yamon, the command line
nux.bk)"
>
> you should recheck all MTD related options due to some recent changes in
> mainline
It's OK all the MTD related option of this file are aligned with the
changes merged in mainline.
Thanks,
Gregory
--
Gregory Clement, Bootli
S0
>> +andiv1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS
>> +# Keep looping if zero (no lock bit yet)
>
> should be a C style comment
OK
Thanks,
Gregory
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
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e?
Yes, as explain above, it s done now.
>> +
>> +/*
>> + * Target offset base(s)
>> + */
>> +#define MSCC_IO_ORIGIN1_OFFSET 0x7000
>> +#define MSCC_IO_ORIGIN1_SIZE 0x0020
>> +#define MSCC_IO_ORIGIN2_OFFSET 0x7100
>> +#def
Hi,
On mar., oct. 09 2018, Gregory CLEMENT wrote:
> The VCore III SoCs such as the Luton but also the Ocelot can remap an SPI
> flash directly in memory. However, for writing in the flash the
> communication has to be done by software.
>
> Each of the signal used for the SPI a
differ.
Signed-off-by: Gregory CLEMENT
---
Hi,
I sent the second version _2_ months ago and did not get
anyfeedback. I hope this patch could be merge soon.
Thanks!
Changelog:
v2 -> v3:
- fix the return value of mscc_gpio_get_direction (reported by Lars
Povlsen)
v1 -> v2:
- use clrbi
yamon, they expect that rd_start and rd_size was passed by
the bootloader in the command line of the kernel, and besides that it
also wait for the root=/dev/ram0.
Signed-off-by: Gregory CLEMENT
---
arch/mips/lib/bootm.c | 78 ---
1 file changed, 58
Adding the support for the Luton boards PCB91 which share common code with
the Ocelots boards, including board code, device tree and configuration.
Signed-off-by: Gregory CLEMENT
---
MAINTAINERS| 1 +
arch/mips/dts/luton_pcb091.dts | 35 ++
arch/mips/dts/mscc
Adding the support for 2 boards sharing common code for Ocelot chip:
PCB120 and PCB123
Signed-off-by: Gregory CLEMENT
---
MAINTAINERS | 5 +
arch/mips/dts/mscc,ocelot.dtsi | 152 +++
arch/mips/dts/mscc,ocelot_pcb.dtsi | 42
This family of SoCs are found in the Microsemi Switches solution and have
already a support in the linux kernel.
Signed-off-by: Gregory CLEMENT
---
MAINTAINERS | 7 +
arch/mips/Kconfig | 6 +
arch/mips/Makefile
As the Ocelots SoCs, this family of SoCs are found in the Microsemi
Switches solution.
Signed-off-by: Gregory CLEMENT
---
arch/mips/mach-mscc/Kconfig | 13 +
arch/mips/mach-mscc/Makefile | 1 +
arch/mips/mach-mscc/cpu.c | 14 +-
arch
rst version
- remove more unused define in the platform header files
- use the automatic cache size detection instead of hard coding it
- reduce the tlb init to only two entries for the IO as needed by the
kernel
- remove the interrupt disabling
- fix the ddr init for luton
Gregory CLEMENT
This path add a new helper allowing to prefetch and lock instructions
into cache. This is useful very early in the boot when no RAM is
available yet.
Signed-off-by: Gregory CLEMENT
---
arch/mips/include/asm/cacheops.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch
Export create_tlb() as an inline function in mipsregs.h. It allows to
remove the declaration of the function from the board files.
Then it will allow also to use this function very early in the boot when
the stack is not usable.
Signed-off-by: Gregory CLEMENT
---
arch/mips/cpu/cpu.c
Hi Daniel,
On dim., oct. 28 2018, Daniel Schwierzeck wrote:
> Am 09.10.18 um 13:58 schrieb Gregory CLEMENT:
>> This family of SoCs are found in the Microsemi Switches solution and have
>> already a support in the linux kernel.
>>
>> Signed-off-by: Gregory CL
Hi Daniel,
On dim., oct. 28 2018, Daniel Schwierzeck wrote:
> Hi Gregory,
>
> sorry for the late response.
>
> Am 09.10.18 um 13:58 schrieb Gregory CLEMENT:
>> The kernels built for the Vcore III linux kernel have different
>> expectation in the way the data were
Hi Jagan,
On mar., oct. 09 2018, Gregory CLEMENT wrote:
> On some platforms, as the Ocelot ones, when wanting to control the CS
> through software, it is not possible to do it through the GPIO
> controller. Indeed, this signal is managed through a dedicated range of
> registers in
possible to
manage the CS at platform level and then using the appropriate registers.
Signed-off-by: Gregory CLEMENT
---
Changelog:
v1 -> v2
- Fix ocelot name
drivers/spi/designware_spi.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/designware_spi.c b/driv
Hi Daniel,
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> On 25.09.2018 15:17, Gregory CLEMENT wrote:
>> On some platforms, as the Ocelot ones, when wanting to control the CS
>> through software, it is not possible to do it through the GPIO
>> controller. Indeed, t
, the management of this pin
is done through this simple gpio driver.
Even if the main purpose of this driver is to be used by soft-spi, it can
still be used as a normal gpio driver but with limitation: for example
the first pin can't be used as output.
Signed-off-by: Gregory CLEMENT
---
Chan
differ.
Signed-off-by: Gregory CLEMENT
---
Changelog:
v1 -> v2:
- use clrbits and setbits from MIPS
- use const and static when needed
- fix style
- use dev_remap_addr
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/mscc/Kcon
yamon, they expect that rd_start and rd_size was passed by
the bootloader in the command line of the kernel, and besides that it
also wait for the root=/dev/ram0.
Signed-off-by: Gregory CLEMENT
---
arch/mips/lib/bootm.c | 77 ---
1 file changed, 57
Adding the support for 2 boards sharing common code for Ocelot chip:
PCB120 and PCB123
Signed-off-by: Gregory CLEMENT
---
arch/mips/dts/mscc,ocelot.dtsi | 132 +++
arch/mips/dts/mscc,ocelot_pcb.dtsi | 33 +++
arch/mips/dts/ocelot_pcb120.dts | 12
Adding the support for the Luton boards PCB91 which share common code with
the Ocelots boards, including board code, device tree and configuration.
Signed-off-by: Gregory CLEMENT
---
arch/mips/dts/luton_pcb091.dts | 36 ++
arch/mips/dts/mscc,luton.dtsi | 87
This family of SoCs are found in the Microsemi Switches solution and have
already a support in the linux kernel.
Signed-off-by: Gregory CLEMENT
---
arch/mips/Kconfig | 6 +
arch/mips/Makefile| 1 +
arch/mips/mach-mscc/Kconfig
As the Ocelots SoCs, this family of SoCs are found in the Microsemi
Switches solution.
Signed-off-by: Gregory CLEMENT
---
arch/mips/mach-mscc/Kconfig | 13 +
arch/mips/mach-mscc/Makefile | 1 +
arch/mips/mach-mscc/cpu.c | 13 +
arch
for luton
Gregory CLEMENT (7):
MIPS: move create_tlb() in an proper header: mipsregs.h
MIPS: Allow to prefetch and lock instructions into cache
MSCC: add support for Ocelot SoCs
MSCC: add support for Luton SoCs
MSCC: add board support for the Ocelots based evaluation boards
MSCC: add
This path add a new helper allowing to prefetch and lock instructions
into cache. This is useful very early in the boot when no RAM is
available yet.
Signed-off-by: Gregory CLEMENT
---
arch/mips/include/asm/cacheops.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch
Export create_tlb() as an inline function in mipsregs.h. It allows to
remove the declaration of the function from the board files.
Then it will allow also to use this function very early in the boot when
the stack is not usable.
Signed-off-by: Gregory CLEMENT
---
arch/mips/cpu/cpu.c
Hi Daniel,
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>> The kernels built for the Vcore III linux kernel have different
>> expectation in the way the data were passed.
>>
>> Unlike with yamon, the command line
Hi Daniel,
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>> Add common configuration header for the VCore III SoCs (currently Ocelot
>> and Luton), but also the defconfig for the evaluation boards of these
>> SoCs.
Hi Daniel,
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>> Adding device tree for Ocelot SoC (extract from Linux) and the 2
>> evaluation boards using this SoC: PCB120 and PCB132.
>>
>> Adding device tree for
Hi Marek,
On jeu., sept. 27 2018, Marek Vasut wrote:
> On 09/25/2018 03:01 PM, Gregory CLEMENT wrote:
>> Adding the support for 3 boards sharing common code:
>> - PCB120 and PCB 123 for Ocelot chip
>> - PCB 91 for Luton chip
>>
>> Signed-off-by: Grego
Hi Daniel,
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>> Adding the support for 3 boards sharing common code:
>> - PCB120 and PCB 123 for Ocelot chip
>> - PCB 91 for Luton chip
>>
[...]
>> diff --
Hi Daniel,
I am bout to send a new version of the series, but befor I am going to
answer to the pending point I didn't already address in my email 10 days
ago.
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> Hi Gregory,
>
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>&g
Gregory,
>
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>> These families of SoCs are found in the Microsemi Switches solution.
>>
>> Currently the support for two families support is added:
>> - Ocelot (VSC7513, VSC7514) already supported in Linux
>> - L
-off-by: Gregory CLEMENT
---
Hi,
Actually this is the second version of this patch.
Compared to the previous version which did not reach the mailing list,
I remove a lot of unused defines in the header.
They can be add later when needed.
Sorry for the noise
Gregory
arch/mips/Kconfig
Hi,
On mar., sept. 25 2018, Gregory CLEMENT wrote:
> Hello,
>
> This series add the support of 2 SoCs: Ocelot and Luton from
> Microsemi. Both of them belongs to the same family Vcore III.
>
> We found them on various advanced switches product.
>
> The support for
possible to
manage the CS at platform level and then using the appropriate registers.
Signed-off-by: Gregory CLEMENT
---
drivers/spi/designware_spi.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index d8b73ea326
, the management of this pin
is done through this simple gpio driver.
Even if the main purpose of this driver is to be used by soft-spi, it can
still be used as a normal gpio driver but with limitation: for example
the first pin can't be used as output.
Signed-off-by: Gregory CLEMENT
---
dr
differ.
Signed-off-by: Gregory CLEMENT
---
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/mscc/Kconfig | 22 +++
drivers/pinctrl/mscc/Makefile | 5 +
drivers/pinctrl/mscc/mscc-common.c| 258
Add common configuration header for the VCore III SoCs (currently Ocelot
and Luton), but also the defconfig for the evaluation boards of these
SoCs.
Signed-off-by: Gregory CLEMENT
---
configs/mscc_luton_defconfig | 66 +
configs/mscc_ocelot_defconfig| 57
yamon, they expect that rd_start and rd_size was passed by
the bootloader in the command line of the kernel, and besides that it
also wait for the root=/dev/ram0.
Signed-off-by: Gregory CLEMENT
---
arch/mips/lib/bootm.c | 62 +--
1 file changed, 42
Adding device tree for Ocelot SoC (extract from Linux) and the 2
evaluation boards using this SoC: PCB120 and PCB132.
Adding device tree for Luton SoC (not yet in Linux) and the evaluation
boards using this SoC: PCB91.
Signed-off-by: Gregory CLEMENT
---
arch/mips/dts/luton_pcb091.dts | 36
Adding the support for 3 boards sharing common code:
- PCB120 and PCB 123 for Ocelot chip
- PCB 91 for Luton chip
Signed-off-by: Gregory CLEMENT
---
board/mscc/common/board.c | 29 +
board/mscc/luton/Kconfig | 14 ++
board/mscc/luton/Makefile | 4
Export create_tlb() as an inline function in mipsregs.h. It allows to
remove the declaration of the function from the board files.
Then it will allow also to use this function very early in the boot when
the stack is not usable.
Signed-off-by: Gregory CLEMENT
---
arch/mips/cpu/cpu.c
.
Thanks,
Gregory
Gregory CLEMENT (6):
MIPS: move create_tlb() in an proper header: mipsregs.h
MSCC: add support for VCoreIII SoCs
MSCC: add board support for the VCoreIII based evaluation boards
MSCC: add device tree for Ocelot and Luton (boards and SoCs)
MSCC: add configuration for Ocelot
Hi Adam,
On mer., juil. 26 2017, Adam Ford wrote:
> This converts the following to Kconfig:
>CONFIG_USB_ETHER
>CONFIG_USB_ETHER_RNDIS
>
> Signed-off-by: Adam Ford
For the VInCo platform
Acked-by: Gregory CLEMENT
Thanks,
Gregory
>
> diff --git a/configs/am
Hi Andreas,
On jeu., févr. 18 2016, Andreas Bießmann wrote:
> Dear Gregory CLEMENT,
>
> Gregory CLEMENT writes:
>>The Versatile Industrial Communication platform is a community oriented
>>board from Landis + Gyr. It comes with:
>>- an RS-485 port
>>- 2 Et
Hi Andreas,
On jeu., janv. 21 2016, "Andreas Bießmann"
wrote:
> Hi Gregory,
>
> On 21.01.2016 12:08, Gregory CLEMENT wrote:
>> Hello all,
>>
>> On mer., déc. 16 2015, Gregory CLEMENT
>> wrote:
>>
>>> The Versatile Industrial Com
Hello all,
On mer., déc. 16 2015, Gregory CLEMENT
wrote:
> The Versatile Industrial Communication platform is a community oriented
> board from Landis + Gyr. It comes with:
> - an RS-485 port
> - 2 Ethernet ports
> - a wireless M-BUS
> - a 4G modem
> - a 4MB SPI
The Versatile Industrial Communication platform is a community oriented
board from Landis + Gyr. It comes with:
- an RS-485 port
- 2 Ethernet ports
- a wireless M-BUS
- a 4G modem
- a 4MB SPI flash
- a 4GB eMMC
Signed-off-by: Gregory CLEMENT
Acked-by: Nicolas Ferre
---
Hi again,
Some of my
The Versatile Industrial Communication platform is a community oriented
board from Landis + Gyr. It comes with:
- an RS-485 port
- 2 Ethernet ports
- a wireless M-BUS
- a 4G modem
- a 4MB SPI flash
- a 4GB eMMC
Signed-off-by: Gregory CLEMENT
---
arch/arm/mach-at91/Kconfig | 6 ++
board/l+g
the gmac with
these SoCs.
Suggested-by: Nicolas Ferre
Signed-off-by: Gregory CLEMENT
---
Hi,
in this v3, I fixed the sama5d2 typo and the missing brace.
I also took care of the cpu_is_* symbols which may not be defined
depending of the choice of the SoC.
Gregory
drivers/net/macb.c | 21
Hi Nicolas,
On mer., déc. 16 2015, Nicolas Ferre wrote:
> Le 16/12/2015 11:27, Gregory CLEMENT a écrit :
>> During the initialization of PHY the gigabit bit capable is set if the
>> controller is a GEM. However, for sama5d2 and sama5d4, the GEM is
>> configured t
Hi Thomas,
On mer., déc. 16 2015, Thomas Petazzoni
wrote:
> Dear Gregory CLEMENT,
>
> On Wed, 16 Dec 2015 11:34:00 +0100, Gregory CLEMENT wrote:
>
>> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
>> index c333647..d7e36cb 100644
>> --
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