On some ocelots platform a workaround is needed in order to be able to
reset the switch without resetting the DDR.
Signed-off-by: Gregory CLEMENT <gregory.clem...@bootlin.com>
---
board/mscc/ocelot/ocelot.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
index 0f7a532158..88f59e8044 100644
--- a/board/mscc/ocelot/ocelot.c
+++ b/board/mscc/ocelot/ocelot.c
@@ -18,6 +18,34 @@ enum {
BOARD_TYPE_PCB123,
};
+void mscc_switch_reset(bool enter)
+{
+ u32 reg, count = 0;
+
+ /* Nasty workaround to avoid GPIO19 (DDR!) being reset */
+ mscc_gpio_set_alternate(19, 2);
+
+ printf("applying SwC reset\n");
+
+ writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
+ writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
+
+ do {
+ reg = readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
+ count++;
+ } while (reg & PERF_SOFT_RST_SOFT_CHIP_RST);
+
+ printf("SwC reset done - reg = 0x%08x, count %u\n", reg, count);
+
+ /*
+ * Reset GPIO19 mode back as regular GPIO, output, high (DDR
+ * not reset) (Order is important)
+ */
+ setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
+ writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
+ mscc_gpio_set_alternate(19, 0);
+}
+
void board_debug_uart_init(void)
{
/* too early for the pinctrl driver, so configure the UART pins here */
--
2.20.1
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