The match controller register is not cleared during
initialization. However, some bits of this register may reset the TC if
tnMRx match it.
As we can't make any assumption about how U-Boot is launched by the first
stage bootloader (such as S1L) clearing this register ensure that the
timers work as expected.
Signed-off-by: Gregory CLEMENT <gregory.clem...@bootlin.com>
---
arch/arm/cpu/arm926ejs/lpc32xx/timer.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
b/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
index 404ccbb716..b3ca686040 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
@@ -33,6 +33,9 @@ static void lpc32xx_timer_reset(struct timer_regs *timer, u32
freq)
/* Set prescale counter value */
writel((get_periph_clk_rate() / freq) - 1, &timer->pr);
+
+ /* Ensure that the counter is not reset when matching TC */
+ writel(0, &timer->mcr);
}
static void lpc32xx_timer_count(struct timer_regs *timer, int enable)
--
2.20.1
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