On Mon, 2020-03-16 at 20:06 +0100, Marek Vasut wrote:
> On 3/16/20 8:04 PM, Simon Goldschmidt wrote:
> > Am 16.03.2020 um 19:04 schrieb Dalon L Westergreen:
> > >
> > > On Thu, 2020-03-12 at 16:57 +0100, Marek Vasut wrote:
> > > > On 3/1
On Thu, 2020-03-12 at 16:57 +0100, Marek Vasut wrote:
> On 3/12/20 4:54 PM, Dalon L Westergreen wrote:
> [...]
>
> (thanks for fixing your mailer :))
>
> > > > > > > The problem was that this was causing weird sporadic hangs on
> > > > > >
e:
> > > > > On 3/9/20 9:50 AM, Ley Foon Tan wrote:
> > > > > > On Thu, Feb 13, 2020 at 2:52 AM Dalon L Westergreen
> > > > > > wrote:
> > > > > > > I am reading through this thread, and want to point out that it is
> > >
On Wed, 2020-02-19 at 18:11 +0100, Marek Vasut wrote:
> On 2/19/20 1:25 PM, chee.hong@intel.com wrote:
> > From: Chee Hong Ang
> > Add board_fit_config_name_match() for matching board name withdevice tree
> > files in FIT image. This will ensure correct DTBfile is loaded for different
> > b
I am reading through this thread, and want to point out that it is not that the
FPGA bridge need be actively used in the fpga, but
rather that this port be configured in the FPGA configuration. This is an
important distinction, ecery FPGA design that
instantiates the HPS does configure the F2S Bri
On Tue, 2019-12-03 at 14:45 +, Ang, Chee Hong wrote:
> > On Tue, Dec 3, 2019 at 2:37 AM Ang, Chee Hong <
> > chee.hong@intel.com
> > >
> > wrote:
> > > > Am 02.12.2019 um 17:10 schrieb Ang, Chee Hong:
> > > > > > On Mon, Dec 2, 2019 at 4:18 PM Ang, Chee Hong
> > > > > > <
> > > > > > che
On Thu, 2019-10-24 at 16:29 +0200, Simon Goldschmidt wrote:
> On Thu, Oct 24, 2019 at 4:25 PM Dalon L Westergreen<
> dalon.westergr...@linux.intel.com> wrote:
> >
> > On Wed, 2019-10-23 at 21:22 +0200, Simon Goldschmidt wrote:
> > Am 23.10.2019 um 18:
On Wed, 2019-10-23 at 21:22 +0200, Simon Goldschmidt wrote:
> Am 23.10.2019 um 18:03 schrieb Dalon L Westergreen:
> > On Tue, 2019-10-22 at 19:13 +0200, Simon Goldschmidt wrote:
> > > Dalon L Westergreen > > dalon.westergr...@linux.intel.com>> schrieb am Di., 2
On Tue, 2019-10-22 at 19:13 +0200, Simon Goldschmidt wrote:
> Dalon L Westergreen schrieb am Di., 22.
> Okt. 2019, 19:10:
> > I mentioned this before, it would be great to not rely on the generated
> > files
> > and do this based purely on the handoff data generated du
I mentioned this before, it would be great to not rely on the generated filesand
do this based purely on the handoff data generated during a quartusbuild. Did
you look at the python source i pointed you to?
--dalon
On Tue, 2019-10-15 at 22:10 +0200, Simon Goldschmidt wrote:
> This new tool convert
On Sat, 2019-10-05 at 21:40 +0200, Simon Goldschmidt wrote:
> Am 27.09.2019 um 20:27 schrieb Dalon Westergreen:
> > From: Dalon Westergreen
> > Stratix10 requires a hex image of the spl plus spl devicetree offset tothe
> > Stratix10 onchip memory located at SPL_TEXT_BASE. This patch addsa target
On Sat, 2019-10-05 at 21:41 +0200, Simon Goldschmidt wrote:
> Am 27.09.2019 um 20:27 schrieb Dalon Westergreen:
> > From: Dalon Westergreen
> > CONFIG_OF_EMBED was primarily enabled to support the stratix10spl hex file
> > requirements. Since this option now produces awarning during build, and th
On Mon, 2019-10-07 at 16:45 +0200, Simon Goldschmidt wrote:
> There's something wrong with your mailer: indentation of replies doesn't
> seemto work. It gets kind of hard to read who wrote what...
> On Mon, Oct 7, 2019 at 4:34 PM Dalon L Westergreen<
> dalon.westergr.
On Mon, 2019-10-07 at 07:49 -0700, Dalon L Westergreen wrote:
> On Mon, 2019-10-07 at 16:06 +0200, Marek Vasut wrote:
> > On 10/7/19 4:03 PM, Dalon L Westergreen wrote:
> > > On Sat, 2019-10-05 at 16:23 -0700, Dalon L Westergreen wrote:
> > > > On Sat, 2019-10-05 at
On Mon, 2019-10-07 at 16:06 +0200, Marek Vasut wrote:
> On 10/7/19 4:03 PM, Dalon L Westergreen wrote:
> > On Sat, 2019-10-05 at 16:23 -0700, Dalon L Westergreen wrote:
> > > On Sat, 2019-10-05 at 01:47 +0200, Marek Vasut wrote:
> > > > On 10/5/19 12:30 AM, Dalon Wes
On Sun, 2019-10-06 at 20:05 +0200, Simon Goldschmidt wrote:
> Am 06.10.2019 um 19:44 schrieb Dalon L Westergreen:
> > On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> > > On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > > > On Sat, 2019-10-05 at
On Sat, 2019-10-05 at 16:23 -0700, Dalon L Westergreen wrote:
> On Sat, 2019-10-05 at 01:47 +0200, Marek Vasut wrote:
> > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > From: Dalon Westergreen Sync devicetree from
> > > 5.2 kernel.
> >
> > Linux 5.3 wa
On Sat, 2019-10-05 at 01:49 +0200, Marek Vasut wrote:
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen
> > Add a common u-boot devicetree include file for the SocFPGAArria10 device.
>
> Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basicallythe same
> thi
On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> > > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > > From: Dalon Westergreen Generic handoff
>
On Sun, 2019-10-06 at 20:05 +0200, Simon Goldschmidt wrote:
> Am 06.10.2019 um 19:44 schrieb Dalon L Westergreen:
> > On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> > > On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > > > On Sat, 2019-10-05 at
On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> > > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > > From: Dalon Westergreen Generic handoff
>
On Sat, 2019-10-05 at 01:49 +0200, Marek Vasut wrote:
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen
> > Add a common u-boot devicetree include file for the SocFPGAArria10 device.
>
> Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basicallythe same
> thi
On Sat, 2019-10-05 at 01:47 +0200, Marek Vasut wrote:
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen
> > Sync devicetree from 5.2 kernel.
>
> Linux 5.3 was already released, can you update this ?Also, make sure to list
> the exact commit ID in the commit message wheni
On Sat, 2019-10-05 at 01:47 +0200, Marek Vasut wrote:
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen
> > Add a script to process hps handoff data and generate a headerfor inclusion
> > in u-boot specific devicetree addons. The headershould be included in the
> > top l
On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen
> > Generic handoff devicetree include uses a header generated bythe qts-filter-
> > a10.sh script in mach-socfpga. The scriptcreates the header based on design
> > sp
On Tue, 2019-06-04 at 08:12 +0200, Simon Goldschmidt wrote:
> On Tue, Jun 4, 2019 at 7:58 AM See, Chin Liang
> wrote:
> > On Tue, 2019-06-04 at 07:13 +0200, Simon Goldschmidt wrote:
> > > On Tue, Jun 4, 2019 at 1:57 AM Dalon Westergreen<
> > > dalon.westergr...@linux.intel.com> wrote:
> > > > From
On Tue, 2019-06-04 at 02:00 +0200, Marek Vasut wrote:
> On 6/4/19 1:57 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen <
> > dalon.westergr...@intel.com
> > >
> >
> > Some architectures, Stratix10, require a hex formatted spl that combines
> > the spl image and dtb. This adds a target to
On Sat, 2019-03-30 at 15:18 -0600, Simon Glass wrote:
> Hi,
> On Fri, 22 Mar 2019 at 09:32, Dalon Westergreen<
> dalon.westergr...@linux.intel.com> wrote:
> > From: Dalon Westergreen
> > Some architectures, Stratix10, require a hex formatted spl that combinesthe
> > spl image and dtb. This adds a
On Fri, 2019-03-22 at 10:11 +0800, Simon Glass wrote:
> Hi,
>
> On Fri, 22 Mar 2019 at 05:37, Marek Vasut wrote:
> > On 3/21/19 5:37 PM, Dalon L Westergreen wrote:
> > > On Thu, 2019-03-21 at 16:48 +0100, Marek Vasut wrote:
> > > > On 3/21/19 3:33 PM, Dalon L
On Wed, 2019-03-20 at 18:09 +0100, Marek Vasut wrote:
> On 3/20/19 4:40 PM, Dalon Westergreen wrote:
> > From: Dalon Westergreen
> >
> > The sfp file is only valid for Gen5 (Cyclone5 & Arria5) and Arria10
> > devices. The file should only be built for these devices.
> >
> > Signed-off-by: Dalon
On Tue, 2019-02-26 at 16:42 +0100, Michal Simek wrote:
> On 26. 02. 19 15:28, Chee, Tien Fong wrote:
> > On Tue, 2019-02-26 at 15:06 +0100, Michal Simek wrote:
> > > On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote:
> > > > From: Tien Fong Chee
> > > >
> > > > This patch adds description on pro
On Wed, 2019-02-13 at 17:10 +0100, Marek Vasut wrote:
> On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> > From: Tien Fong Chee
> >
> > Add default fitImage file bundling FPGA bitstreams for Arria10.
> >
> > Signed-off-by: Tien Fong Chee
> >
> > ---
> >
> > changes for v8
> > - Changed t
On Tue, 2019-02-12 at 11:17 +0100, Marek Vasut wrote:
> On 2/12/19 11:13 AM, Chee, Tien Fong wrote:
> > On Tue, 2019-02-12 at 10:43 +0100, Marek Vasut wrote:
> > > On 2/12/19 10:35 AM, Chee, Tien Fong wrote:
> > > [...]
> > >
> > > > > my preference for the fit image would be
> > > > >
> > > > >
On Sat, 2019-02-09 at 11:02 +0100, Marek Vasut wrote:
> On 2/8/19 11:51 PM, Dalon L Westergreen wrote:
> > On Fri, 2019-02-08 at 21:36 +0100, Simon Goldschmidt wrote:
> > >
> > > Am Fr., 8. Feb. 2019, 21:28 hat Dalon L Westergreen <
> > > dalon.westergr...@l
On Mon, 2019-02-11 at 12:01 +0100, Marek Vasut wrote:
> On 2/11/19 6:36 AM, Chee, Tien Fong wrote:
> > On Tue, 2019-02-05 at 09:46 +0100, Marek Vasut wrote:
> > > On 2/1/19 5:02 PM, Chee, Tien Fong wrote:
> > > > On Fri, 2019-02-01 at 09:25 +0100, Marek Vasut wrote:
> > > > > On 2/1/19 4:48 AM, Che
On Fri, 2019-02-08 at 21:36 +0100, Simon Goldschmidt wrote:
>
>
> Am Fr., 8. Feb. 2019, 21:28 hat Dalon L Westergreen <
> dalon.westergr...@linux.intel.com> geschrieben:
> > On Thu, 2019-02-07 at 22:23 +0100, Simon Goldschmidt wrote:
> > > To clean up reset hand
On Fri, 2019-02-01 at 12:02 -0800, Dalon L Westergreen wrote:
> On Sat, 2019-02-02 at 00:02 +0800, Chee, Tien Fong wrote:
> > On Fri, 2019-02-01 at 09:25 +0100, Marek Vasut wrote:
> > > On 2/1/19 4:48 AM, Chee, Tien Fong wrote:
> > > > On Thu, 2019-01-31 at
On Thu, 2019-01-31 at 22:51 +0800, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add FPGA driver to support program FPGA with FPGA bitstream loading from
> filesystem. The driver are designed based on generic firmware loader
> framework. The driver can handle FPGA program operation f
On Sat, 2019-02-02 at 00:02 +0800, Chee, Tien Fong wrote:
> On Fri, 2019-02-01 at 09:25 +0100, Marek Vasut wrote:
> > On 2/1/19 4:48 AM, Chee, Tien Fong wrote:
> > > On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
> > > > On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> > > > >
> > > >
On Tue, 2018-11-20 at 21:54 +0100, Simon Goldschmidt wrote:
> On 20.11.2018 20:33, Marek Vasut wrote:
> > On 11/20/2018 08:22 PM, Simon Goldschmidt wrote:
> > > From: Simon Goldschmidt
> > >
> > > On socfpga gen5, a warm reboot from Linux currently triggers a warm
> > > reset via reset manager ct
On Mon, 2018-10-22 at 22:48 +0200, Simon Goldschmidt wrote:
> On 18.10.2018 23:04, Marek Vasut wrote:
>
> On 10/18/2018 10:20 PM, Simon Goldschmidt wrote:
>
>
> Marek Vasut mailto:marek.va...@gmail.com>>
> schrieb am Do., 18. Okt. 2018, 22:15:
>
> On 10/18/2018 09:28 PM, Simon Goldschmidt
On Thu, 2018-09-20 at 09:25 -0400, Thomas Epperson wrote:
> I've done some troubleshooting on warm resets and determined that the ocramis
> not being set correctly for warm reset to run properly (it hangs theprocessor
> on my de0-nano-soc board).I think it should be not enabled or fully setup so
>
On Wed, 2018-09-12 at 02:03 +0200, Marek Vasut wrote:
> On 09/12/2018 01:55 AM, Dalon L Westergreen wrote:
> On Tue, 2018-09-11 at 23:55 +0200, Marek Vasut wrote:
> On 09/10/2018 07:28 PM, Dalon Westergreen wrote:The dtb should be embedded in
> the u-boot-spl image so thatthe CONFIG_S
On Tue, 2018-09-11 at 23:55 +0200, Marek Vasut wrote:
> On 09/10/2018 07:28 PM, Dalon Westergreen wrote:
> The dtb should be embedded in the u-boot-spl image so thatthe
> CONFIG_SPL_TARGET of spl/u-boot-spl.hex includes it.
> This also affects the main u-boot image, so
> adjustCONFIG_SPL_FS_LOAD_PA
On Tue, 2018-09-11 at 15:52 +0200, Marek Vasut wrote:
> On 09/11/2018 03:28 PM, Dalon L Westergreen wrote:
> On Tue, 2018-09-11 at 11:31 +0200, Marek Vasut wrote:
> On 09/10/2018 10:41 PM, Dalon Westergreen wrote:Incorrect type of size
> variable results in 0 beingreturned for sdram s
On Tue, 2018-09-11 at 11:31 +0200, Marek Vasut wrote:
> On 09/10/2018 10:41 PM, Dalon Westergreen wrote:
> Incorrect type of size variable results in 0 beingreturned for sdram sizes
> greater than or equal to4GB.
> Signed-off-by: Dalon Westergreen ---
> drivers/ddr/altera/sdram_s10.c | 2 +- 1 file
On Mon, 2018-09-10 at 20:14 +0200, Simon Goldschmidt wrote:
> On 10.09.2018 19:28, Dalon Westergreen wrote:
> The dtb should be embedded in the u-boot-spl image so that
> the CONFIG_SPL_TARGET of spl/u-boot-spl.hex includes it.
>
> This also affects the main u-boot image, so adjust
> CONFIG_SPL_FS
On Mon, 2018-09-10 at 20:06 +0200, Simon Goldschmidt wrote:
> On 10.09.2018 19:28, Dalon Westergreen wrote:
> This patch set adds a possible hex output of the
> u-boot-spl elf and enables said output for the
> Intel Stratix10 device. Stratix10 requires a hex
> output of the elf for creating the se
On Fri, 2018-09-07 at 18:25 +0200, Marek Vasut wrote:
> On 09/07/2018 06:15 PM, Dalon L Westergreen wrote:
> On Thu, 2018-09-06 at 23:56 +0200, Marek Vasut wrote:
> On 09/06/2018 11:26 PM, Dalon L Westergreen wrote:
> On Thu, 2018-09-06 at 15:41 +0200, Marek Vasut wrote:
> On 09/0
On Thu, 2018-09-06 at 23:56 +0200, Marek Vasut wrote:
> On 09/06/2018 11:26 PM, Dalon L Westergreen wrote:On Thu, 2018-09-06 at 15:41
> +0200, Marek Vasut wrote:On 09/06/2018 03:39 PM, Dalon L Westergreen wrote:On
> Thu, 2018-09-06 at 12:09 +0200, Marek Vasut wrote:On 09/06/2018 05:02 AM
On Thu, 2018-09-06 at 15:41 +0200, Marek Vasut wrote:
> On 09/06/2018 03:39 PM, Dalon L Westergreen wrote:
>
> On Thu, 2018-09-06 at 12:09 +0200, Marek Vasut wrote:
>
> On 09/06/2018 05:02 AM, Dalon Westergreen wrote:
> Stratix10 requires a hex image of the spl for boot.
On Thu, 2018-09-06 at 15:41 +0200, Marek Vasut wrote:
> On 09/06/2018 03:39 PM, Dalon L Westergreen wrote:
> On Thu, 2018-09-06 at 12:09 +0200, Marek Vasut wrote:
> On 09/06/2018 05:02 AM, Dalon Westergreen wrote:Stratix10 requires a hex image
> of the spl for boot. The heximage is
On Thu, 2018-09-06 at 07:51 +0200, Simon Goldschmidt wrote:
> On Thu, Sep 6, 2018 at 5:04 AM Dalon Westergreen wrote:
>
> Stratix10 requires a hex image of the spl for boot. The heximage is added to
> the FPGA configuration image and loaded tothe processor memory by the
> configuration engine.
>
On Thu, 2018-09-06 at 12:09 +0200, Marek Vasut wrote:
> On 09/06/2018 05:02 AM, Dalon Westergreen wrote:
> Stratix10 requires a hex image of the spl for boot. The heximage is added to
> the FPGA configuration image and loaded tothe processor memory by the
> configuration engine.
> v2: -> add CONF
On Thu, 2018-09-06 at 12:08 +0200, Marek Vasut wrote:
> On 09/06/2018 05:02 AM, Dalon Westergreen wrote:
>
> Only the Cyclone5/Arria5 and Arria10 devices require the sfp
> formated image for booting. This path ensures that the file is
> only generated for those devices.
>
> Signed-off-by: Dalon W
On Tue, 2018-08-28 at 17:51 +0200, Marek Vasut wrote:
> On 08/28/2018 05:43 PM, Dalon L Westergreen wrote:
>
> On Tue, 2018-08-28 at 01:54 +0200, Marek Vasut wrote:
>
> On 08/28/2018 12:03 AM, Dalon L Westergreen wrote:
> On Mon, 2018-08-27 at 21:03 +0200, Marek Vasut wrote:
On Tue, 2018-08-28 at 01:54 +0200, Marek Vasut wrote:
> On 08/28/2018 12:03 AM, Dalon L Westergreen wrote:
> On Mon, 2018-08-27 at 21:03 +0200, Marek Vasut wrote:
> On 08/27/2018 05:30 PM, Dalon L Westergreen wrote:
> On Tue, 2018-08-21 at 05:52 +0200, Marek Vasut wrote:
> On 08/2
On Mon, 2018-08-27 at 21:03 +0200, Marek Vasut wrote:
> On 08/27/2018 05:30 PM, Dalon L Westergreen wrote:
> On Tue, 2018-08-21 at 05:52 +0200, Marek Vasut wrote:
> On 08/20/2018 11:04 PM, Dalon L Westergreen wrote:
> On Mon, 2018-08-20 at 20:33 +0200, Marek Vasut wrote:
> On 08/2
On Tue, 2018-08-21 at 05:52 +0200, Marek Vasut wrote:
> On 08/20/2018 11:04 PM, Dalon L Westergreen wrote:
> On Mon, 2018-08-20 at 20:33 +0200, Marek Vasut wrote:
> On 08/20/2018 03:54 PM, Dalon Westergreen wrote:
> Stratix10 requires a hex image of the spl for boot. The hex
> im
On Mon, 2018-08-20 at 20:33 +0200, Marek Vasut wrote:
> On 08/20/2018 03:54 PM, Dalon Westergreen wrote:
> Stratix10 requires a hex image of the spl for boot. The hex
> image is added to the FPGA configuration image and loaded to
> the processor memory by the configuration engine.
>
> Signed-off-
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