On Thu, 2019-10-24 at 16:29 +0200, Simon Goldschmidt wrote:
> On Thu, Oct 24, 2019 at 4:25 PM Dalon L Westergreen<
> dalon.westergr...@linux.intel.com> wrote:
> >
> > On Wed, 2019-10-23 at 21:22 +0200, Simon Goldschmidt wrote:
> > Am 23.10.2019 um 18:03 schrieb Dalon L Westergreen:
> >
> >
> > On Tue, 2019-10-22 at 19:13 +0200, Simon Goldschmidt wrote:
> >
> >
> > Dalon L Westergreen <
> > dalon.westergr...@linux.intel.com
> >
> >
> >
> > <mailto:
> > dalon.westergr...@linux.intel.com
> >
> > > > schrieb am Di., 22. Okt.
> >
> > 2019, 19:10:
> > I mentioned this before, it would be great to not rely on the
> > generated files
> > and do this based purely on the handoff data generated during a quartus
> > build. Did you look at the python source i pointed you to?
> >
> > No, not yet. But I don't think that will be a problem. I sent this
> > series mainly to discuss the dts format (boardspecific handoff dtsi vs
> > genetic dtsi plus boardspecific header file).
> >
> > The board specific dtsi does look cleaner, but i do like the simplicity
> > of generating the header in arria10.
> >
> > I could easily replicate what you do, generate the header, and use it to
> > create the dtsi.
> >
> > I'm not too fond myself of that tool I created, as it requires you to
> > have a compiler. I just was too lazy write a script for that.
> >
> > However, I would prefer having a script that does it. And if the sources
> > are quartus output files instead of existing qts files, my tool doesn't
> > work any more, anway.
> >
> > So I think we should come up with a script (e.g. sh or py) that parses
> > quartus output and creates a handoff dtsi (without a header). We'll only
> > need something different for converting existing qts files then...
> >
> > In that case, i would stick with adding a .h file along with a common
> > handoff dtsi as i didin the a10 filter script i sent the other week. I would
> > suggest your source is perfectfor migrating existing c5/a5 platforms.
>
> Why can't we change that a10 script to create handoff dtsi files as well?
I just dont like building the dtsi in source, the code to create a header is
simpler and cleaner. Froma files perspective, 1 dtsi + a header for each board,
or a dtsi for each board, not sure there is muchdifference either way. but
using headers keeps the utility simpler.
--dalon
> > Is there a preference for python? It would fit nicely b/c we could re-use
> > the codeI pointed out previously for binary parsing.
>
> Well, *my* preference would be to not depend on having gcc installed to
> convertfrom quartus output to dtsi. I just did that because C was easier toget
> started.
> I'm not a big fan of python, but since it's used everywhere in U-Boot,
> Ifigured it should be ok? Having a standard shell script do the job would
> evenlower the requirements of course.
> Regards,Simon
> > Dinh, Marek, Ley Foon, comments?
> > --dalon
> >
> > Regards,
> > Simon
> >
> >
> > --dalon
> >
> >
> > I still favor boardspecific handoff dtsi, but I would like to use the
> > same style for all socfpga flavours.
> >
> > Plus this tool is required to convert existing boards where we don't
> > have the quartus project files at hand.
> >
> > Regards,
> > Simon
> >
> >
> > --dalon
> >
> > On Tue, 2019-10-15 at 22:10 +0200, Simon Goldschmidt wrote:
> > This new tool converts handoff information from quartus to "*_handoff.dtsi"
> > devicetree files. This is in preparation to move from ad-hoc code in arch
> > that parses the 'qts' header files to drivers parsing the same information
> > from devicetree.
> >
> > Converting existing U-Boot 'qts' files is also supported.
> >
> > Signed-off-by: Simon Goldschmidt <
> > simon.k.r.goldschm...@gmail.com
> >
> >
> > <mailto:
> > simon.k.r.goldschm...@gmail.com
> >
> >
> > ---
> >
> > Changes in v2: None
> >
> > arch/arm/mach-socfpga/create_handoff_gen5.c | 660 ++++++++++++++++++++
> > arch/arm/mach-socfpga/qts-to-handoff.sh | 83 +++
> > 2 files changed, 743 insertions(+)
> > create mode 100644 arch/arm/mach-socfpga/create_handoff_gen5.c
> > create mode 100755 arch/arm/mach-socfpga/qts-to-handoff.sh
> >
> > diff --git a/arch/arm/mach-socfpga/create_handoff_gen5.c b/arch/arm/mach-
> > socfpga/create_handoff_gen5.c
> > new file mode 100644
> > index 0000000000..6ec436719d
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/create_handoff_gen5.c
> > @@ -0,0 +1,660 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * This is a host-tool that needs to be compiled per board and prints the
> > + * handoff.dtsi to stdout.
> > + */
> > +
> > +#include <stdio.h>
> > +#include <stdint.h>
> > +
> > +/* Define kernel types */
> > +typedef uint8_t u8;
> > +typedef uint32_t u32;
> > +
> > +#ifdef USE_QUARTUS_OUTPUT
> > +#ifdef ARRIA5
> > +#include "iocsr_config_arria5.c"
> > +#include "pinmux_config_arria5.c"
> > +#else
> > +#include "iocsr_config_cyclone5.c"
> > +#include "pinmux_config_cyclone5.c"
> > +#endif
> > +#include "pll_config.h"
> > +#include "sdram/sdram_config.h"
> > +#include "sequencer_auto.h"
> > +#include "sequencer_defines.h"
> > +#include "sequencer_auto_ac_init.c"
> > +#include "sequencer_auto_inst_init.c"
> > +#define RW_MGR(x) __RW_MGR_##x
> > +#else
> > +#define RW_MGR(x) RW_MGR_##x
> > +#include <iocsr_config.h>
> > +#include <pinmux_config.h>
> > +#include <pll_config.h>
> > +#include <sdram_config.h>
> > +#endif
> > +
> > +#include "include/mach/clock_manager_gen5.h"
> > +#include "include/mach/sdram_gen5.h"
> > +
> > +#ifndef ARRAY_SIZE
> > +#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
> > +#endif
> > +
> > +const char handoff_dtsi_hdr[] =
> > + "// SPDX-License-Identifier: GPL-2.0\n"
> > + "/*\n"
> > + " *<auto-generated>\n"
> > + " * This code was generated by a tool based on\n"
> > + " * handoffs from both Qsys and Quartus.\n"
> > + " *\n"
> > + " * Changes to this file may be lost if\n"
> > + " * the code is regenerated.\n"
> > + " *</auto-generated>\n"
> > + " */\n";
> > +
> > +/* Wrap PLL config */
> > +
> > +#define MAIN_VCO_BASE ( \
> > + (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
> > + CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
> > + (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
> > + CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
> > + )
> > +
> > +#define PERI_VCO_BASE ( \
> > + (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
> > + CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
> > + (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
> > + CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
> > + (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
> > + CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
> > + )
> > +
> > +#define SDR_VCO_BASE ( \
> > + (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
> > + CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
> > + (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
> > + CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
> > + (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
> > + CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
> > + )
> > +
> > +static const struct cm_config cm_default = {
> > + /* main group */
> > + MAIN_VCO_BASE,
> > + (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
> > + CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
> > + CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
> > + CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
> > + CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
> > + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
> > + CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
> > + CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
> > + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
> > + CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
> > + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
> > + CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
> > + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
> > + CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
> > + CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
> > + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
> > + CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
> > + CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
> > + CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
> > + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
> > + CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
> > +
> > + /* peripheral group */
> > + PERI_VCO_BASE,
> > + (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
> > + CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
> > + (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
> > + CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
> > + (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
> > + CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
> > + (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
> > + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
> > + (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
> > + CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
> > + (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
> > + CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
> > + (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
> > + CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
> > + (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
> > + CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
> > + (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
> > + CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
> > + (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
> > + CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
> > + (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
> > + CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
> > + (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
> > + CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
> > + (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
> > + CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
> > + (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
> > + CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
> > +
> > + /* sdram pll group */
> > + SDR_VCO_BASE,
> > + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
> > + CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
> > + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
> > + CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
> > + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
> > + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
> > + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
> > + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
> > + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
> > + CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
> > + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
> > + CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
> > + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
> > + CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
> > + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
> > + CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
> > +
> > + /* altera group */
> > + CONFIG_HPS_ALTERAGRP_MPUCLK,
> > +};
> > +
> > +/* Wrap SDRAM config */
> > +static const struct socfpga_sdram_config sdram_config = {
> > + .ctrl_cfg =
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
> > + SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
> > + SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
> > + SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
> > + SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
> > + SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
> > + SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
> > + SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
> > + SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
> > + SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
> > + .dram_timing1 =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
> > + SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
> > + SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
> > + SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
> > + SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
> > + SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
> > + SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
> > + .dram_timing2 =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
> > + SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
> > + SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
> > + SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
> > + SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
> > + SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
> > + .dram_timing3 =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
> > + SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
> > + SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
> > + SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
> > + SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
> > + SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
> > + .dram_timing4 =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
> > + SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
> > + SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
> > + .lowpwr_timing =
> > + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
> > + SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
> > + SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
> > + .dram_odt =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
> > + SDR_CTRLGRP_DRAMODT_READ_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
> > + SDR_CTRLGRP_DRAMODT_WRITE_LSB),
> > + .extratime1 =
> > + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
> > + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
> > + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) |
> > +(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
> > + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
> > + .dram_addrw =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
> > + SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
> > + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
> > + SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
> > + ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
> > + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
> > + .dram_if_width =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
> > + SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
> > + .dram_dev_width =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
> > + SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
> > + .dram_intr =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
> > + SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
> > + .lowpwr_eq =
> > + (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
> > + SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
> > + .static_cfg =
> > + (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
> > + SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
> > + SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
> > + .ctrl_width =
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
> > + SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
> > + .cport_width =
> > + (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
> > + SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
> > + .cport_wmap =
> > + (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
> > + SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
> > + .cport_rmap =
> > + (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
> > + SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
> > + .rfifo_cmap =
> > + (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
> > + SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
> > + .wfifo_cmap =
> > + (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
> > + SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
> > + .cport_rdwr =
> > + (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
> > + SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
> > + .port_cfg =
> > + (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
> > + SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
> > + .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
> > + .fifo_cfg =
> > + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
> > + SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
> > + SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
> > + .mp_priority =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
> > + SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
> > + .mp_weight0 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
> > + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
> > + .mp_weight1 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
> > + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
> > + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
> > + .mp_weight2 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
> > + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
> > + .mp_weight3 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
> > + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
> > + .mp_pacing0 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
> > + SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
> > + .mp_pacing1 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
> > + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
> > + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
> > + .mp_pacing2 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
> > + SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
> > + .mp_pacing3 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
> > + SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
> > + .mp_threshold0 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
> > + SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
> > + .mp_threshold1 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
> > + SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
> > + .mp_threshold2 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
> > + SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
> > + .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
> > +};
> > +
> > +static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
> > + .activate_0_and_1 = RW_MGR(ACTIVATE_0_AND_1),
> > + .activate_0_and_1_wait1 = RW_MGR(ACTIVATE_0_AND_1_WAIT1),
> > + .activate_0_and_1_wait2 = RW_MGR(ACTIVATE_0_AND_1_WAIT2),
> > + .activate_1 = RW_MGR(ACTIVATE_1),
> > + .clear_dqs_enable = RW_MGR(CLEAR_DQS_ENABLE),
> > + .guaranteed_read = RW_MGR(GUARANTEED_READ),
> > + .guaranteed_read_cont = RW_MGR(GUARANTEED_READ_CONT),
> > + .guaranteed_write = RW_MGR(GUARANTEED_WRITE),
> > + .guaranteed_write_wait0 = RW_MGR(GUARANTEED_WRITE_WAIT0),
> > + .guaranteed_write_wait1 = RW_MGR(GUARANTEED_WRITE_WAIT1),
> > + .guaranteed_write_wait2 = RW_MGR(GUARANTEED_WRITE_WAIT2),
> > + .guaranteed_write_wait3 = RW_MGR(GUARANTEED_WRITE_WAIT3),
> > + .idle = RW_MGR(IDLE),
> > + .idle_loop1 = RW_MGR(IDLE_LOOP1),
> > + .idle_loop2 = RW_MGR(IDLE_LOOP2),
> > + .init_reset_0_cke_0 = RW_MGR(INIT_RESET_0_CKE_0),
> > + .init_reset_1_cke_0 = RW_MGR(INIT_RESET_1_CKE_0),
> > + .lfsr_wr_rd_bank_0 = RW_MGR(LFSR_WR_RD_BANK_0),
> > + .lfsr_wr_rd_bank_0_data = RW_MGR(LFSR_WR_RD_BANK_0_DATA),
> > + .lfsr_wr_rd_bank_0_dqs = RW_MGR(LFSR_WR_RD_BANK_0_DQS),
> > + .lfsr_wr_rd_bank_0_nop = RW_MGR(LFSR_WR_RD_BANK_0_NOP),
> > + .lfsr_wr_rd_bank_0_wait = RW_MGR(LFSR_WR_RD_BANK_0_WAIT),
> > + .lfsr_wr_rd_bank_0_wl_1 = RW_MGR(LFSR_WR_RD_BANK_0_WL_1),
> > + .lfsr_wr_rd_dm_bank_0 = RW_MGR(LFSR_WR_RD_DM_BANK_0),
> > + .lfsr_wr_rd_dm_bank_0_data = RW_MGR(LFSR_WR_RD_DM_BANK_0_DATA),
> > + .lfsr_wr_rd_dm_bank_0_dqs = RW_MGR(LFSR_WR_RD_DM_BANK_0_DQS),
> > + .lfsr_wr_rd_dm_bank_0_nop = RW_MGR(LFSR_WR_RD_DM_BANK_0_NOP),
> > + .lfsr_wr_rd_dm_bank_0_wait = RW_MGR(LFSR_WR_RD_DM_BANK_0_WAIT),
> > + .lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR(LFSR_WR_RD_DM_BANK_0_WL_1),
> > + .mrs0_dll_reset = RW_MGR(MRS0_DLL_RESET),
> > + .mrs0_dll_reset_mirr = RW_MGR(MRS0_DLL_RESET_MIRR),
> > + .mrs0_user = RW_MGR(MRS0_USER),
> > + .mrs0_user_mirr = RW_MGR(MRS0_USER_MIRR),
> > + .mrs1 = RW_MGR(MRS1),
> > + .mrs1_mirr = RW_MGR(MRS1_MIRR),
> > + .mrs2 = RW_MGR(MRS2),
> > + .mrs2_mirr = RW_MGR(MRS2_MIRR),
> > + .mrs3 = RW_MGR(MRS3),
> > + .mrs3_mirr = RW_MGR(MRS3_MIRR),
> > + .precharge_all = RW_MGR(PRECHARGE_ALL),
> > + .read_b2b = RW_MGR(READ_B2B),
> > + .read_b2b_wait1 = RW_MGR(READ_B2B_WAIT1),
> > + .read_b2b_wait2 = RW_MGR(READ_B2B_WAIT2),
> > + .refresh_all = RW_MGR(REFRESH_ALL),
> > + .rreturn = RW_MGR(RETURN),
> > + .sgle_read = RW_MGR(SGLE_READ),
> > + .zqcl = RW_MGR(ZQCL),
> > +
> > + .true_mem_data_mask_width = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
> > + .mem_address_mirroring = RW_MGR_MEM_ADDRESS_MIRRORING,
> > + .mem_data_mask_width = RW_MGR_MEM_DATA_MASK_WIDTH,
> > + .mem_data_width = RW_MGR_MEM_DATA_WIDTH,
> > + .mem_dq_per_read_dqs = RW_MGR_MEM_DQ_PER_READ_DQS,
> > + .mem_dq_per_write_dqs = RW_MGR_MEM_DQ_PER_WRITE_DQS,
> > + .mem_if_read_dqs_width = RW_MGR_MEM_IF_READ_DQS_WIDTH,
> > + .mem_if_write_dqs_width = RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
> > + .mem_number_of_cs_per_dimm = RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
> > + .mem_number_of_ranks = RW_MGR_MEM_NUMBER_OF_RANKS,
> > + .mem_virtual_groups_per_read_dqs =
> > + RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
> > + .mem_virtual_groups_per_write_dqs =
> > + RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
> > +};
> > +
> > +static const struct socfpga_sdram_io_config io_config = {
> > + .delay_per_dchain_tap = IO_DELAY_PER_DCHAIN_TAP,
> > + .delay_per_dqs_en_dchain_tap = IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
> > + .delay_per_opa_tap_lo = IO_DELAY_PER_OPA_TAP & 0xff,
> > + .delay_per_opa_tap_hi = (IO_DELAY_PER_OPA_TAP << 8) & 0xff,
> > + .dll_chain_length = IO_DLL_CHAIN_LENGTH,
> > + .dqdqs_out_phase_max = IO_DQDQS_OUT_PHASE_MAX,
> > + .dqs_en_delay_max = IO_DQS_EN_DELAY_MAX,
> > + .dqs_en_delay_offset = IO_DQS_EN_DELAY_OFFSET,
> > + .dqs_en_phase_max = IO_DQS_EN_PHASE_MAX,
> > + .dqs_in_delay_max = IO_DQS_IN_DELAY_MAX,
> > + .dqs_in_reserve = IO_DQS_IN_RESERVE,
> > + .dqs_out_reserve = IO_DQS_OUT_RESERVE,
> > + .io_in_delay_max = IO_IO_IN_DELAY_MAX,
> > + .io_out1_delay_max = IO_IO_OUT1_DELAY_MAX,
> > + .io_out2_delay_max = IO_IO_OUT2_DELAY_MAX,
> > + .shift_dqs_en_when_shift_dqs = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
> > +};
> > +
> > +static const struct socfpga_sdram_misc_config misc_config = {
> > + .afi_rate_ratio = AFI_RATE_RATIO,
> > + .calib_lfifo_offset = CALIB_LFIFO_OFFSET,
> > + .calib_vfifo_offset = CALIB_VFIFO_OFFSET,
> > + .enable_super_quick_calibration = ENABLE_SUPER_QUICK_CALIBRATION,
> > + .max_latency_count_width = MAX_LATENCY_COUNT_WIDTH,
> > + .read_valid_fifo_size = READ_VALID_FIFO_SIZE,
> > + .reg_file_init_seq_signature_ll = REG_FILE_INIT_SEQ_SIGNATURE & 0xff,
> > + .reg_file_init_seq_signature_lh = (REG_FILE_INIT_SEQ_SIGNATURE >> 8) &
> > 0xff,
> > + .reg_file_init_seq_signature_hl = (REG_FILE_INIT_SEQ_SIGNATURE >> 16) &
> > 0xff,
> > + .reg_file_init_seq_signature_hh = (REG_FILE_INIT_SEQ_SIGNATURE >> 24) &
> > 0xff,
> > + .tinit_cntr0_val = TINIT_CNTR0_VAL,
> > + .tinit_cntr1_val = TINIT_CNTR1_VAL,
> > + .tinit_cntr2_val = TINIT_CNTR2_VAL,
> > + .treset_cntr0_val = TRESET_CNTR0_VAL,
> > + .treset_cntr1_val = TRESET_CNTR1_VAL,
> > + .treset_cntr2_val = TRESET_CNTR2_VAL,
> > +};
> > +
> > +static void print_hdr(void)
> > +{
> > + printf(handoff_dtsi_hdr);
> > +}
> > +
> > +static void print_clkmgr_base(void)
> > +{
> > + const char handoff_dtsi_clkmgr_base[] =
> > + "\n"
> > + "&osc1 {\n"
> > + " clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC1_HZ */
> > + "};\n"
> > + "\n"
> > + "&osc2 {\n"
> > + " clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC2_HZ */
> > + "};\n"
> > + "\n"
> > + "&f2s_periph_ref_clk {\n"
> > + " clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_PER_REF_HZ */
> > + "};\n"
> > + "\n"
> > + "&f2s_sdram_ref_clk {\n"
> > + " clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_SDR_REF_HZ */
> > + "};\n";
> > +
> > + printf(handoff_dtsi_clkmgr_base, CONFIG_HPS_CLK_OSC1_HZ,
> > + CONFIG_HPS_CLK_OSC2_HZ, CONFIG_HPS_CLK_F2S_PER_REF_HZ,
> > + CONFIG_HPS_CLK_F2S_SDR_REF_HZ);
> > +}
> > +
> > +/*
> > + * dtc stores u32 array big endian but we load them raw and expect them to
> > be in
> > + * little endian format. To prevent this tool to depend on host endianess,
> > do
> > + * the switch manually, not via 'htonl'.
> > + */
> > +static u32 swap_bytes(u32 val)
> > +{
> > + return (val << 24) | ((val & 0xFF00ul) << 8) |
> > + ((val & 0xFF0000ul) >> 8) | (val >> 24);
> > +}
> > +
> > +static void print_array_ulong(const unsigned long *arr, size_t arr_size,
> > + size_t el_per_line, const char *indent1,
> > + const char *name, const char *indent_next)
> > +{
> > + size_t i;
> > +
> > + printf("%s%s = <", indent1, name);
> > + for (i = 0; i < arr_size; i++) {
> > + printf("0x%08x", swap_bytes((u32)arr[i]));
> > + if (i + 1 < arr_size) {
> > + if (i % el_per_line == (el_per_line - 1)) {
> > + printf("\n%s", indent_next);
> > + } else {
> > + printf(" ");
> > + }
> > + }
> > + }
> > + printf(">;\n");
> > +}
> > +
> > +#ifdef USE_QUARTUS_OUTPUT
> > +static void print_array_sysmgrinit(const unsigned long *arr, size_t
> > arr_size,
> > + const char *indent1, const char *name,
> > + const char *indent_next)
> > +{
> > + size_t i;
> > +
> > + printf("%s%s = [", indent1, name);
> > + for (i = 0; i < arr_size; i++) {
> > + printf("%02x", (u8)arr[i]);
> > + if (i + 1 < arr_size) {
> > + if (i % 8 == 7) {
> > + printf("\n%s", indent_next);
> > + } else {
> > + printf(" ");
> > + }
> > + }
> > + }
> > + printf("];\n");
> > +}
> > +#define print_array_alt_u32 print_array_ulong
> > +#else
> > +#define print_array_sysmgrinit(arr, sz, ind1, n, ind2) print_array_u8(arr,
> > sz, 8, ind1, n, ind2)
> > +#define print_array_alt_u32 print_array_u32
> > +#endif
> > +
> > +static void print_array_u32(const u32 *arr, size_t arr_size,
> > + size_t el_per_line, const char *indent1,
> > + const char *name, const char *indent_next)
> > +{
> > + size_t i;
> > +
> > + printf("%s%s = <", indent1, name);
> > + for (i = 0; i < arr_size; i++) {
> > + printf("0x%08x", swap_bytes(arr[i]));
> > + if (i + 1 < arr_size) {
> > + if (i % el_per_line == (el_per_line - 1)) {
> > + printf("\n%s", indent_next);
> > + } else {
> > + printf(" ");
> > + }
> > + }
> > + }
> > + printf(">;\n");
> > +}
> > +
> > +static void print_array_u8(const u8 *arr, size_t arr_size, size_t
> > el_per_line,
> > + const char *indent1, const char *name,
> > + const char *indent_next)
> > +{
> > + size_t i;
> > +
> > + printf("%s%s = [", indent1, name);
> > + for (i = 0; i < arr_size; i++) {
> > + printf("%02x", arr[i]);
> > + if (i + 1 < arr_size) {
> > + if (i % el_per_line == (el_per_line - 1)) {
> > + printf("\n%s", indent_next);
> > + } else {
> > + printf(" ");
> > + }
> > + }
> > + }
> > + printf("];\n");
> > +}
> > +
> > +
> > +static void print_clkmgr_cfg(void)
> > +{
> > + const char handoff_dtsi_clkmgr_cfg_a[] =
> > + "\n"
> > + "&clkmgr {\n";
> > + const char handoff_dtsi_clkmgr_cfg_b[] = "};\n";
> > + const char clk_mgr_cfg_indent[] = "\t\t\t ";
> > +
> > + printf(handoff_dtsi_clkmgr_cfg_a);
> > + print_array_u32((const u32 *)&cm_default, sizeof(cm_default)/4, 4, "\t",
> > + "altr,clk-mgr-cfg", clk_mgr_cfg_indent);
> > + printf(handoff_dtsi_clkmgr_cfg_b);
> > +}
> > +
> > +static void print_sysmgr(void)
> > +{
> > + const char handoff_dtsi_sysmgr_begin[] =
> > + "\n"
> > + "&sysmgr {\n";
> > + const char handoff_dtsi_sysmgr_end[] = "};\n";
> > + const char sysmgr_cfg_indent[] = "\t\t\t\t\t";
> > + size_t i;
> > +
> > + printf(handoff_dtsi_sysmgr_begin);
> > +
> > + /* sys_mgr_init_table is an u8 table */
> > + print_array_sysmgrinit(sys_mgr_init_table, ARRAY_SIZE(sys_mgr_init_table),
> > + "\t", "altr,pinmux-cfg","\t\t\t ");
> > + /* ioscr scan chain table 0 */
> > + print_array_ulong(iocsr_scan_chain0_table,
> > + ARRAY_SIZE(iocsr_scan_chain0_table), 4,
> > + "\t", "altr,iocsr-scan-chain0-table",
> > + sysmgr_cfg_indent);
> > + /* ioscr scan chain table 0 */
> > + print_array_ulong(iocsr_scan_chain1_table,
> > + ARRAY_SIZE(iocsr_scan_chain1_table), 4,
> > + "\t", "altr,iocsr-scan-chain1-table",
> > + sysmgr_cfg_indent);
> > + /* ioscr scan chain table 0 */
> > + print_array_ulong(iocsr_scan_chain2_table,
> > + ARRAY_SIZE(iocsr_scan_chain2_table), 4,
> > + "\t", "altr,iocsr-scan-chain2-table",
> > + sysmgr_cfg_indent);
> > + /* ioscr scan chain table 0 */
> > + print_array_ulong(iocsr_scan_chain3_table,
> > + ARRAY_SIZE(iocsr_scan_chain3_table), 4,
> > + "\t", "altr,iocsr-scan-chain3-table",
> > + sysmgr_cfg_indent);
> > + printf(handoff_dtsi_sysmgr_end);
> > +}
> > +
> > +static void print_sdram_cfg(void)
> > +{
> > + const char handoff_dtsi_sdram_cfg_begin[] =
> > + "\n"
> > + "&sdr {\n";
> > + const char handoff_dtsi_sdram_cfg_end[] = "};\n";
> > +
> > + printf(handoff_dtsi_sdram_cfg_begin);
> > + print_array_u32((const u32 *)&sdram_config, sizeof(sdram_config)/4, 4,
> > + "\t", "altr,sdr-cfg", "\t\t\t");
> > + print_array_u8((const u8 *)&rw_mgr_config, sizeof(rw_mgr_config), 8,
> > + "\t", "altr,sdr-rw-mgr-cfg", "\t\t\t ");
> > + print_array_u8((const u8 *)&io_config, sizeof(io_config), 8,
> > + "\t", "altr,sdr-io-cfg", "\t\t\t ");
> > + print_array_u8((const u8 *)&misc_config, sizeof(misc_config), 8,
> > + "\t", "altr,sdr-misc-cfg", "\t\t\t ");
> > + print_array_alt_u32(ac_rom_init, ARRAY_SIZE(ac_rom_init), 4,
> > + "\t", "altr,sdr-ac-rom-init", "\t\t\t\t");
> > + print_array_alt_u32(inst_rom_init, ARRAY_SIZE(inst_rom_init), 4,
> > + "\t", "altr,sdr-inst-rom-init", "\t\t\t\t ");
> > + printf(handoff_dtsi_sdram_cfg_end);
> > +}
> > +
> > +int main(void)
> > +{
> > + print_hdr();
> > + print_clkmgr_base();
> > + print_clkmgr_cfg();
> > + print_sysmgr();
> > + print_sdram_cfg();
> > +}
> > diff --git a/arch/arm/mach-socfpga/qts-to-handoff.sh b/arch/arm/mach-
> > socfpga/qts-to-handoff.sh
> > new file mode 100755
> > index 0000000000..b9032a5411
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/qts-to-handoff.sh
> > @@ -0,0 +1,83 @@
> > +#!/bin/sh
> > +# This script converts Quartus handoff files (in Quartus or U-Boot format)
> > +# to a handoff.dtsi file.
> > +
> > +
> > +usage() {
> > + MY_BASENAME=`basename $0`
> > + echo "${MY_BASENAME} [soc_type] [input_qts_dir] [input_bsp_dir]
> > [output_file]"
> > + echo " or"
> > + echo "${MY_BASENAME} 'u-boot' [uboot_qts_dir] [output_file]"
> > + echo ""
> > + echo "Process QTS-generated headers into handoff.dtsi:"
> > + echo ""
> > + echo " soc_type - Type of SoC, either 'cyclone5' or 'arria5'."
> > + echo " input_qts_dir - Directory with compiled Quartus project"
> > + echo " and containing the Quartus project file (QPF)."
> > + echo " input_bsp_dir - Directory with generated bsp containing"
> > + echo " the settings.bsp file."
> > + echo " output_file - Full filename to store the handoff dtsi file."
> > + echo " uboot_qts_dir - board/qts directory if input files are in"
> > + echo " 'old-style' U-Boot format."
> > + echo ""
> > +}
> > +
> > +soc="$1"
> > +
> > +HANDOFF_TEMPLATE="`dirname $0`/create_handoff_gen5.c"
> > +
> > +case "$soc" in
> > +"cyclone5"|"arria5")
> > + if [ "$#" -ne 4 ] ; then
> > + usage
> > + exit 1
> > + fi
> > + in_qts_dir="$2"
> > + in_bsp_dir="$3"
> > + output_file="$4"
> > + out_dir=`dirname ${output_file}`
> > +
> > + if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \
> > + ! -d "${out_dir}" -o -z "${soc}" ] ; then
> > + usage
> > + exit 3
> > + fi
> > +
> > + if [ "$soc" = "cyclone5" ] ; then
> > + CMDLINE_DEFINES="-DCYCLONE5"
> > + else
> > + CMDLINE_DEFINES="-DARRIA5"
> > + fi
> > + CMDLINE_DEFINES="${CMDLINE_DEFINES} -DUSE_QUARTUS_OUTPUT
> > -I${in_bsp_dir}/generated/"
> > + for d in ${in_qts_dir}/hps_isw_handoff/*/ ; do
> > + CMDLINE_DEFINES="${CMDLINE_DEFINES} -I$d"
> > + done
> > + ;;
> > +"u-boot")
> > + if [ "$#" -ne 3 ] ; then
> > + usage
> > + exit 1
> > + fi
> > + in_qts_dir="$2"
> > + output_file="$3"
> > + out_dir=`dirname ${output_file}`
> > +
> > + if [ ! -d "${in_qts_dir}" -o ! -d "${out_dir}" ] ; then
> > + usage
> > + exit 3
> > + fi
> > +
> > + CMDLINE_DEFINES="-I${in_qts_dir}"
> > + ;;
> > +*)
> > + usage
> > + exit 1
> > + ;;
> > +esac
> > +
> > +# compile
> > +gcc ${CMDLINE_DEFINES} ${HANDOFF_TEMPLATE} -o
> > ${out_dir}/create_handoff_gen5
> > +${out_dir}/create_handoff_gen5 > ${output_file}
> > +
> > +# TODO: remove tmp file:
> > +#rm $${out_dir}/create_handoff_gen5
> >
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