Hi Jaehoon,
Philipp has send out another patch for disable t he secure region,
and this patch is no need now.
Thanks,
- Kever
On 03/30/2017 01:04 PM, Jaehoon Chung wrote:
On 03/30/2017 12:01 PM, Kever Yang wrote:
Hi Philipp,
On 03/29/2017 08:59 PM, Dr. Philipp Tomsich wrote:
Kever
Dear Tom,
Could pull these patches into u-boot/master?
The following changes since commit 5cf618ee60a752d058a767372ca1ecb8d9c09b16:
Merge git://git.denx.de/u-boot-arc (2017-03-24 08:19:30 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-mmc.git master
for you to fet
Add misc support for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile| 1 +
arch/arm/mach-socfpga/include/mach/misc.h | 6 +
arch/arm/mach-socfpga/misc_arria10.c | 258 ++
3 files changed, 265
Update Kconfig and Makefile to enable Arria 10.
Clean up Makefile and sorting *.o alphanumerically.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Kconfig | 10 +
arch/arm/mach-socfpga/Makefile | 46 ++
2 file
Add support for the Arria10 SoCDK.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
board/altera/arria10-socdk/Kconfig | 18 ++
board/altera/arria10-socdk/Makefile | 7 +++
board/altera/arria10-socdk/socfpga.c | 7 +++
3 files changed, 32 insertions(+)
Add config and defconfig for the Arria10 and update socfpga_common.h.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
configs/socfpga_arria10_defconfig | 28 ++
include/configs/socfpga_arria10_socdk.h | 66 +
include/configs/socfpg
Add reset driver support for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile | 2 +
arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 +
.../include/mach/reset_manager_arria10.h | 144
arch/ar
Device tree files for Arria 10
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_arria10.dtsi | 859 +
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 30 +
..
Add pinmux support for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/include/mach/pinmux.h | 15 +
arch/arm/mach-socfpga/pinmux_arria10.c | 96 +
3 files chan
These registers only available for Gen5 device, exclude them
from Arria 10 build.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
drivers/fpga/socfpga.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index f1b2f2c..3751574
Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have different driver.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
drivers/Kconfig | 2 ++
drivers/ddr/Kconfig | 1 +
driv
Add SPL support for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/spl.c | 74 ++---
1 file changed, 69 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
in
Add compatible strings for Intel Arria 10 SoCFPGA device.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
include/fdtdec.h | 8
lib/fdtdec.c | 8
2 files changed, 16 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index d074478..2134701 100644
Add clock driver support for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
Conflicts:
arch/arm/mach-socfpga/clock_manager.c
---
arch/arm/mach-socfpga/Makefile |3 +-
arch/arm/mach-socfpga/clock_manager.c | 10 +
arch/arm/mach
Add sdram header file for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 380 +
1 file changed, 380 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_arria10.h
diff --git
Add system manager register struct and macros for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
.../arm/mach-socfpga/include/mach/system_manager.h | 74 +---
.../include/mach/system_manager_arria10.h | 81 ++
2 files changed
Restructure misc driver in the preparation to support A10.
Move the Gen5 specific code to gen5 file. No functional change.
Change all uint32_t_to u32.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile| 2 +-
arch/arm/mach-socfpga/include/mach/misc.h | 25 ++
Add i2c, timer and other A10 macros.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
b/arch/arm/mach-socfpga/include/mach/base_addr_a1
Restructure system manager in the preparation to support A10.
No functional change.
Change uint32_t to u32.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile | 5 +-
.../arm/mach-socfpga/include/mach/system_manager.h | 128 ++---
.../{system_ma
Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files. Minor update in socfpga_per_reset().
No functional change.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile | 2 +-
arch/arm/mach-socfpga/include/mach
Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files. No functional change.
Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile | 3
This is the 3rd version of patchset to adds support for Intel Arria 10 SoC.
This version mainly resolved comments from Marek in [v2].
This is initial patchset enables the basic support for Arria 10 and other
features will come after this.
This series is working on top of “arm: socfpga: Move to us
On 03/30/2017 12:01 PM, Kever Yang wrote:
> Hi Philipp,
>
>
> On 03/29/2017 08:59 PM, Dr. Philipp Tomsich wrote:
>> Kever,
>>
>> I did a bit of quick experiment by altering the DMA target addresses for
>> the DMA and can confirm that the root cause must be one of the security
>> registers.
>
> T
Sorry for top posting. I am using OWA which doesn't do inline reply.
Jaehoon,
The trouble is the env_init() returns the default environment for SPL part. It
means whatever variables I saved doesn't get loaded during the SPL part. It is
only available after the SPL loads the RAM version. For exa
Hi York,
On 03/23/2017 07:58 AM, york sun wrote:
> Jaehoon,
>
> I noticed the env_init() returns default environmental variable for SPL
> build. I wonder if you can make some change to use the actual variables?
> I am having some trouble to get the saved variable during SPL boot.
Which trouble
On 03/29/2017 05:41 PM, Lukasz Majewski wrote:
> Hi Simon,
>
> +CC board maintainer: Jaehoon.
>
>> This is not used by any board. Drop it.
>>
>> Signed-off-by: Simon Glass
>> Clean up board_f sequence a little
>> This series tries to remove #ifdefs from the board_f init sequence. It
>> gets as f
On 03/23/2017 12:00 AM, Jean-Jacques Hiblot wrote:
> This is a preparation work for the support of CONFIG_BLK.
>
> Signed-off-by: Jean-Jacques Hiblot
Applied on u-boot-mmc. Thanks!
Best Regards,
Jaehoon Chung
> ---
> drivers/mmc/omap_hsmmc.c | 27 ++-
> 1 file changed,
On 03/23/2017 12:00 AM, Jean-Jacques Hiblot wrote:
> Signed-off-by: Jean-Jacques Hiblot
Applied on u-boot-mmc. Thanks!
Best Regards,
Jaehoon Chung
> ---
> drivers/mmc/omap_hsmmc.c | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mm
On 03/23/2017 12:00 AM, Jean-Jacques Hiblot wrote:
> Signed-off-by: Jean-Jacques Hiblot
Applied on u-boot-mmc. Thanks!
Best Regards,
Jaehoon Chung
> ---
> drivers/mmc/omap_hsmmc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/o
Hi,
On 03/23/2017 12:00 AM, Jean-Jacques Hiblot wrote:
> For consistency, use an accessor to access the private data. Also for the
> same reason, rename all priv_data to priv.
>
> Signed-off-by: Jean-Jacques Hiblot
Applied on u-boot-mmc. Thanks!
Best Regards,
Jaehoon Chung
> ---
> drivers/mm
Hi Wenyou,
On 03/23/2017 01:48 PM, Wenyou Yang wrote:
> Add the driver model support for Atmel mci while retaining the
> existing legacy code. This allows the driver to support boards
> that have converted to driver model as well as those that have not.
>
> Signed-off-by: Wenyou Yang
If Andreas
Hi Jernej,
On 03/30/2017 07:23 AM, Jernej Skrabec wrote:
MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
expansion ports.
Signed-off-by: Jernej Skrabec
---
Changes in v3:
- split out cosmetic changes
Hi Jernej,
On 03/30/2017 07:23 AM, Jernej Skrabec wrote:
Sort rk3288 boards in alphabetical order.
Signed-off-by: Jernej Skrabec
---
Changes in v3:
- new patch
arch/arm/dts/Makefile | 10 ++--
arch/arm/mach-rockchip/rk3288/Kconfig | 90 +--
Hi Philipp,
On 03/30/2017 03:20 AM, Philipp Tomsich wrote:
The RK3399 hangs during DMA of the Designware MMC controller, when
performing DMA-based transactions in SPL due to the DDR security settings
left behind by the BootROM (i.e. accesses to the first MB of DRAM are
restricted... however, th
Hi Philipp,
On 03/29/2017 08:59 PM, Dr. Philipp Tomsich wrote:
Kever,
I did a bit of quick experiment by altering the DMA target addresses for
the DMA and can confirm that the root cause must be one of the security
registers.
Thanks for debugging on this, you are right about the root cause.
Hi Tom,
Herewith some fairly minor changes from my patchwork queue.
The following changes since commit 5cf618ee60a752d058a767372ca1ecb8d9c09b16:
Merge git://git.denx.de/u-boot-arc (2017-03-24 08:19:30 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-dm.git
for you
Sort rk3288 boards in alphabetical order.
Signed-off-by: Jernej Skrabec
---
Changes in v3:
- new patch
arch/arm/dts/Makefile | 10 ++--
arch/arm/mach-rockchip/rk3288/Kconfig | 90 +--
doc/README.rockchip | 2 +-
3 files changed,
MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
expansion ports.
Signed-off-by: Jernej Skrabec
---
Changes in v3:
- split out cosmetic changes into a new patch
Changes in v2:
- change license to SPDX id
This series adds support for MiQi board.
MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
expansion ports.
Patch 1 first sorts all rk3288 boards alphabeticaly.
Patch 2 adds support for MiQi board
Jerne
Hi Maxime,
Thank you for all your reviews!
On 29/03/2017 10:12, Maxime Ripard wrote:
Hi,
On Wed, Mar 29, 2017 at 09:26:37AM +0200, Mylène Josserand wrote:
Convert the CONS_INDEX configuration to Kconfig.
Update sunxi's defconfigs to remove SYS_EXTRA_OPTIONS variable not
needed anymore.
Defaul
From: Stefan Agner
For i.MX 6SoloX/i.MX 7 simple binary files are used to boot the
auxiliary CPU core (Cortex-M4). This patch moves the "parsing" of
this binary firmwares to the SoC independent code. This allows to
add different binary formats more easily.
While at it, also move the comment abou
From: Stefan Agner
Use i.MX bootaux support introduced for i.MX 6SoloX/i.MX 7 for
Vybrid too. Starting the Cortex-M4 core on Vybrid works a bit
differently, naemly it uses a GPR register to define the initial
PC. There is no way to define the initial stack (the stack is
set up in a boot ROM). Thi
From: Stefan Agner
Support elf firmware files for the auxiliary Cortex-M4 core. This
has the advantage that the user does not need to know to which
address the binary has been linked to. However, in order to load
the elf sections to the right address, we need to translate the
Cortex-M4 core memor
From: Stefan Agner
This patchset enables to boot elf binaries on secondary Cortex-M
class cores available on i.MX 6SoloX/7Solo/7Dual. This makes
handling and loading firmwares much more convinient since all
information where the firmware has to be loaded to is contained in
the elf headers. A typi
From: Stefan Agner
For some reason Python 3 seems to think it does not need to build
the library. Using the --force parameter makes sure that the library
gets built always. This is especially important since we move the
library in the next step of the Makefile, hence forcing a rebuild
every time
Hi Simon,
Just a reminder for your review whenever you get a chance.
Cheers,
Vikas
> -Original Message-
> From: Vikas MANOCHA
> Sent: Friday, March 24, 2017 3:19 PM
> To: u-boot@lists.denx.de
> Cc: Vikas MANOCHA ; Simon Glass
> Subject: [PATCH] fdt: allow address translation in case of
Hi Michal/Simon,
> -Original Message-
> From: Vikas MANOCHA
> Sent: Friday, March 24, 2017 2:48 PM
> To: u-boot@lists.denx.de
> Cc: Vikas MANOCHA ; Michal Simek
> ; Simon Glass
> Subject: [PATCH] dm: avoid dropping pin control DT properties in case of
> SPL_PINCTRL
>
> This patch repla
Signed-off-by: Philipp Tomsich
---
Changes in v3: None
arch/arm/dts/rk3399-puma.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/dts/rk3399-puma.dts b/arch/arm/dts/rk3399-puma.dts
index 09b3858..50e43c7 100644
--- a/arch/arm/dts/rk3399-puma.dts
+++ b/arch/arm/dts/rk3399-puma.dts
The RK3399 hangs during DMA of the Designware MMC controller, when
performing DMA-based transactions in SPL due to the DDR security settings
left behind by the BootROM (i.e. accesses to the first MB of DRAM are
restricted... however, the DMA is likely to target this first MB, as it
transfers from/t
The (shared) rk3399.dtsi had defined the 'rockchip,vbus-gpio'
properties for each USB 3.0 controller.
As the GPIO usage will vary (e.g. one of those GPIOs shuts down one of
the regulators on the RK3399-Q7) between boards, we move this from the
shared dtsi into the device tree file for the EVB boar
> -Original Message-
> From: york sun
> Sent: Wednesday, March 29, 2017 10:33 PM
> To: Sumit Garg ; u-boot@lists.denx.de
> Cc: Ruchika Gupta ; Prabhakar Kushwaha
> ; Vini Pillai
> Subject: Re: [PATCH 6/7] SECURE_BOOT: Enable chain of trust on LS1012A
> platform
>
> On 03/29/2017 10:01 AM,
On 03/29/2017 10:01 AM, Sumit Garg wrote:
>> -Original Message-
>> From: york sun
>> Sent: Wednesday, March 29, 2017 10:20 PM
>> To: Sumit Garg ; u-boot@lists.denx.de
>> Cc: Ruchika Gupta ; Prabhakar Kushwaha
>> ; Vini Pillai
>> Subject: Re: [PATCH 6/7] SECURE_BOOT: Enable chain of trust o
> -Original Message-
> From: york sun
> Sent: Wednesday, March 29, 2017 10:20 PM
> To: Sumit Garg ; u-boot@lists.denx.de
> Cc: Ruchika Gupta ; Prabhakar Kushwaha
> ; Vini Pillai
> Subject: Re: [PATCH 6/7] SECURE_BOOT: Enable chain of trust on LS1012A
> platform
>
> On 03/23/2017 01:19 AM,
> -Original Message-
> From: york sun
> Sent: Wednesday, March 29, 2017 10:16 PM
> To: Sumit Garg ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha ; Ruchika Gupta
> ; Vini Pillai
> Subject: Re: [u-boot-release] [PATCH 3/7] SECURE_BOOT: Enable chain of trust
> on LS1046A platform
>
> On 03/
Using changes in this patch we were able to reduce approx 4k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1046ardb/Makefile to remove
compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescale
Using changes in this patch we were able to reduce approx 10k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1043ardb/Makefile to remove
compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescal
On 03/23/2017 01:19 AM, Sumit Garg wrote:
> From: Vinitha Pillai-B57223
>
> Define bootscript and its header addresses for QSPI target
> Also add PPA header address in Kconfig
>
> Signed-off-by: Vinitha Pillai
> Signed-off-by: Sumit Garg
> ---
> arch/arm/cpu/armv8/fsl-layerscape/Kconfig
On 03/23/2017 01:19 AM, Sumit Garg wrote:
> From: Vinitha Pillai-B57223
>
> Define bootscript and its header addresses for QSPI target. Also
> define PPA header address to enable PPA validation.
>
> Signed-off-by: Vinitha Pillai
> Signed-off-by: Sumit Garg
> ---
> arch/arm/cpu/armv8/fsl-layersc
From: Thomas Schaefer
Depending on DDR configuration, gcc-6.x will show up unused-const-
variable messages. Use __maybe_unused specifier for all dynamic_odt
variable definitions to remove these warnings.
Memory footprint will not increase as gcc will optimize out unused
constants.
Signed-off-by
> -Original Message-
> From: york sun
> Sent: Wednesday, March 29, 2017 9:15 PM
> To: Sumit Garg ; u-boot@lists.denx.de
> Cc: Ruchika Gupta ; Prabhakar Kushwaha
> ; Mingkai Hu ; Vini
> Pillai
> Subject: Re: [PATCH v4] ls1046ardb: SPL size reduction in case of non-xip boot
>
> On 03/29/201
On 03/29/2017 08:36 AM, Sumit Garg wrote:
>>>
>>> diff --git a/include/configs/ls1046ardb.h
>>> b/include/configs/ls1046ardb.h index 2141b82..c01eb1f 100644
>>> --- a/include/configs/ls1046ardb.h
>>> +++ b/include/configs/ls1046ardb.h
>>> @@ -9,6 +9,18 @@
>>>
>>> #include "ls1046a_common.h"
>>>
> -Original Message-
> From: york sun
> Sent: Wednesday, March 29, 2017 8:57 PM
> To: Sumit Garg ; u-boot@lists.denx.de
> Cc: Ruchika Gupta ; Prabhakar Kushwaha
> ; Mingkai Hu ; Vini
> Pillai
> Subject: Re: [PATCH v4] ls1046ardb: SPL size reduction in case of non-xip boot
>
> On 03/29/201
On 03/29/2017 05:33 AM, Sumit Garg wrote:
> Using changes in this patch we were able to reduce approx 4k
> size of u-boot-spl.bin image. Following is breif description of
> changes to reduce SPL size:
> 1. Changes in board/freescale/ls1046ardb/Makefile to remove
>compilation of eth.c and cpld.c
Hi Fabio,
On Mon, Sep 26, 2016 at 5:44 PM, Fabio Estevam wrote:
> From: Fabio Estevam
>
> When using SPL on i.mx6 we frequently notice some DDR initialization
> mismatches between the SPL code and the non-SPL code.
>
> This causes stability issues like the ones reported at 7dbda25ecd6d7c
> ("mx6
On Wed, 29 Mar 2017, Wolfgang Denk wrote:
> Dear Robert,
>
> In message you wrote:
> >
> > kind of a trivial question but i was just perusing the code related
> > to FIT images and ran across this in main.c:
> ...
> > #if defined(CONFIG_UPDATE_TFTP)
> > update_tftp(0UL, NULL, NULL);
Hi Olliver,
thanks for having a look.
On 29/03/17 15:43, Olliver Schinagl wrote:
> Hey Andre,
>
> On 01-03-17 03:25, Andre Przywara wrote:
>> mksunxiboot limits the size of the resulting SPL binaries to pretty
>> conservative values to cover all SoCs and all boot media (NAND).
>> It turns out th
Dear Robert,
In message you wrote:
>
> kind of a trivial question but i was just perusing the code related
> to FIT images and ran across this in main.c:
...
> #if defined(CONFIG_UPDATE_TFTP)
> update_tftp(0UL, NULL, NULL);<- THERE
> #endif /* CONFIG_UPDATE_TFTP */
>
From: Vinitha Pillai-B57223
Add NAND secure boot target for ls1043ardb.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size as
header is appended to u-boot image. So header will also be copied from SD to
DDR.
- MA
i'm following along the instructions to use the sandbox to demo a
FIT image:
$ make O=sandbox sandbox_config
$ make O=sandbox
$ ./test/image/test-fit.py -u sandbox/u-boot
but running that last command produces only:
FIT Tests
=
Warning (unit_address_vs_reg): Node /reset@0 has a
From: Vinitha Pillai-B57223
- Add SD secure boot target for ls1046ardb.
- Implement board specific spl_board_init() to setup CAAM stream ID and
corresponding stream ID in SMMU.
- Change the u-boot size defined by a macro for copying the main U-Boot by SPL
to also include the u-boot Secure Boo
From: Vinitha Pillai-B57223
- Add SD secure boot target for ls1046ardb.
- Implement board specific spl_board_init() to setup CAAM stream ID and
corresponding stream ID in SMMU.
- Change the u-boot size defined by a macro for copying the main U-Boot by SPL
to also include the u-boot Secure Boo
- Add SD secure boot target for ls1043ardb.
- Implement board specific spl_board_init() to setup CAAM stream ID and
corresponding stream ID in SMMU.
- Change the u-boot size defined by a macro for copying the main U-Boot by SPL
to also include the u-boot Secure Boot header size as header is app
at the top of that file:
#if !(defined(CONFIG_FIT) && defined(CONFIG_OF_LIBFDT))
#error "CONFIG_FIT and CONFIG_OF_LIBFDT are required for auto-update feature"
#endif
#if defined(CONFIG_UPDATE_TFTP) && !defined(CONFIG_MTD_NOR_FLASH)
#error "CONFIG_UPDATE_TFTP and !CONFIG_MTD_NOR_FLASH needed fo
kind of a trivial question but i was just perusing the code related
to FIT images and ran across this in main.c:
/* We come here after U-Boot is initialised and ready to process commands */
void main_loop(void)
{
const char *s;
bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP,
Kever,
I did a bit of quick experiment by altering the DMA target addresses for
the DMA and can confirm that the root cause must be one of the security
registers.
The DMA target addresses are located on the SPL stack, which by default
grows down from 0x0008_ (so the addresses will be 0x0007_f
Using changes in this patch we were able to reduce approx 4k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1046ardb/Makefile to remove
compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescale
On Wed, Mar 29, 2017 at 12:17:31PM +0100, Andre Przywara wrote:
> Hi,
>
> On 29/03/17 07:57, Maxime Ripard wrote:
> > On Tue, Mar 28, 2017 at 01:45:22AM +0100, Andre Przywara wrote:
> >> The Pine64 (and all other 64-bit Allwinner boards) need to load an
> >> ARM Trusted Firmware image beside the a
Using changes in this patch we were able to reduce approx 10k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1043ardb/Makefile to remove
compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescal
From: Jakob Unterwurzacher
The existing Rockchip SPI (rk_spi.c) driver also matches the hardware
block found in the RK3399. This has been confirmed both with SPI NOR
flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5.
This change adds the 'rockchip,rk3399-spi' string to its co
To include the ability to load from an SPI flash in SPL, it's not
sufficient to define SPL_SPI_SUPPORT and SPL_SPI_FLASH_SUPPORT via
Kconfig... so we conditionally define SPL_SPI_LOAD if SPI support
is already enabled for SPL via Kconfig.
Signed-off-by: Philipp Tomsich
---
Changes in v2: None
For the RK3399, i2c_set_rate (and by extension: our spi_set_rate,
which had been mindlessly following the template of the i2c_set_rate
implementation) miscalculates the rate returned due to a off-by-one
error resulting from the following sequence of events:
1. calculates 'src_div := src_freq / ta
From: Jakob Unterwurzacher
On the RK3399-Q7 we need to enable a number of configuration options
(e.g. CONFIG_SPI_FLASH_WINBND) dependent on Kconfig seeing CONFIG_SPI
and CONFIG_SPI_FLASH active.
To allow for these being defined in Kconfig (e.g. via defconfig) and
to avoid a warning on having the
This change adds support for configuring the module clocks for SPI1 and
SPI5 from the 594MHz GPLL.
Note that the driver (rk_spi.c) always sets this to 99MHz, but the
implemented functionality is more general and will also support
different clock configurations.
X-AffectedPlatforms: RK3399-Q7
Sign
To support SPI flashes (via the device model) and enable loading of
later-stage images from SPI in SPL, we need a few adjustments to the
common configuration header for the RK3399:
- enable SPL_SPI_LOAD if SPI is enabled for SPL (in rk3399_common)
- move CONFIG_SPI and CONFIG_SPI_FLASH (from rk3
This commit adds support for the pin-configuration of the SPI5
controller of the RK3399 through the following changes:
* grf_rk3399.h: adds definition for configuring the SPI5 pins
in the GPIO2C group
* periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
* pinctrl_rk3399.c:
Hi,
On 29/03/17 07:57, Maxime Ripard wrote:
> On Tue, Mar 28, 2017 at 01:45:22AM +0100, Andre Przywara wrote:
>> The Pine64 (and all other 64-bit Allwinner boards) need to load an
>> ARM Trusted Firmware image beside the actual U-Boot proper.
>> This can now be easily achieved by using the just ex
2017-03-28 20:47 GMT+09:00 Felipe Balbi :
>
> Hi,
>
> Nishanth Menon writes:
>> Hi Masahiro-san,
>>
>> On Tue, Mar 28, 2017 at 1:29 AM, Masahiro Yamada
>> wrote:
>> [...]
>>>
>>> When O= is given, the build system runs in the object tree,
>>> not in the source tree.
>>> (This is the same as Linux
Hi Tom,
please pull the Marvell mvpp2 patches with the ethernet
support for the ARMv8 Armada 7k/8k platforms. The
ethernet patches are all acked by Joe and he is okay with
me pushing them via the Marvell tree.
Thanks,
Stefan
The following changes since commit 1c694102a56895b7aea636f026955cc5d7ee
On 23.03.2017 17:01, Stefan Roese wrote:
This patchset does the following things:
- It brings the latest Linux changes from the mvpp2 ethernet driver done
by Thomas Petazzoni to the U-Boot version of this driver. This enables
the usage of this driver on the new Marvell Armada 7k / 8k ARMv8
On 03/29/2017 05:49 AM, tien.fong.c...@intel.com wrote:
> From: "Chee, Tien Fong"
>
> Commit ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole
> header file") miss out cleaning macro in this header file, and this
> has broken implementation of a boot header capability in socfpga
> SPL.
Hi Simon,
+CC board maintainer: Jaehoon.
> This is not used by any board. Drop it.
>
> Signed-off-by: Simon Glass
> Clean up board_f sequence a little
> This series tries to remove #ifdefs from the board_f init sequence. It
> gets as far as I2C and then we need to discuss whether we can start t
Hi,
On Wed, Mar 29, 2017 at 09:26:37AM +0200, Mylène Josserand wrote:
> Convert the CONS_INDEX configuration to Kconfig.
> Update sunxi's defconfigs to remove SYS_EXTRA_OPTIONS variable not
> needed anymore.
> Default value is 1 except for sun5i (equals 2) and sun8i (equals 5).
>
> Signed-off-by:
On Wed, Mar 29, 2017 at 09:26:34AM +0200, Mylène Josserand wrote:
> Convert CONFIG_RGMII to Kconfig. Thanks to that, it is possible to
> update defconfig files of SYS_EXTRA_OPTIONS accordingly and
> remove it when it is possible.
>
> Signed-off-by: Mylène Josserand
Acked-by: Maxime Ripard
Than
On Wed, Mar 29, 2017 at 09:26:33AM +0200, Mylène Josserand wrote:
> Convert the SUNXI_EMAC config to Kconfig. Remove it from SYS_EXTRA_OPTIONS
> from many sunxi defconfig and renamed it into SUN4I_EMAC to not confuse it
> with SUN8I_EMAC.
>
> Signed-off-by: Mylène Josserand
Acked-by: Maxime Ripa
Hi,
On Wed, Mar 29, 2017 at 09:26:28AM +0200, Mylène Josserand wrote:
> +config SUN7I_GMAC
> + bool "Enable GMAC Ethernet support"
GMAC itself is a quite common term when talking about a Gigabit
Ethernet controller. How about something like "Enable Allwinner GMAC
Ethernet Support"?
Once fixe
Kever,
we didn’t have time to track this down yet, so we’ve put this work-around
in place to be reverted once we isolate this issue.
The problem goes away once ATF is running in EL3 and U-Boot executes
in its normal privilege level… so our guess is that it’s either an issue with
running in EL3 or
Convert the SUNXI_EMAC config to Kconfig. Remove it from SYS_EXTRA_OPTIONS
from many sunxi defconfig and renamed it into SUN4I_EMAC to not confuse it
with SUN8I_EMAC.
Signed-off-by: Mylène Josserand
---
configs/A10-OLinuXino-Lime_defconfig | 3 ++-
configs/A10s-OLinuXino-M_defconfig | 2 +-
co
Convert the CONS_INDEX configuration to Kconfig.
Update sunxi's defconfigs to remove SYS_EXTRA_OPTIONS variable not
needed anymore.
Default value is 1 except for sun5i (equals 2) and sun8i (equals 5).
Signed-off-by: Mylène Josserand
---
board/sunxi/Kconfig | 9 +
con
This configuration is not necessary in a defconfig file so
it is removed from the SYS_EXTRA_OPTIONS.
Signed-off-by: Mylène Josserand
Acked-by: Maxime Ripard
---
configs/icnova-a20-swac_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/icnova-a20-swac_defconfi
Convert the CONFIG_SATAPWR into kconfig.
Thanks to that, many SYS_EXTRA_OPTIONS can be removed from some
defconfigs.
Signed-off-by: Mylène Josserand
Acked-by: Maxime Ripard
---
board/sunxi/Kconfig| 7 +++
board/sunxi/board.c| 7 ---
config
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