From: Suresh Gupta
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same value.
Signed-off-by: Sriram Dash
Signed-off-by: Sures
> -Original Message-
> From: york sun
> Sent: Monday, January 30, 2017 9:44 PM
> To: Bharat Bhushan ; Z.Q. Hou
> ; M.H. Lian ; u-
> b...@lists.denx.de
> Cc: albert.u.b...@aribaud.net; s...@chromium.org
> Subject: Re: [PATCH 1/3] fsl-lsch3: rename ls2080a_stream_id.h to
> stream_id_lsch3.h
From: Suresh Gupta
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
Signed-off-by: Suresh Gupta
---
Changes in v2:
The patch set implement USB PHY errata workaround which are
required for LS series of freescale platforms which have
Synopsis UTMI PHY
Suresh Gupta (8):
armv8: Add workaround for USB erratum A-009008
armv8: Add workaround for USB erratum A-009798
armv8: Add workaround for USB erratum A-00899
From: Suresh Gupta
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
Signed-off-by: Suresh Gupta
---
Changes in v2:
From: Suresh Gupta
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed
From: Suresh Gupta
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
Signed-off-by: Suresh Gupta
---
Changes in v2:
From: Suresh Gupta
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed
From: Suresh Gupta
Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings
Change settings required for transmitter signal swings to pass
compliance tests.
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
First patch is rename the stream-id defination file to generic
so that this can be leveraged for new SOCs, ls2088, ls1088 etc.
Second add stream-ids allocation for NXP Chasis-2 based SOCs, ls1043, ls1046
etc.
and Third patch enables PCI-LUT initialization.
Bharat Bhushan (3):
fsl-lsch3: rename
Layerscape Chasis-2 also uses same PCIe controller
as used in Chasis-3 and have similar PCI-Lut.
We need to initialize the pcie-lut for Chasis-2 also
as in Chasis-3.
Signed-off-by: Bharat Bhushan
---
drivers/pci/pcie_layerscape_fixup.c | 4
1 file changed, 4 deletions(-)
diff --git a/driv
From: Suresh Gupta
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed
Layerscape Chasis-2 have PCIe device, some platform devices and
DPAA1 devices which will use stream-ids for iommu level isolation
as they lies behind SMMU.
This patch defines the stream-ids for Chasis-2 devices.
stream-ids for DPAA1 are reserved for future use.
Signed-off-by: Bharat Bhushan
---
The stream ID allocation for Chasis3.0 devices,
LS1088, LS2088 and LS2080, can be shared.
This patch renames this accordingly.
Signed-off-by: Bharat Bhushan
---
.../asm/arch-fsl-layerscape/ls2080a_stream_id.h| 77 --
.../asm/arch-fsl-layerscape/stream_id_lsch3.h | 7
From: Vinitha Pillai
Raw uboot image is used in place of FIT image in secure boot.
The maximum allocated size of raw u-boot bin is 1MB in memory map.
Hence , CONFIG_SYS_MONITOR_LEN has been modified to 1 MB.
The bootscript (BS_ADDR) and its header (BS_HDR_ADDR) offset on
MMC have also been modi
From: Suresh Gupta
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same vale.
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh
Hi Stefan,
On 01/31/2017 02:44 PM, Stefan Roese wrote:
> Hi Jaehoon,
>
> On 31.01.2017 04:43, Jaehoon Chung wrote:
>> On 01/25/2017 04:51 PM, Stefan Roese wrote:
>>> Now that the SD/SDIO/MMC DT properties are updated in the Marvell
>>> A3700 and A7/8k DT files, we need to match the checks for com
Hi Jaehoon,
On 31.01.2017 04:43, Jaehoon Chung wrote:
On 01/25/2017 04:51 PM, Stefan Roese wrote:
Now that the SD/SDIO/MMC DT properties are updated in the Marvell
A3700 and A7/8k DT files, we need to match the checks for compatible
node in the PHY driver as well.
This patch was delegated to
Hello Masahiro,
Am 27.01.2017 um 22:53 schrieb Masahiro Yamada:
The readl_poll_timeout() is a useful helper to poll registers
and error out if the condition is not met.
Signed-off-by: Masahiro Yamada
---
drivers/i2c/i2c-uniphier-f.c | 34 ++
1 file changed,
Hello Masahiro,
Am 27.01.2017 um 22:53 schrieb Masahiro Yamada:
This include is unnecessary for low-level drivers.
Signed-off-by: Masahiro Yamada
---
drivers/i2c/i2c-uniphier-f.c | 1 -
drivers/i2c/i2c-uniphier.c | 1 -
2 files changed, 2 deletions(-)
Reviewed-by: Heiko Schocher
bye
On Monday 30 January 2017 08:45 PM, Roger Quadros wrote:
> PRU ethernet MAC address range is present in the
> board EEPROM. Parse it and setup eth?addr
> environment variables.
>
> Signed-off-by: Roger Quadros
> ---
> board/ti/ks2_evm/board_k2g.c | 19 +++
> configs/k2g_evm_def
On Monday 30 January 2017 08:45 PM, Roger Quadros wrote:
> In stead of defining the board EEPROM address in the board headers
> let's define them in the board config files and make them
> configurable by Kconfig.
>
> Signed-off-by: Roger Quadros
> ---
> arch/arm/Kconfig | 10 +
On Monday 30 January 2017 08:45 PM, Roger Quadros wrote:
> Use the same convention that was used for ICSS1 Ethernet
> - If pin is output, set as PIN_OUTPUT
> - If pin is input and external pull resistor present set as PIN_INPUT
> - If pin is input and external pull resistor absent, set pull to sa
On Monday 30 January 2017 08:45 PM, Roger Quadros wrote:
> The board can support either ICSS1 Ethernet ports or LCD
> based on J51 jumper. Factory default is ICSS1 Ethernet ports
> (i.e. Jumper not populated).
>
> Use the GPIO to detect the jumper setting and configure the
> pinmux accordingly.
On Monday 30 January 2017 08:45 PM, Roger Quadros wrote:
> Keystone and OMAP platforms will need this to set ethernet
> MAC addresses from board EEPROM.
>
> Signed-off-by: Roger Quadros
Reviewed-by: Lokesh Vutla
Thanks and regards,
Lokesh
___
U-Boo
On Monday 30 January 2017 08:45 PM, Quadros, Roger wrote:
> GPIO_TO_PIN(bank, bank_gpio) returns the GPIO index
> from the GPIO bank number and bank's GPIO offset number.
>
> Signed-off-by: Roger Quadros
> Reviewed-by: Tom Rini
Reviewed-by: Lokesh Vutla
Thanks and regards,
Lokesh
_
As reported in [1], rename the k2* dts files to keystone-* files
this will force consistency throughout.
Script for the same (and hand modified for Makefile and config
files):
for i in arch/arm/dts/k2*
do
b=`basename $i`;
git mv $i arch/arm/dts/keystone-$b;
sed -i -e "s/$b/
Hi Heiner,
On 01/28/2017 05:56 AM, Heiner Kallweit wrote:
> Enable new Meson GX MMC driver in Odroid C2 defconfig.
Conflicts this patch on latest u-boot.
Best Regards,
Jaehoon Chung
>
> Signed-off-by: Heiner Kallweit
> ---
> v2:
> - move GXBB_PINMUX definition from patch 3 to this one
> v3:
>
Hi Stefan,
On 01/25/2017 04:51 PM, Stefan Roese wrote:
> Now that the SD/SDIO/MMC DT properties are updated in the Marvell
> A3700 and A7/8k DT files, we need to match the checks for compatible
> node in the PHY driver as well.
This patch was delegated to me. But i think right that it might be de
Hi Simon
On 01/26/2017 11:23 PM, Simon Glass wrote:
> Hi Jaehoon,
>
> On 18 January 2017 at 23:13, Jaehoon Chung wrote:
>> Add the max8997 controller for Driver model.
>> Exynos4210 is using max8997 pmic controller.
>> (pmic_max8997.c should be deprecated.)
>>
>> Signed-off-by: Jaehoon Chung
>>
To get Falcon mode working with zImage is currently non trivial as zImages
do not fit into U-Boot's image concept too well. Fortunately at least for
ARM boards it seems getting memory node right is quite sufficient.
What about changing 'fdt memory' command to update memory node according to
detecte
Hey all,
It's release day and v2017.03-rc1 is out and the merge window is closed.
I've updated git and the tarballs are also up now.
I plan on doing -rc2 on the 13th of February. I think my own queue is
looking rather reasonable at this point, but that may be in part due to
moving a few bigger s
On Tue, Jan 24, 2017 at 11:06 PM, Wenyou Yang wrote:
> To avoid the failure of mdio_register(), add the .remove callback
> to unregister the mii_dev when remove the ethernet device.
>
> Signed-off-by: Wenyou Yang
Acked-by: Joe Hershberger
___
U-Boot m
On Mon, Jan 30, 2017 at 01:44:04PM +0100, Jean-Jacques Hiblot wrote:
>
>
> On 27/01/2017 00:36, Tom Rini wrote:
> >On Wed, Jan 25, 2017 at 11:21:32AM +0100, Jean-Jacques Hiblot wrote:
> >>
> >>On 24/01/2017 20:11, Tom Rini wrote:
> >>>On Tue, Jan 24, 2017 at 06:04:47PM +0100, Jean-Jacques Hiblot
On 01/30/2017 08:43 AM, york@nxp.com wrote:
> On 01/24/2017 02:35 AM, Prabhakar Kushwaha wrote:
>> eLBC IP clock is always a constant divisor of platform clock
>> pre-defined per SoC. Clock ratio register (LCRR) used in
>> current implementation governs eLBC IP output clock.
>>
>> So update eLB
On 01/30/2017 02:45 AM, Bharat Bhushan wrote:
> The stream ID allocation for Chasis3.0 devices,
> LS1088, LS2088 and LS2080, can be shared.
>
> This patch renames this accordingly.
>
> Signed-off-by: Bharat Bhushan
> ---
> .../asm/arch-fsl-layerscape/ls2080a_stream_id.h| 77
> ---
On 01/30/2017 02:56 AM, Ashish Kumar wrote:
> From: Prabhakar Kushwaha
>
> SerDes information is not necessary to be present in RCWSR29 register.
> It may vary from SoC to SoC.
>
> So Avoid RCWSR28 register hard-coding.
>
> Signed-off-by: Prabhakar Kushwaha
Ashish,
Please add your signature nex
On 01/30/2017 02:19 AM, Ashish Kumar wrote:
> From: Prabhakar Kushwaha
>
> MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.
>
> So move QSGMII wriop_init_dpmac() to SoC file.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
> .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c|
On 01/24/2017 02:35 AM, Prabhakar Kushwaha wrote:
> eLBC IP clock is always a constant divisor of platform clock
> pre-defined per SoC. Clock ratio register (LCRR) used in
> current implementation governs eLBC IP output clock.
>
> So update eLBC IP clock to be defined as per predefined clock
> divi
On 01/24/2017 02:35 AM, Prabhakar Kushwaha wrote:
> Enable ELBC from Kconfig.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
> arch/powerpc/cpu/mpc85xx/Kconfig| 26 ++
> include/configs/MPC8313ERDB.h | 1 -
> include/configs/MPC8315ERDB.h | 1 -
> include/co
On 01/29/2017 11:24 PM, Vinitha Pillai-B57223 wrote:
> From: Vinitha Pillai
>
> Raw uboot image is used in place of FIT image in secure boot.
> The maximum allocated size of raw u-boot bin is 1MB in memory map.
> Hence , CONFIG_SYS_MONITOR_LEN has been modified to 1 MB.
> The bootscript (BS_ADDR)
On 01/30/2017 05:42 AM, Suresh Gupta wrote:
> From: Suresh Gupta
>
> USB High Speed (HS) EYE Height Adjustment
> USB HS speed eye diagram fails with the default value at
> many corners, particularly at a high temperature
>
> Optimal eye at TXVREFTUNE value to 1001 is observed, change
> set the sam
On 01/29/2017 11:24 PM, Vinitha Pillai-B57223 wrote:
> From: Vinitha Pillai
>
> Raw uboot image is used in place of FIT image in secure boot.
> The maximum allocated size of raw u-boot bin is 1MB in memory map.
> Hence , CONFIG_SYS_MONITOR_LEN has been modified to 1 MB.
> The bootscript (BS_ADDR)
On 01/30/2017 03:09 AM, Prabhakar Kushwaha wrote:
> Hi York,
>
>
>> -Original Message-
>> From: york sun
>> Sent: Saturday, January 28, 2017 2:15 AM
>> To: Prabhakar Kushwaha ; Bogdan Purcareata
>> ; u-boot@lists.denx.de
>> Subject: Re: [PATCH] drivers: net: fsl-mc: Fixup MAC addresses in D
On 23/01/2017 18:45, Tom Rini wrote:
> On Mon, Jan 23, 2017 at 05:20:25PM +, linux-kernel-dev wrote:
>>> From: Tom Rini [mailto:tr...@konsulko.com]
>>> Sent: Montag, 23. Januar 2017 16:31
>>>
>>> On Mon, Jan 23, 2017 at 03:11:27PM +0100, linux-kernel-...@beckhoff.com
>>> wrote:
>>>
From: P
From: Nishanth Menon
AM571x IDK and AM572x IDK have optional LCD Kits that can be purchased.
These can be one of OSD101T2045 or the newer OSD101T2587. The LCD panel
itself has no registers that can be used to identify the panel, however,
the touchscreen controllers on the panels are different.
H
On Mon, 2017-01-30 at 16:07 +0100, Alexander Graf wrote:
> On 01/29/2017 12:05 AM, Dalon Westergreen wrote:
> >
> > From: Dalon Westergreen
> >
> > Remove the default environment as it is now in a common
> > header.
> >
> > Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
> > to set
From: Lokesh Vutla
Non OMAP platforms i.e. Keystone will also need to use the board
EEPROM helpers so let's make the macro platform independent.
Signed-off-by: Roger Quadros
Signed-off-by: Lokesh Vutla
---
arch/arm/include/asm/omap_common.h | 8 +---
board/ti/common/board_detect.h | 2
PRU ethernet MAC address range is present in the
board EEPROM. Parse it and setup eth?addr
environment variables.
Signed-off-by: Roger Quadros
---
board/ti/ks2_evm/board_k2g.c | 19 +++
configs/k2g_evm_defconfig| 2 ++
2 files changed, 21 insertions(+)
diff --git a/board/ti
Use the same convention that was used for ICSS1 Ethernet
- If pin is output, set as PIN_OUTPUT
- If pin is input and external pull resistor present set as PIN_INPUT
- If pin is input and external pull resistor absent, set pull to same
as that of the external PHY's internall pull.
Signed-off-by: Ro
In stead of defining the board EEPROM address in the board headers
let's define them in the board config files and make them
configurable by Kconfig.
Signed-off-by: Roger Quadros
---
arch/arm/Kconfig | 10 ++
configs/am57xx_evm_defconfig | 2 ++
configs/am57xx_evm_
GPIO_TO_PIN(bank, bank_gpio) returns the GPIO index
from the GPIO bank number and bank's GPIO offset number.
Signed-off-by: Roger Quadros
Reviewed-by: Tom Rini
---
arch/arm/include/asm/arch-omap5/gpio.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-omap5/gpio
The board can support either ICSS1 Ethernet ports or LCD
based on J51 jumper. Factory default is ICSS1 Ethernet ports
(i.e. Jumper not populated).
Use the GPIO to detect the jumper setting and configure the
pinmux accordingly. Also select the right DT blob based on
the chosen configuration.
J51 a
Hi,
This series contains
- Support am571x-idk LCD vs 6 port ethernet pinmux configuration.
- AM57xx-idk LCD detection support.
- K2G: pick up PRUSS ethernet MAC addresses from board EEPROM.
Changelog:
v2:
- avoid using __maybe_unused.
- moved EEPROM address configuration to Kconfig.
- LCD detect
Keystone and OMAP platforms will need this to set ethernet
MAC addresses from board EEPROM.
Signed-off-by: Roger Quadros
---
board/ti/common/board_detect.c | 57 ++
board/ti/common/board_detect.h | 12 +
2 files changed, 69 insertions(+)
diff --gi
On 01/30/2017 04:11 PM, Dalon Westergreen wrote:
On Mon, 2017-01-30 at 15:55 +0100, Alexander Graf wrote:
On 01/29/2017 12:05 AM, Dalon Westergreen wrote:
From: Dalon Westergreen
Move repeated environment settings for socfpga boards
to a common header.
The default values for the boot partiti
On Mon, 2017-01-30 at 15:55 +0100, Alexander Graf wrote:
> On 01/29/2017 12:05 AM, Dalon Westergreen wrote:
> >
> > From: Dalon Westergreen
> >
> > Move repeated environment settings for socfpga boards
> > to a common header.
> >
> > The default values for the boot partition and the
> > OS file
On 01/29/2017 12:05 AM, Dalon Westergreen wrote:
From: Dalon Westergreen
Remove the default environment as it is now in a common
header.
Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
to set the linux devicetree name.
Signed-off-by: Dalon Westergreen
Acked-by: Marek Vasut
Acked
On 01/29/2017 12:05 AM, Dalon Westergreen wrote:
From: Dalon Westergreen
Remove the default environment as it is now in a common
header.
Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
to set the linux devicetree name.
Signed-off-by: Dalon Westergreen
Acked-by: Marek Vasut
---
On 01/29/2017 12:05 AM, Dalon Westergreen wrote:
From: Dalon Westergreen
Move repeated environment settings for socfpga boards
to a common header.
The default values for the boot partition and the
OS filesystem partition have changed and as
as result the default uboot environment for socfpga
b
Hi York,
> -Original Message-
> From: york sun
> Sent: Saturday, January 28, 2017 2:15 AM
> To: Prabhakar Kushwaha ; Bogdan Purcareata
> ; u-boot@lists.denx.de
> Subject: Re: [PATCH] drivers: net: fsl-mc: Fixup MAC addresses in DPC
>
> On 01/26/2017 05:05 AM, Prabhakar Kushwaha wrote:
>
On 01/29/2017 04:13 AM, Dalon Westergreen wrote:
From: Dalon Westergreen
the socfpga bootrom supports mmc booting from either a raw image
starting at 0x0, or from a partition of type 0xa2. This patch
adds support for locating the boot image in the first type 0xa2
partition found.
Signed-off-b
> -Original Message-
> From: york sun
> Sent: Friday, January 27, 2017 11:13 PM
> To: Priyanka Jain ; u-boot@lists.denx.de
> Cc: Arpit Goel
> Subject: Re: [PATCH 2/3] armv8: fsl-lsch3: Update VID support
>
> On 01/18/2017 09:43 PM, Priyanka Jain wrote:
> > VID support in NXP layerscape
Hi !
I'm wondering why the is_hab_enabled function (see
arch/arm/imx-common/hab.c) is reading the fuses rather than the OCOTP
shadow registers ?
During my attempts at secure boot I realized two things:
- by default, if secure boot is not enabled, the HAB rom will block any
authenticate code
- if th
From: Vincent Tinelli
On some cases the first 440 bytes of MBR are used to keep an additional
information for ROM boot loader. 'gpt write' command doesn't preserve
that area and makes boot code gone.
Preserve boot code area when run 'gpt write' command.
Signed-off-by: Vincent Tinelli
Signed-of
On 27/01/2017 00:36, Tom Rini wrote:
On Wed, Jan 25, 2017 at 11:21:32AM +0100, Jean-Jacques Hiblot wrote:
On 24/01/2017 20:11, Tom Rini wrote:
On Tue, Jan 24, 2017 at 06:04:47PM +0100, Jean-Jacques Hiblot wrote:
On 24/01/2017 16:46, Tom Rini wrote:
I had noticed that it's quite old indeed.
eLBC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock ratio register (LCRR) used in
current implementation governs eLBC IP output cloc.
Update sys_info->freq_localbus to represent eLBC input clock with
value constant divisor of platform clock.
Signed-off-by: Prab
From: Prabhakar Kushwaha
MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.
So move QSGMII wriop_init_dpmac() to SoC file.
Signed-off-by: Prabhakar Kushwaha
---
.../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c| 27 +
.../include/asm/arch-fsl-layerscape/
The PPA implements PSCI which requires for power managment.
Added support of PPA for LS1012AQDS, LS1012ARDB and LS1012AFRDM.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Abhimanyu Saini
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Enabled FSL_LS_PPA
Changes for v3: Rebased and updated a
> -Original Message-
> From: york sun
> Sent: Saturday, January 28, 2017 2:10 AM
> To: Prabhakar Kushwaha ; u-
> b...@lists.denx.de
> Cc: Z.Q. Hou ; Abhimanyu Saini
>
> Subject: Re: [PATCH 2/2][v3] armv8: ls1012a: Add support of PPA
>
> On 01/26/2017 08:09 PM, Prabhakar Kushwaha wrote:
>
PPA binary needs to be relocated on secure DDR, hence marking out
a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag
is set
Signed-off-by: Hou Zhiqiang
Signed-off-by: Abhimanyu Saini
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
Changes for v3: Rebased top
From: Prabhakar Kushwaha
SerDes information is not necessary to be present in RCWSR29 register.
It may vary from SoC to SoC.
So Avoid RCWSR28 register hard-coding.
Signed-off-by: Prabhakar Kushwaha
---
.../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c| 28 +++
.../include/
Sets the tapdelays for eMMC HS200 mode support for
ZynqMP as tapdelays needs to be programmed for it to
work
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- None
---
board/xilinx/zynqmp/tap_delays.c | 1 +
drivers/mmc/zynq_sdhci.c | 2 +-
2 files changed, 2 insertions(+)
This patch series adds support SD3.0 and eMMC HS200
modes for ZynqMP. This series also contains changes
in mmc and sdhci framework to support SD3.0 and HS200.
Siva Durga Prasad Paladugu (15):
mmc: sdhci: Update host capabilities about host controller
mmc: Add support for SD3.0
mmc: sdhci: Ad
Enable ELBC from Kconfig.
Signed-off-by: Prabhakar Kushwaha
---
Changes for v5: Added first time in the patch set
Changes for v6: Sending as it is
arch/powerpc/cpu/mpc85xx/Kconfig| 26 ++
include/configs/MPC8313ERDB.h | 1 -
include/configs/MPC8315ERDB.h
IFC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock control register (CCR) used in
current implementation governs IFC IP output clock.
Update sys_info->freq_localbus to represent IFC input clock with
value constant divisor of platform clock.
Signed-off-by: Prabh
IFC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock control register (CCR) used in
current implementation governs IFC IP output clock.
Update sys_info->freq_localbus to represent IFC input clock with
value constant divisor of platform clock.
Signed-off-by: Prabh
Enable IFC from Kconfig.
Signed-off-by: Prabhakar Kushwaha
---
Changes for v5: Added first time
Changes for v6: Sending as it is
arch/powerpc/cpu/mpc85xx/Kconfig | 17 +
include/configs/B4860QDS.h | 1 -
include/configs/BSC9131RDB.h | 1 -
include/configs/BSC9132QDS.
Update host capabilities for driver with host controller
information related to UHS modes incase of SD and HS200
mode incase of eMMC.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- None
---
drivers/mmc/sdhci.c | 28 +++-
include/mmc.h | 7 +++
Add support to execute platform/board specific tuning needed
for SDR104 and SDR50 UHS modes.This patch adds hook routine
to support specific tuning requirements.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- None
---
drivers/mmc/sdhci.c | 8
include/sdhci.h | 1 +
Add SD3.0 support for ZynqMP, this support needs a
platform specific tuning and tap delays for UHS
modes of SD3.0 and this patch takes care of it.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- None
---
board/xilinx/zynqmp/Makefile | 1 +
board/xilinx/zynqmp/tap_delays.c
Boot partition is not supported in HS200 mode, hence change
clock to high speed while accessing boot partition and
revert back when partition is switching to other than boot
partition
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- Added this in series as per review comment
---
Make the naming scheme consistent; all SDHCI-base drivers prefixed
with CONFIG_MMC_SDHCI_.
While we are here, add "depends on ARCH_ROCKCHIP".
Signed-off-by: Masahiro Yamada
---
Changes in v2: None
configs/evb-rk3399_defconfig | 2 +-
drivers/mmc/Kconfig | 15 ---
drivers
[1] Rename CONFIG_SANDBOX_MMC to CONFIG_MMC_SANDBOX for consistency
I want all MMC driver options prefixed with CONFIG_MMC_.
[2] Fix dependency
Add necessary depends on to avoid compile error.
Instead "depends on MMC" is unneeded because this config entry
resides inside of "if MMC"
Make the naming scheme consistent; all SDHCI-base drivers prefixed
with CONFIG_MMC_SDHCI_.
While we are here, add "depends on ARCH_ZYNQ || ARCH_ZYNQMP".
Signed-off-by: Masahiro Yamada
---
Changes in v2: None
arch/arm/mach-zynq/Kconfig | 2 +-
configs/topic_miami_defconf
Make the naming scheme consistent; all SDHCI-base drivers prefixed
with CONFIG_MMC_SDHCI_.
While we are here, add "depends on ARCH_AT91".
Signed-off-by: Masahiro Yamada
---
Changes in v2: None
configs/sama5d2_xplained_mmc_defconfig | 2 +-
configs/sama5d2_xplained_spiflash_defconfig |
Make the naming scheme consistent; all SDHCI-base drivers prefixed
with CONFIG_MMC_SDHCI_.
Signed-off-by: Masahiro Yamada
---
Changes in v2: None
configs/dragonboard410c_defconfig | 2 +-
drivers/mmc/Kconfig | 20 ++--
drivers/mmc/Makefile | 2 +-
3
Make the naming scheme consistent; all SDHCI-base drivers prefixed
with CONFIG_MMC_SDHCI_.
Signed-off-by: Masahiro Yamada
---
Changes in v2: None
configs/pic32mzdask_defconfig | 2 +-
drivers/mmc/Kconfig | 14 +++---
drivers/mmc/Makefile | 2 +-
3 files changed, 9
Now, CONFIG_GENERIC_MMC seems equivalent to CONFIG_MMC.
Let's create an entry for "config GENERIC_MMC" with "default MMC",
then convert all macro defines in headers to Kconfig. Almost all
of the defines will go away.
I see only two exceptions:
configs/blanche_defconfig
configs/sandbox_noblk_
Update execute tuning and set clock to support for
HS200 mode.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- Split the patch with only sdhci related changes
---
drivers/mmc/sdhci.c | 18 +-
include/mmc.h | 1 +
2 files changed, 14 insertions(+), 5 deleti
Update quirk if 1.8 voltage switching is not supported
on boards by reading the property "no-1-8-v" from device
tree.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- None
---
drivers/mmc/zynq_sdhci.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/mmc/zynq_s
Define routines of mmio write and read functionalities
for zynqmp platform.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- None
---
arch/arm/cpu/armv8/zynqmp/cpu.c | 51
arch/arm/include/asm/arch-zynqmp/sys_proto.h | 3 ++
2 files chan
Add support for eMMC HS200 mode by reading
card type from ext_csd and then by switching to
HS200 timing mode.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- Split the patch with only mmc changes
---
drivers/mmc/mmc.c | 24 ++--
include/mmc.h | 7 +++
Deine private structure arasan_sdhci_priv instead of sdhci_host
as private. This allows us in adding more private data as required
for usage in driver.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- None
---
drivers/mmc/zynq_sdhci.c | 19 +++
1 file changed, 15
Make sdhci_ops of host modifiable as ops may contain
platform specific funtion pointers which may need
to be defined for some platforms(example: platform specific
tuning and delays)
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- None
---
include/sdhci.h | 2 +-
1 file changed,
Add quirk if voltage switching to 1.8v is broken, in this
case no UHS modes were supported
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- None
---
drivers/mmc/sdhci.c | 3 ++-
include/sdhci.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/s
Add support for any platform/board specific delays
requirement while setting clocks. Some boards needs
to program tapdelay for setting certain high frequencies
and this patch adds hook for supporting the same.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- None
---
drivers/mmc/
Add support for all UHS modes of SD3.0.
This patch defines the routines to switch
volatge, setting uhs modes and execute tuning
as these are needed for SD3.0 support
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- Split the patch with only sdhci changes
as per comment
---
driv
The SD3.0 needs voltage switching to 1.8V
based on host and cards capabilities and also
needs to switch to one of the uhs modes based
on cards capability. This supports frequencies
till 200MHz. This patch define hooks to perform
the same at sdhci driver level.
Signed-off-by: Siva Durga Prasad Pala
Hi Jagan,
On 30/01/2017 10:41, Jagan Teki wrote:
>> You are the board maintainer, and it is your decision. Anyway, clocks
>> are not disable in u-boot, and they can remain on in Linux, because they
>> are set just if needed. Some kernels had disabled in the past for some
>> platform (I know OMAP3
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