On Wed, Sep 21, 2016 at 10:02:47AM -0400, Tom Rini wrote:
> On Wed, Sep 21, 2016 at 03:46:08PM +0200, Enric Balletbo Serra wrote:
> > 2016-09-21 14:51 GMT+02:00 Tom Rini :
> > > On Wed, Sep 21, 2016 at 01:46:51PM +0200, Enric Balletbo Serra wrote:
> > >> Hi,
> > >>
> > >> 2016-09-21 11:39 GMT+02:00
Hi Sandy,
On 09/21/2016 08:41 PM, Sandy Patterson wrote:
On Tue, Sep 20, 2016 at 10:56 PM, Kever Yang
mailto:kever.y...@rock-chips.com>> wrote:
parameters changes from dts to auto-detect including those I
removed from dts and ddrconfig, stride, they should be the same as
without
Hi Sandy,
On 09/21/2016 07:53 PM, Sandy Patterson wrote:
On Tue, Sep 20, 2016 at 11:00 PM, Kever Yang
mailto:kever.y...@rock-chips.com>> wrote:
Hi Sandy,
On 09/20/2016 09:21 PM, Sandy Patterson wrote:
You're probably going to need to change this around now that the
Kconfig
Enable the NAND interface on this board.
Signed-off-by: Chris Packham
---
Changes in v2: None
arch/arm/dts/armada-385-amc.dts | 8
configs/db-88f6820-amc_defconfig | 2 ++
include/configs/db-88f6820-amc.h | 4
3 files changed, 14 insertions(+)
diff --git a/arch/arm/dts/armada-3
This board is a plug in card for Marvell's switch system development
kits. Form-factor aside it is similar to the DB-88F6820-GP with the
following differences.
- TCLK is 200MHz
- SPI1 is used
- No SATA
- No MMC
- NAND flash
Reviewed-by: Simon Glass
Signed-off-by: Chris Packham
---
I've used my w
88F6820 is a specific Armada-38x chip that is used on the DB-88F6820-GP
board. Rather than having DB_88F6820_GP and TARGET_DB_88F6820_GP which
selects the former. Rename DB_88F6820_GP to 88F6820 so that other boards
using the 88F6820 can be added.
Signed-off-by: Chris Packham
---
Changes in v2:
On 09/21/2016 08:45 AM, Tom Rini wrote:
> On Wed, Sep 21, 2016 at 03:22:59PM +, york sun wrote:
>> On 09/20/2016 03:30 PM, Tom Rini wrote:
>>> On Tue, Sep 20, 2016 at 09:40:00PM +, york sun wrote:
On 09/20/2016 02:36 PM, Tom Rini wrote:
> On Tue, Sep 20, 2016 at 09:22:09PM +, y
Tom,
I made these patches on top of my fsl-qoriq master. Once merged,
the ad-hoc config error should not appear. In this set, I start to convert
some options to Kconfig. Please let me know if this is the right solution. I
also convert the MMDC driver to use data structure as you suggested. Do not
Instead of using multiple macros, a data structure is used to pass
board-specific parameters to MMDC DDR driver.
Signed-off-by: York Sun
CC: Shengzhou Liu
---
board/freescale/ls1012afrdm/ls1012afrdm.c | 18 ++-
board/freescale/ls1012aqds/ls1012aqds.c | 18 ++-
board/fr
On 09/21/2016 04:25 AM, Chin Liang See wrote:
> To enable configuration of sdr.ctrlcfg.extratime1 register which enable
> extra clocks for read to write command timing. This is critical to
> ensure successful LPDDR2 interface
>
> Signed-off-by: Chin Liang See
> Cc: Marek Vasut
> Cc: Dinh Nguyen
It should be EMMC_BOOT instead of CONFIG_EMMC_BOOT.
Signed-off-by: York Sun
CC: Gong Qianyu
---
configs/ls1046ardb_emmc_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/ls1046ardb_emmc_defconfig
b/configs/ls1046ardb_emmc_defconfig
index 2daddf4..a1ee1ab 100
Move this config to Kconfig option and clean up existing uses.
Signed-off-by: York Sun
CC: Calvin Johnson
CC: Prabhakar Kushwaha
---
arch/arm/Kconfig | 3 +++
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 +++
arch/arm/cpu/armv8/fsl-layers
Move this option to Kconfig and clean up existing uses.
Signed-off-by: York Sun
CC: Hou Zhiqiang
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 12
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 -
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch
Move this option to Kconfig and clean up existing uses.
Signed-off-by: York Sun
CC: Mingkai Hu
CC: Gong Qianyu
---
arch/arm/Kconfig | 4
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 ++
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 2 +-
arc
On Wed, Sep 21, 2016 at 03:51:17PM -0700, York Sun wrote:
> Move this option to Kconfig and clean up existing uses.
>
> Signed-off-by: York Sun
> CC: Hou Zhiqiang
Reviewed-by: Tom Rini
--
Tom
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U-Bo
On Wed, Sep 21, 2016 at 03:51:18PM -0700, York Sun wrote:
> It should be EMMC_BOOT instead of CONFIG_EMMC_BOOT.
>
> Signed-off-by: York Sun
> CC: Gong Qianyu
Reviewed-by: Tom Rini
--
Tom
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___
U-Boot ma
On Wed, Sep 21, 2016 at 03:51:15PM -0700, York Sun wrote:
> Instead of using multiple macros, a data structure is used to pass
> board-specific parameters to MMDC DDR driver.
>
> Signed-off-by: York Sun
> CC: Shengzhou Liu
Thanks for doing this!
Reviewed-by: Tom Rini
--
Tom
signature.asc
On Wed, Sep 21, 2016 at 03:51:16PM -0700, York Sun wrote:
> Move this config to Kconfig option and clean up existing uses.
>
> Signed-off-by: York Sun
> CC: Calvin Johnson
> CC: Prabhakar Kushwaha
Reviewed-by: Tom Rini
--
Tom
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On Wed, Sep 21, 2016 at 03:51:14PM -0700, York Sun wrote:
> Move this option to Kconfig and clean up existing uses.
>
> Signed-off-by: York Sun
> CC: Mingkai Hu
> CC: Gong Qianyu
Reviewed-by: Tom Rini
--
Tom
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Move U_BOOT_DRIVER() entry from the data file (clk-uniphier-mio.c)
to the core support file (clk-uniphier-core.c) because I do not want
to repeat the driver boilerplate when I add more clock data.
Signed-off-by: Masahiro Yamada
---
drivers/clk/uniphier/clk-uniphier-core.c | 88 +
- Add PLL init code for LD11 SoC
- Cleanup clk driver
- Sync Device Trees
Masahiro Yamada (5):
ARM: uniphier: add PLL init code for LD11 SoC
clk: uniphier: constify clock data arrays/structures
clk: uniphier: move U_BOOT_DRIVER entry to core code
clk: uniphier: allow to have clock
- Initialize PLLs (SPL initializes only DPLL to save the precious
SPL memory footprint)
- Adjust CPLL/MPLL to the final tape-out frequency
- Accelerate the Cortex-A53 clock to the maximum frequency since
it is running at 500MHz (SPLL/4) on startup
Signed-off-by: Masahiro Yamada
---
arc
Sync device trees with Linux for easier DT life.
Signed-off-by: Masahiro Yamada
---
arch/arm/dts/uniphier-common32.dtsi | 56 +--
arch/arm/dts/uniphier-ph1-ld11.dtsi | 80
arch/arm/dts/uniphier-ph1-ld20.dtsi | 75 ++
To sync the DT binding with Linux, the register base must be taken
from the parent syscon node.
Signed-off-by: Masahiro Yamada
---
drivers/clk/uniphier/clk-uniphier-core.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/uniphier/clk-uniphier-co
Clarify these clock data are constant.
Signed-off-by: Masahiro Yamada
---
drivers/clk/uniphier/clk-uniphier-core.c | 6 +++---
drivers/clk/uniphier/clk-uniphier-mio.c | 6 +++---
drivers/clk/uniphier/clk-uniphier.h | 6 +++---
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a
2016-09-21 11:28 GMT+09:00 Masahiro Yamada :
> Unlike Linux, nothing about errno.h is arch-specific in U-Boot.
> As you see, all of arch/${ARCH}/include/asm/errno.h is just a
> wrapper of . Actually, U-Boot does not
> export headers to user-space, so we just have to care about the
> consistency in
Hi,
Am Donnerstag, 28. Juli 2016, 21:46:04 schrieb Doug Anderson:
> On Mon, Jul 11, 2016 at 7:45 PM, Kever Yang
wrote:
> > Hi Simon,
> >
> > CC Doug for this topic.
> >
> > On 07/12/2016 07:54 AM, Simon Glass wrote:
> >> Hi Kever,
> >>
> >> On 11 July 2016 at 00:58, Kever Yang wrote:
> >>> H
Signed-off-by: Tom Rini
---
You don't need to issue a new series for just this change, but I had to
fix clk.h for today.
---
include/clk.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/clk.h b/include/clk.h
index 94c003714700..5a5c2ff1e674 100644
--- a/include/clk.h
Since we return -ENOSYS in some cases we must have
available.
Signed-off-by: Tom Rini
---
include/clk.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/clk.h b/include/clk.h
index 9b2452268d40..94c003714700 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -10,6 +10,7 @@
#define _C
From: Jagan Teki
Moved FSL_QSPI/SPI/SPI-FLASH configs from include/configs
into respective used defconfigs.
- CONFIG_FSL_QSPI
- CONFIG_SPI_FLASH
- CONFIG_SPI_FLASH_BAR
- CONFIG_SPI_FLASH_STMICRO
Cc: Stefano Babic
Cc: Peng Fan
Signed-off-by: Jagan Teki
---
configs/mx6sxsabreauto_defconfig |
From: Jagan Teki
Since FSL_QSPI driver still supporting non-dm code
better to move the Kconfig from DM undefined place.
Cc: Stefano Babic
Cc: Peng Fan
Signed-off-by: Jagan Teki
---
drivers/spi/Kconfig | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/
On Wed, Sep 7, 2016 at 3:18 PM, Vignesh R wrote:
> This patch series tries to improve QSPI write speed by writing 16 bytes
> at once whenever possible. Also remove unnecessary 100us delay for
> AM437x.
>
> Tested on AM437x SK, DRA74 and DRA72 EVM.
Applied to u-boot-spi/master
thanks!
--
Jagan T
On 09/21/2016 12:01 PM, Tom Rini wrote:
> On Wed, Sep 21, 2016 at 04:07:49PM +, york sun wrote:
>> On 09/21/2016 08:45 AM, Tom Rini wrote:
>>> On Wed, Sep 21, 2016 at 03:22:59PM +, york sun wrote:
On 09/20/2016 03:30 PM, Tom Rini wrote:
> On Tue, Sep 20, 2016 at 09:40:00PM +, y
On Wed, Sep 21, 2016 at 04:07:49PM +, york sun wrote:
> On 09/21/2016 08:45 AM, Tom Rini wrote:
> > On Wed, Sep 21, 2016 at 03:22:59PM +, york sun wrote:
> >> On 09/20/2016 03:30 PM, Tom Rini wrote:
> >>> On Tue, Sep 20, 2016 at 09:40:00PM +, york sun wrote:
> On 09/20/2016 02:36 P
Hi York,
PCIe couldn't work on ls1046a as the driver code is not updated yet.
So I removed the configs from board files. And Minghuan has been
working on the PCIe driver patch.
Hi Mingkai and Shengzhou,
Could you please help on the DDR option question? Thanks.
Regards,
Qianyu
> -Original
H3 seems to have a silicon bug breaking the impedance calibration.
This is currently worked around in software by multiple steps
combining the results to replace the wrong values.
Revision A chips need a different workaround, which is present in
the vendor bootloader too, but got overlooked in lac
On Wed, Sep 21, 2016 at 03:22:59PM +, york sun wrote:
> On 09/20/2016 03:30 PM, Tom Rini wrote:
> > On Tue, Sep 20, 2016 at 09:40:00PM +, york sun wrote:
> >> On 09/20/2016 02:36 PM, Tom Rini wrote:
> >>> On Tue, Sep 20, 2016 at 09:22:09PM +, york sun wrote:
> >>>
> Tom and Simon,
Hi Tom,
this pull-request introduces:
- new board: MIPSfpga
- new board: Boston with variants for MIPS32r2/MIPS64r2 and BE/LE
- updates to DM core code needed for Boston board
- support for L2 cache and MIPS coherency manager
- various fixes on cache initialization
The following changes since co
On 09/20/2016 03:30 PM, Tom Rini wrote:
> On Tue, Sep 20, 2016 at 09:40:00PM +, york sun wrote:
>> On 09/20/2016 02:36 PM, Tom Rini wrote:
>>> On Tue, Sep 20, 2016 at 09:22:09PM +, york sun wrote:
>>>
Tom and Simon,
After commit 371244cb19f9804711dd66e4281ff7979915fd2e, all m
On Wed, Sep 21, 2016 at 10:15 AM, Stefan Roese wrote:
> On 21.09.2016 17:12, Marek Vasut wrote:
>>
>> On 09/20/2016 07:17 PM, Paul Burton wrote:
>>>
>>> Commit bac17b78dace ("image-fit: switch ENOLINK to ENOENT") changed
>>> fit_get_node_from_config to return -ENOENT when a property doesn't
>>> ex
On 09/21/2016 12:46 AM, Mingkai Hu wrote:
>
>
>> -Original Message-
>> From: york sun
>> Sent: Saturday, September 17, 2016 4:14 AM
>> To: Q.Y. Gong ; u-boot@lists.denx.de
>> Cc: Prabhakar Kushwaha ; Mingkai Hu
>> ; S.H. Xie ; Z.Q. Hou
>> ; Wenbin Song ;
>> Shengzhou Liu
>> Subject: Re: [P
On Mon, Sep 19, 2016 at 10:05:45PM -0400, Tom Rini wrote:
> There are a few boards that use CONFIG_ISO_STRING as part of a sanity
> check during firmware update at run time. Move this string to Kconfig.
>
> Signed-off-by: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
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On Fri, Jul 29, 2016 at 03:31:47PM +0530, Siva Durga Prasad Paladugu wrote:
> Move the config IDENT_STRING to Kconfig and migrate all boards
>
> [sivadur: Migrate zynq boards]
> Signed-off-by: Siva Durga Prasad Paladugu
> [trini: Update configs, add some default to sunxi Kconfig]
> Signed-off-by
On Sun, Sep 18, 2016 at 09:09:39PM -0600, Simon Glass wrote:
> Hi Tom,
>
> This includes some refactoring to improve the dtoc code.
>
>
> The following changes since commit 9a6535e05f17acf03e891266a650cb6029124743:
>
> Merge branch 'master' of git://git.denx.de/u-boot-uniphier
> (2016-09-18
On Mon, Sep 19, 2016 at 10:05:44PM -0400, Tom Rini wrote:
> Convert CONFIG_MIP405T from SYS_EXTRA_OPTIONS to a real config
>
> There are two boards, MIP405 and MIP405T that have a few differences.
> Start by checking for CONFIG_TARGET_MIP405. Then introduce
> CONFIG_TARGET_MIP405T and use that n
On 21.09.2016 17:12, Marek Vasut wrote:
On 09/20/2016 07:17 PM, Paul Burton wrote:
Commit bac17b78dace ("image-fit: switch ENOLINK to ENOENT") changed
fit_get_node_from_config to return -ENOENT when a property doesn't
exist, but didn't change any of its callers which check return values.
Notably
On 09/20/2016 07:17 PM, Paul Burton wrote:
> Commit bac17b78dace ("image-fit: switch ENOLINK to ENOENT") changed
> fit_get_node_from_config to return -ENOENT when a property doesn't
> exist, but didn't change any of its callers which check return values.
> Notably it didn't change boot_get_ramdisk,
On Wednesday, 21 September 2016 16:19:58 BST Daniel Schwierzeck wrote:
> Am 21.09.2016 um 15:59 schrieb Paul Burton:
> > Some systems are configured such that multiple CPUs begin running from
> > their reset vector following a system reset. If this occurs then U-Boot
> > will be run on multiple CPU
Am 21.09.2016 um 15:59 schrieb Paul Burton:
> Some systems are configured such that multiple CPUs begin running from
> their reset vector following a system reset. If this occurs then U-Boot
> will be run on multiple CPUs simultaneously, which causes all sorts of
> issues as the multiple instance
Paul Burton writes:
> Some systems are configured such that multiple CPUs begin running from
> their reset vector following a system reset. If this occurs then U-Boot
> will be run on multiple CPUs simultaneously, which causes all sorts of
> issues as the multiple instances of U-Boot clobber each
Some systems are configured such that multiple CPUs begin running from
their reset vector following a system reset. If this occurs then U-Boot
will be run on multiple CPUs simultaneously, which causes all sorts of
issues as the multiple instances of U-Boot clobber each other.
Prevent this from hap
On Wednesday, 21 September 2016 14:51:05 BST Matthew Fortune wrote:
> Paul Burton writes:
> > Some systems are configured such that multiple CPUs begin running from
> > their reset vector following a system reset. If this occurs then U-Boot
> > will be run on multiple CPUs simultaneously, which ca
The Kconfig entry for L2 cache support is MIPS_L2_CACHE, not MIPS_L2.
Fix that.
Signed-off-by: Paul Burton
---
Feel free to fold this into "boston: Introduce support for the MIPS
Boston development board" as it's a minor fixup.
arch/mips/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deleti
On Wed, Sep 21, 2016 at 03:46:08PM +0200, Enric Balletbo Serra wrote:
> 2016-09-21 14:51 GMT+02:00 Tom Rini :
> > On Wed, Sep 21, 2016 at 01:46:51PM +0200, Enric Balletbo Serra wrote:
> >> Hi,
> >>
> >> 2016-09-21 11:39 GMT+02:00 Ladislav Michl :
> >> > On Tue, Sep 20, 2016 at 08:26:36PM -0400, Tom
On Wednesday, 21 September 2016 15:14:41 BST Daniel Schwierzeck wrote:
> Hi Paul,
>
> Am 21.09.2016 um 12:08 schrieb Paul Burton:
> > Some systems are configured such that multiple CPUs begin running from
> > their reset vector following a system reset. If this occurs then U-Boot
> > will be run o
2016-09-21 14:51 GMT+02:00 Tom Rini :
> On Wed, Sep 21, 2016 at 01:46:51PM +0200, Enric Balletbo Serra wrote:
>> Hi,
>>
>> 2016-09-21 11:39 GMT+02:00 Ladislav Michl :
>> > On Tue, Sep 20, 2016 at 08:26:36PM -0400, Tom Rini wrote:
>> >> On Wed, Sep 21, 2016 at 01:52:21AM +0200, Ladislav Michl wrote:
Some systems are configured such that multiple CPUs begin running from
their reset vector following a system reset. If this occurs then U-Boot
will be run on multiple CPUs simultaneously, which causes all sorts of
issues as the multiple instances of U-Boot clobber each other.
Prevent this from hap
Hi Jaehoon,
On Tue, Sep 20, 2016 at 08:10:52AM +0900, Jaehoon Chung wrote:
> On 09/19/2016 10:17 PM, Maxime Ripard wrote:
> > On Wed, Sep 14, 2016 at 12:05:19PM +0200, Hans de Goede wrote:
> >> Hi,
> >>
> >> On 13-09-16 13:50, Maxime Ripard wrote:
> >>> Hi,
> >>>
> >>> On Mon, Sep 12, 2016 at 04:4
On Wednesday, 21 September 2016 12:59:39 BST Langer, Thomas wrote:
> Hello Paul,
>
> > diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
> > index fc6dd66..dd37ac3 100644
> > --- a/arch/mips/cpu/start.S
> > +++ b/arch/mips/cpu/start.S
> > @@ -112,6 +112,31 @@ ENTRY(_start)
> >
> > .a
Hi Paul,
Am 21.09.2016 um 12:08 schrieb Paul Burton:
> Some systems are configured such that multiple CPUs begin running from
> their reset vector following a system reset. If this occurs then U-Boot
> will be run on multiple CPUs simultaneously, which causes all sorts of
> issues as the multiple
Hello Paul,
>
> diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
> index fc6dd66..dd37ac3 100644
> --- a/arch/mips/cpu/start.S
> +++ b/arch/mips/cpu/start.S
> @@ -112,6 +112,31 @@ ENTRY(_start)
>
> .align 4
> reset:
> +#if __mips_isa_rev >= 6
> + .setpush
> + .set
On Wed, Sep 21, 2016 at 01:46:51PM +0200, Enric Balletbo Serra wrote:
> Hi,
>
> 2016-09-21 11:39 GMT+02:00 Ladislav Michl :
> > On Tue, Sep 20, 2016 at 08:26:36PM -0400, Tom Rini wrote:
> >> On Wed, Sep 21, 2016 at 01:52:21AM +0200, Ladislav Michl wrote:
> >> > On Tue, Sep 20, 2016 at 07:45:14PM -
On Tue, Sep 20, 2016 at 10:56 PM, Kever Yang
wrote:
>
> parameters changes from dts to auto-detect including those I removed from
> dts and ddrconfig, stride, they should be the same as without my patch,
> which means my patch suppose to not change any parameter for DDR other than
> how we get tho
On Tue, Sep 20, 2016 at 11:00 PM, Kever Yang
wrote:
> Hi Sandy,
>
> On 09/20/2016 09:21 PM, Sandy Patterson wrote:
>
> You're probably going to need to change this around now that the Kconfig
> stuff has been applied to master. Suggest following patch instead:
>
>
> I didn't enable the BACK_TO_BR
Hi,
2016-09-21 11:39 GMT+02:00 Ladislav Michl :
> On Tue, Sep 20, 2016 at 08:26:36PM -0400, Tom Rini wrote:
>> On Wed, Sep 21, 2016 at 01:52:21AM +0200, Ladislav Michl wrote:
>> > On Tue, Sep 20, 2016 at 07:45:14PM -0400, Tom Rini wrote:
> [snip]
>> > > But why do we even need to set MACH_TYPE the
The linux kernel imx_v6_v7_defconfig sets the user/kernel memory split
to 3G/1G now (was 2G/2G before). We have to adapt the BOOTMAPSZ so that
the decompressor finds zImage and dtb in lowmem.
Signed-off-by: Soeren Moch
---
Cc: Stefano Babic
Cc: u-boot@lists.denx.de
---
include/configs/tbs2910.h
On Wed, Sep 21, 2016 at 1:31 AM, york sun wrote:
> On 09/19/2016 09:59 PM, macro.wav...@gmail.com wrote:
>> From: Hongbo Zhang
>>
>> ARMV7_PSCI depends on ARMV7_NONSEC && ARCH_SUPPORT_PSCI, and ARMV7_NONSEC
>> depends on CPU_V7_HAS_NONSEC, LS102XA didn't enable CPU_V7_HAS_NONSEC, but
>> defined A
From: Hongbo Zhang
Following commits 217f92b and 1544698, these two config CPU_V7_HAS_NONSEC
and CPU_V7_HAS_VIRT are moved to Kconfig, for correctly select ARMV7_PSCI.
Signed-off-by: Hongbo Zhang
---
arch/arm/Kconfig | 4
include/configs/ls1021aqds.h | 2 --
include/configs/ls
Ensure that cache operations complete before returning from
mips_cache_reset by placing a completion barrier (sync instruction)
before the return. Without this there is no guarantee that the cache ops
will complete before any subsequent memory accesses, since they are
indexed cache ops & thus not i
Writing to the coprocessor 0 TagLo registers introduces an execution
hazard in that we need that write to complete before any cache
instructions execute. Ensure that hazard is cleared by inserting an ehb
instruction between the TagLo writes & cache op loop.
Signed-off-by: Paul Burton
---
Change
During boot we set Config.K0=2 (uncached) such that any accesses to the
kseg0 memory region are performed uncached before the caches are
initialised. This write to the Config register introduces an execution
hazard between it & any following memory accesses (such as the load of
_gp), which we need
Enable support for the MIPS Coherence Manager & L2 caches on the MIPS
Malta board, removing the need for us to attempt to bypass the L2 during
boot (which would fail with recent CPUs that expose L2 config via the CM
anyway).
Signed-off-by: Paul Burton
---
Changes in v3: None
Changes in v2: None
This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.
If the L2 can be bypassed then we bypass it early i
MIPS Linux expects the bootloader to leave the boot CPU a member of the
coherent domain when running on a system with a CM, and we will need to
do so if we wish to make use of IOCUs to have cache-coherent DMA in
U-Boot (and on some systems there is no choice in that matter). When a
CM is present, j
Map the Global Control Registers (GCRs) provided by the MIPS Coherence
Manager (CM) in preparation for using some of them in later patches.
Signed-off-by: Paul Burton
---
Changes in v3: None
Changes in v2: None
arch/mips/Kconfig | 16
arch/mips/cpu/Makefile | 2 +
Define names for registers holding cache sizes throughout
mips_cache_reset, in order to make the code easier to read & allow for
changing register assignments more easily.
Signed-off-by: Paul Burton
---
Changes in v3: None
Changes in v2: None
arch/mips/lib/cache_init.S | 42 +++
On systems where cache initialisation doesn't require zeroed memory (ie.
systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined)
perform cache initialisation prior to lowlevel_init & DDR
initialisation. This allows for DDR initialisation code to run cached &
thus significantly faster.
Si
Rather than probing the cache line sizes on every call of any cache
maintenance function, probe them once during boot & store the values in
the global data structure for later use. This will reduce the overhead
of the cache maintenance functions, which isn't a big deal yet but
becomes more importan
The coprocessor 0 Config register includes 9 implementation defined
bits, which in some processors do things like enable write combining or
other functionality. We ought not to wipe them to 0 during boot. Rather
than doing so, preserve their value & only clear the bits standardised
by the MIPS arch
Enable use of the instruction cache immediately after it has been
initialised. This will only take effect if U-Boot was linked to run from
kseg0 rather than kseg1, but when this is the case the data cache
initialisation code will run cached & thus significantly faster.
Signed-off-by: Paul Burton
In order to prepare for MIPS arch code making use of arch_cpu_init in a
later patch, stop using it from ath79 SoC code & instead use the new
mach_cpu_init which is provided for this purpose.
Signed-off-by: Paul Burton
---
Changes in v3: None
Changes in v2:
- Rebase atop changes in patch 1
arc
Currently we have a mismash of architectures which use arch_cpu_init
from architecture-wide code (arc, avr32, blackfin, mips, nios2, xtensa)
and architectures which use arch_cpu_init from machine/SoC level code
(arm, x86).
In order to clean this mess up & allow for both use cases, introduce a
new
This series introduces support for initialising & maintaining L2 caches
on MIPS systems. This allows U-Boot to function correctly on systems
where such caches are present, whereas without performing L2 maintenance
it is likely to fail with cache coherence issues when writing code or
performing DMA
The relocate_code function was handling cache maintenance incorrectly.
It copied U-Boot to its new location, flushed the caches & then
proceeded to apply relocations & jump to the new code without flushing
the caches again. This is problematic as the instruction cache could
potentially have already
Some systems are configured such that multiple CPUs begin running from
their reset vector following a system reset. If this occurs then U-Boot
will be run on multiple CPUs simultaneously, which causes all sorts of
issues as the multiple instances of U-Boot clobber each other.
Prevent this from hap
On 09/21/2016 04:35 AM, Chin Liang See wrote:
> Update documentation to include the Cyclone V SoC Preloader
> development flow. This include the update of Preloader handoff
> through qts-filter.sh script. At same time, removed the SDMMC
> documentation as its using DM now.
Good stuff . s/folder/di
On 09/21/2016 03:53 AM, Chin Liang See wrote:
> On Wed, 2016-09-21 at 03:20 +0200, Marek Vasut wrote:
>> On 09/20/2016 08:05 AM, Chin Liang See wrote:
>>> To enable configuration of sdr.ctrlcfg.extratime1 register which
>>> enable
>>> extra clocks for read to write command timing. This is critical
On 09/21/2016 05:35 AM, Kever Yang wrote:
> Add a Kconfig for Rockchip xhci controller.
>
> Signed-off-by: Kever Yang
Acked-by: Marek Vasut
Feel free to pick it through rockchip tree .
--
Best regards,
Marek Vasut
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U-Boot@lis
Use atf-uboot.ub image instead of atf.ub.
Signed-off-by: Michal Simek
---
include/configs/xilinx_zynqmp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 9f1dd684685c..d92028c3e831 100644
--- a/include/c
On Tue, Sep 20, 2016 at 08:26:36PM -0400, Tom Rini wrote:
> On Wed, Sep 21, 2016 at 01:52:21AM +0200, Ladislav Michl wrote:
> > On Tue, Sep 20, 2016 at 07:45:14PM -0400, Tom Rini wrote:
[snip]
> > > But why do we even need to set MACH_TYPE these days?
> >
> > That's only needed for non-device tree
Hi,
I propose you this patch in order to take into account strings larger than
actual size (32). I recently faced to 'fastboot.partition-type:userdata'
(it was in Android context) but this could be the case for other purposes.
I propose to simply double the size. Is it ok for you?
Regards
---
On Sun, Sep 18, 2016 at 12:28 PM, Wenyou Yang wrote:
> Add driver model support while retaining the existing legacy code.
> This allows the driver to support boards that have converted to
> driver model as well as those that have not.
>
> Signed-off-by: Wenyou Yang
> Reviewed-by: Simon Glass
> A
Update documentation to include the Cyclone V SoC Preloader
development flow. This include the update of Preloader handoff
through qts-filter.sh script. At same time, removed the SDMMC
documentation as its using DM now.
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
---
doc/READ
On Fri, Sep 16, 2016 at 6:39 PM, Stefan Roese wrote:
> This patch adds the SPI device tree nodes that are still missing to
> the Armada 3700 dts files.
>
> Signed-off-by: Stefan Roese
> Cc: Nadav Haklai
> Cc: Kostya Porotchkin
> Cc: Wilson Ding
> Cc: Victor Gu
> Cc: Hua Jing
> Cc: Terry Zhou
On Fri, Sep 16, 2016 at 6:39 PM, Stefan Roese wrote:
> The SPI IP core in the Marvell Armada 3700 is similar to the one in the
> other Armada SoCs. But the differences are big enough that it makes
> sense to introduce a new driver instead of cluttering the old
> kirkwood driver with #ifdef's.
>
>
Dear Tom,
Could pull these patches on u-boot/master?
The following changes since commit 9b1b6d42256a4c2e59c803afdbf90d39371e61ba:
Revert "Increase default of CONFIG_SYS_MALLOC_F_LEN for SPL_OF_CONTROL"
(2016-09-19 15:20:09 -0400)
are available in the git repository at:
http://git.denx.de/
Hi Masahiro-san,
On Wed, 2016-09-21 at 11:01 +0900, Masahiro Yamada wrote:
> Unlike Linux, nothing about errno.h is arch-specific in U-Boot.
> As you see, all of arch/${ARCH}/include/asm/errno.h is just a
> wrapper of . Actually, U-Boot does not
> export headers to user-space, so we just have to
move the UBI config options into Kconfig.
Signed-off-by: Heiko Schocher
Reviewed-by: Simon Glass
Reviewed-by: Andrew F. Davis
Reviewed by: Evgeni Dobrev
---
Tested with tbot:
http://lists.denx.de/pipermail/u-boot/2016-June/258119.html
result:
Boards : 1196
compile err : 36
not checked :
Hello Andrew,
Am 20.09.2016 um 17:02 schrieb Tom Rini:
On Tue, Sep 20, 2016 at 09:26:15AM -0500, Andrew F. Davis wrote:
On 09/20/2016 12:50 AM, Heiko Schocher wrote:
Hello Andrew,
Am 19.09.2016 um 18:03 schrieb Andrew F. Davis:
BTW, the following addresses that bounce should be removed from
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