On 09/21/2016 03:53 AM, Chin Liang See wrote: > On Wed, 2016-09-21 at 03:20 +0200, Marek Vasut wrote: >> On 09/20/2016 08:05 AM, Chin Liang See wrote: >>> To enable configuration of sdr.ctrlcfg.extratime1 register which >>> enable >>> extra clocks for read to write command timing. This is critical to >>> ensure successful LPDDR2 interface >>> >>> Signed-off-by: Chin Liang See <cl...@altera.com> >>> Cc: Marek Vasut <ma...@denx.de> >>> Cc: Dinh Nguyen <dingu...@opensource.altera.com> >>> --- >>> Changes for v2 >>> - Removed v1 patches #2 to #9 as no boards are using LPDDR2 >>> --- >>> arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++++++- >>> arch/arm/mach-socfpga/qts-filter.sh | 2 +- >>> arch/arm/mach-socfpga/wrap_sdram_config.c | 9 +++++++++ >>> drivers/ddr/altera/sdram.c | 3 +++ >>> 4 files changed, 20 insertions(+), 2 deletions(-) >>> [...] >> >> I'd really like to avoid the ifdef, can we do that (fix all boards to >> set the register to zero) ? Otherwise I'm fine with the patch. >> > > Ok I know where you come from. ifdef will cause some test challenge in > term of coverage. In this case, let me fix all boards to zeroes. Thanks
-- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
