On Wednesday, 21 September 2016 14:51:05 BST Matthew Fortune wrote:
> Paul Burton <paul.bur...@imgtec.com> writes:
> > Some systems are configured such that multiple CPUs begin running from
> > their reset vector following a system reset. If this occurs then U-Boot
> > will be run on multiple CPUs simultaneously, which causes all sorts of
> > issues as the multiple instances of U-Boot clobber each other.
> >
> > Prevent this from happening by simply hanging with an infinite loop if
> > we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum
> > as appropriate, is non-zero.
> >
> > Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
> >
> > ---
> >
> > Changes in v2:
> > - Rebase atop u-boot-mips/next
> > - Execute a wait instruction in the loop
> > - Fill delay slots with NOPs
> >
> > arch/mips/cpu/start.S | 31 ++++++++++++++++++++++++++++++-
> > arch/mips/include/asm/mipsregs.h | 7 +++++++
> > 2 files changed, 37 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index
> > 8f85ede..171fbfd 100644
> > --- a/arch/mips/cpu/start.S
> > +++ b/arch/mips/cpu/start.S
> > @@ -108,9 +108,38 @@ ENTRY(_start)
> >
> > .align 4
> >
> > reset:
> > +#if __mips_isa_rev >= 6
> > + .set push
> > + .set reorder
> > + mfc0 t0, CP0_CONFIG, 1
> > + bgez t0, 1f
> > + mfc0 t0, CP0_CONFIG, 2
> > + bgez t0, 1f
> > + mfc0 t0, CP0_CONFIG, 3
> > + bgez t0, 1f
> > + mfc0 t0, CP0_CONFIG, 4
> > + bgez t0, 1f
> > + mfc0 t0, CP0_CONFIG, 5
> > + and t0, t0, MIPS_CONF5_VP
> > + beqz t0, 1f
>
> If you want to shorten this a bit:
>
> According to MD00090-2B-MIPS32PRA-AFP-06.02 config5 must exist if any
> feature it describes is implemented and there are features which are
> mandatory in release6 within config5... therefore config5 is
> guaranteed to exist on release6 upwards.
>
> Matthew
Hi Matthew,
Good point & nice catch! It would be awfully nice if things like this were
clearer in the PRA...
Thanks,
Paul
>
> > +
> > + mfc0 t0, CP0_GLOBALNUMBER
> > + b 2f
> > + .set pop
> > +#endif
> > +
> > +1: mfc0 t0, CP0_EBASE
> > + and t0, t0, EBASE_CPUNUM
> > +
> > + /* Hang if this isn't the first CPU in the system */
> > + beqz t0, 1f
> > + nop
> > +2: wait
> > + b 2b
> > + nop
> >
> > /* Clear watch registers */
> >
> > - MTC0 zero, CP0_WATCHLO
> > +1: MTC0 zero, CP0_WATCHLO
> >
> > mtc0 zero, CP0_WATCHHI
> >
> > /* WP(Watch Pending), SW0/1 should be cleared */ diff --git
> >
> > a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
> > index b4c2dff..9ab5063 100644
> > --- a/arch/mips/include/asm/mipsregs.h
> > +++ b/arch/mips/include/asm/mipsregs.h
> > @@ -39,6 +39,7 @@
> >
> > #define CP0_ENTRYLO0 $2
> > #define CP0_ENTRYLO1 $3
> > #define CP0_CONF $3
> >
> > +#define CP0_GLOBALNUMBER $3, 1
> >
> > #define CP0_CONTEXT $4
> > #define CP0_PAGEMASK $5
> > #define CP0_WIRED $6
> >
> > @@ -361,6 +362,11 @@
> >
> > #define CAUSEF_BD (_ULCAST_(1) << 31)
> >
> > /*
> >
> > + * Bits in the coprocessor 0 EBase register.
> > + */
> > +#define EBASE_CPUNUM 0x3ff
> > +
> > +/*
> >
> > * Bits in the coprocessor 0 config register.
> > */
> >
> > /* Generic bits. */
> >
> > @@ -553,6 +559,7 @@
> >
> > #define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
> > #define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
> > #define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
> >
> > +#define MIPS_CONF5_VP (_ULCAST_(1) << 7)
> >
> > #define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
> > #define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
> > #define MIPS_CONF5_L2C (_ULCAST_(1) << 10)
> >
> > --
> > 2.10.0
> >
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot@lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot
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