From: Yuan Yao
Signed-off-by: Yuan Yao
---
board/freescale/common/qixis.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 113295f..de9daeb 100644
--- a/board/freescale/common/qixis.c
+++ b/boa
From: Yuan Yao
This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.
Signed-off-by: Yuan Yao
---
Changed in v2:
merged the patch:
0009-armv8-ls2080aqds-Enable-QSPI-boot-s
From: Yuan Yao
Signed-off-by: Yuan Yao
---
board/freescale/ls2080aqds/README | 35 +++
1 file changed, 35 insertions(+)
diff --git a/board/freescale/ls2080aqds/README
b/board/freescale/ls2080aqds/README
index 6ddad92..21e8c7b 100644
--- a/board/freescale/ls2080
From: Yuan Yao
The Freescale QSPI driver has been converted to Driver Model.
This patch enable FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.
Signed-off-by: Yuan Yao
---
configs/ls2080aqds_nand_defconfig | 9 +
1 file changed, 9 insertions(+)
diff --git a/confi
From: Yuan Yao
Freescale QSPI and DSPI driver have been converted to Driver Mode.
This converting bring dtb file for u-boot and this increase the size
of u-boot image.
LS2080A nand boot use SPL framework.
This patch increase the size of image load from NAND to RAM in SPL.
Signed-off-by: Yuan Yao
From: Yuan Yao
In order to access QSPI flash we must asserted ISO allowing
the DUT to access the full IFC domain.
But deasserted the unused ISO will allowing maximum performance.
So if we want to access QSPI flash when boot from NAND,
we should use the below board configuration:
Boot Source
From: Yuan Yao
Add QSPI controller and slave dts node for LS2080AQDS board.
Signed-off-by: Yuan Yao
---
arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++
arch/arm/dts/fsl-ls2080a.dtsi| 10 ++
2 files changed, 24 insertions(+)
diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arc
From: Yuan Yao
When QSPI is enabled, NOR flash and QIXIS can't be accessed through IFC
due to pin mux.
Signed-off-by: Yuan Yao
---
include/configs/ls2080aqds.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index dab3
From: Yuan Yao
Enable QSPI flash related configure options.
Signed-off-by: Yuan Yao
---
include/configs/ls2080aqds.h | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 3edb0b9..3cba10a 100644
--- a
From: Yuan Yao
QSPI module output SCLK divisor value is configured through SCFG.
Signed-off-by: Yuan Yao
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
board/freescale/ls2080aqds/ls2080aqds.c| 5 +
2 files changed, 6 insertions(+)
diff --git a/arch/arm/i
From: Yuan Yao
This series add support for QSPI boot on LS2080AQDS.
Yuan Yao (11):
armv8: ls2080aqds: Select QSPI CLK div via SCFG
configs: ls2080a_common: Remove duplicate NOR configs
configs: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable
configs: ls2080aqds: Enable QSPI flash su
From: Yuan Yao
The NOR flash related configure options also appear in ls2080aqds.h and
ls2080ardb.h, and the two files all have included ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.
Signed-off-by: Yuan Yao
---
include/configs/ls2080a_common.h | 7 ---
inc
Hi Simon,
On Sun, 6 Mar 2016 19:27:48 -0700
Simon Glass s...@chromium.org wrote:
> At present simple-panel requires regulator support and will not build
> without it. But some panels do not have a power supply, or at least not one
> that can be controlled. Update the implementation to cope with
On 03/04/2016 12:49 AM, York Sun wrote:
> On 03/02/2016 06:30 PM, Yao Yuan wrote:
> > On 03/03/2016 12:52 AM, York Sun wrote:
> >> On 03/02/2016 02:41 AM, Yuan Yao wrote:
> >>> From: Yuan Yao
> >>>
> >>> This patch adds QSPI boot support for LS2080AQDS board.
> >>> The QSPI boot image need to be p
Hi Masahiro,
On 6 March 2016 at 20:07, Masahiro Yamada wrote:
> Hi Simon,
>
>
> 2016-03-07 11:45 GMT+09:00 Simon Glass :
>> This tool requires that the aliases node be the first node in the tree. But
>> when it is not, it does not handle things gracefully. In fact it crashes.
>>
>> Fix this, and
Hi Simon
On 2016年03月07日 10:39, Simon Glass wrote:
Hi Chris,
On 29 February 2016 at 19:29, Chris Zhong wrote:
Hi Simon
On 03/01/2016 10:04 AM, Simon Glass wrote:
Hi Chris,
On 29 February 2016 at 05:16, Chris Zhong wrote:
The DMC driver in v3.14 kernel[0] get the ddr setting from PMU_SYS_
Add two microcode files for broadwell.
Signed-off-by: Simon Glass
---
arch/x86/dts/microcode/m7240651_001c.dtsi | 1328 +
arch/x86/dts/microcode/mc0306d4_0018.dtsi | 944 ++
2 files changed, 2272 insertions(+)
create mode 100644 arch/x86/dts/mic
Hi Simon,
2016-03-07 11:45 GMT+09:00 Simon Glass :
> This tool requires that the aliases node be the first node in the tree. But
> when it is not, it does not handle things gracefully. In fact it crashes.
>
> Fix this, and add a more helpful error message.
>
> Signed-off-by: Simon Glass
> Report
Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly
uses common code.
Signed-off-by: Simon Glass
---
arch/x86/cpu/broadwell/Makefile | 1 +
arch/x86/cpu/broadwell/lpc.c | 77 +++
arch/x86/include/asm/arch-broadwell/lpc.h
As each core starts up, record its microcode version and CPU ID so these can
be presented with the 'cpu detail' command.
Signed-off-by: Simon Glass
---
arch/x86/cpu/intel_common/microcode_intel.c | 2 +-
arch/x86/cpu/mp_init.c | 5 +
arch/x86/include/asm/microcode.h
We don't need this anymore - we can use device tree and the new pinconfig
driver instead.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/gpio.h | 141 --
board/coreboot/coreboot/coreboot.c| 5 --
board/efi/efi-x86/efi.c
Add a video driver for Intel's broadwell integrated graphics controller.
This uses a binary blob for most init, with the driver just performing a few
basic tasks.
This driver supports VESA as the mode-setting mechanism. Since most boards
don't support driver model yet with VESA, a special case is
Make a few minor updates to make the meaning clearer.
Signed-off-by: Simon Glass
---
doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
b/doc/device-
The code to call the memory reference code is common to several Intel CPUs.
Add common code for performing this init. Intel calls this 'Pre-EFI-Init'
(PEI), where EFI stands for Extensible Firmware Interface.
Signed-off-by: Simon Glass
---
arch/x86/cpu/intel_common/Makefile | 1 +
arch/
Add a driver for the broadwell low-power platform controller hub.
Signed-off-by: Simon Glass
---
arch/x86/cpu/broadwell/Makefile | 2 +
arch/x86/cpu/broadwell/iobp.c | 144
arch/x86/cpu/broadwell/pch.c | 540 ++
arch/x86/
Add a function to set the ID in the IOAPIC.
Signed-off-by: Simon Glass
---
arch/x86/cpu/ioapic.c | 16
arch/x86/include/asm/ioapic.h | 2 ++
2 files changed, 18 insertions(+)
diff --git a/arch/x86/cpu/ioapic.c b/arch/x86/cpu/ioapic.c
index 112a9c6..d15e86c 100644
---
It is useful to automate the process of converting code from coreboot a
little. Add a sed script which performs some common transformations.
Signed-off-by: Simon Glass
---
doc/README.x86 | 9 +
scripts/coreboot.sed | 17 +
2 files changed, 26 insertions(+)
create
Some of the Intel CPU code is common to several Intel CPUs. Move it into a
common location along with required declarations.
Signed-off-by: Simon Glass
---
arch/x86/cpu/intel_common/Makefile| 1 +
arch/x86/cpu/intel_common/cpu_common.c| 111 ++
arch/x86
Add a driver for the broadwell northbridge. This sets up the location of
several blocks of registers.
Signed-off-by: Simon Glass
---
arch/x86/cpu/broadwell/Makefile | 1 +
arch/x86/cpu/broadwell/northbridge.c | 59
2 files changed, 60 insertions(+)
cr
At present the architecture is deduced from the toolchain filename. Allow it
to be specified by the caller.
Signed-off-by: Simon Glass
---
tools/buildman/toolchain.py | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/tools/buildman/toolchain.py b/tools/build
At present buildman allows you to specify the directory containing the
toolchain, but not the actual toolchain prefix. If there are multiple
toolchains in a single directory, this can be inconvenient.
Add a new 'toolchain-prefix' setting to the settings file, which allows
the full prefix (or path
At present if you try to use buildman with the branch 'test' it will
complain that it is unsure whether you mean the branch or the directory.
This is a feature of the 'git log' command that buildman uses. Fix it
by resolving the ambiguity.
Signed-off-by: Simon Glass
---
tools/patman/gitutil.py
At present the priority of a toolchain is calculated from its filename based
on hard-coded rules. Allow it to be specified by the caller. We will use
this in a later patch. Also display the priority and provide a message when
it is overriden by another toolchain of higher priority.
Signed-off-by:
Normally we use a single quote for strings unless there is a reason not to
(such as an embedded single quote). Fix a few counter-examples in this file.
Also add a missing function-argument comment.
Signed-off-by: Simon Glass
---
tools/buildman/toolchain.py | 11 ++-
1 file changed, 6 in
Fix this nit to keep the code consistent.
Signed-off-by: Simon Glass
---
tools/patman/patchstream.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index 6d3c41f..27d031e 100644
--- a/tools/patman/patchstream.py
+++
It is convenient to install symlinks to buildman and patman in the search
patch, such as /usr/local/bin. But when this is done, the -H option fails to
work because it looks in the directory containing the symlink instead of its
target. Fix this.
Signed-off-by: Simon Glass
---
tools/buildman/con
This tool requires that the aliases node be the first node in the tree. But
when it is not, it does not handle things gracefully. In fact it crashes.
Fix this, and add a more helpful error message.
Signed-off-by: Simon Glass
Reported-by: Masahiro Yamada
---
tools/fdtgrep.c | 14 ++
Broadwell needs a special binary blob to set up the PCH. Add code to run
this on start-up.
Signed-off-by: Simon Glass
---
arch/x86/cpu/broadwell/Makefile | 1 +
arch/x86/cpu/broadwell/refcode.c | 108 +++
2 files changed, 109 insertions(+)
create mode 100
This is a little easier on the eyes, particularly when the backlight is set
to maximum.
Signed-off-by: Simon Glass
---
include/configs/x86-chromebook.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index 057d4be..ae969b
At present the board ID GPIOs are hard-coded. Move them to the device tree
so that we can use general SDRAM init code.
Signed-off-by: Simon Glass
---
arch/x86/dts/chromebook_link.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook
Many of the model-specific indexes are common to several Intel CPUs. Add
some more common ones, and remove them from the ivybridge-specific header
file.
Signed-off-by: Simon Glass
---
arch/x86/cpu/ivybridge/model_206ax.c | 5 +--
arch/x86/include/asm/arch-ivybridge/model_206ax.h |
The SDRAM SPD (Serial Presence Detect) information should be contained
with the SDRAM controller. This makes it easier for the controller to access
it and removes the need for a separate compatible string.
As a first step, move the information.
Signed-off-by: Simon Glass
---
arch/x86/dts/chrom
This adds the broadwell architecture, with the CPU driver and some useful
header files.
Signed-off-by: Simon Glass
---
arch/x86/Kconfig| 1 +
arch/x86/cpu/Makefile | 1 +
arch/x86/cpu/broadwell/Kconfig | 30 ++
arch/x86/cpu/bro
The clrsetbits_...() macros are useful for working with memory mapped I/O.
But they do not work with I/O space, as used on x86 machines.
Add some macros to provide similar features for I/O.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/io.h | 22 ++
1 file changed, 22
In order to use GPIO phandles we need to add some GPIO properties as
specified by the GPIO bindings. Add these for link.
Signed-off-by: Simon Glass
---
arch/x86/dts/chromebook_link.dts | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/x86/dts/chromebook_link.
There is an extra line in the comment in the header. Remove it.
Signed-off-by: Simon Glass
---
include/configs/x86-chromebook.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index ae969b9..c94096a 100644
--- a/include/conf
Intel has invented yet another binary blob which firmware is required to
run. This is run after SDRAM is ready. It is linked to load at a particular
address, typically 0, but is a relocatable ELF so can be moved if required.
Add support for this in the build system. The file should be placed in th
Add a SATA driver for broadwell. This supports connecting an SSD and the
usual U-Boot commands to read and write data.
Signed-off-by: Simon Glass
---
arch/x86/cpu/broadwell/Makefile | 1 +
arch/x86/cpu/broadwell/sata.c | 269
2 files changed, 270 ins
This is similar to MCH in that it is used in various drivers. Add it to
the common header.
Signed-off-by: Simon Glass
---
arch/x86/cpu/ivybridge/bd82x6x.c | 1 +
arch/x86/cpu/ivybridge/lpc.c | 6 --
arch/x86/include/asm/arch-ivybridge/pch.h | 5 -
arch/x86/include/
This is not needed now that the memory controller driver has the SPD data
in its own node.
Signed-off-by: Simon Glass
---
arch/x86/dts/chromebook_link.dts | 1 -
include/fdtdec.h | 1 -
lib/fdtdec.c | 1 -
3 files changed, 3 deletions(-)
diff --git a/arch/x8
Some of the Intel ME code is common to several Intel CPUs. Move it into a
common location. Add a header file for report_platform.c also.
Signed-off-by: Simon Glass
---
arch/x86/cpu/intel_common/Makefile | 2 +
.../cpu/{ivybridge => intel_common}/me_status.c| 20 +-
.../{i
Add an address which can be used for loading and running the reference code
when needed.
Signed-off-by: Simon Glass
---
include/configs/x86-chromebook.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index c575dab..057d4
This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.
Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard
Various less-visible drivers are provided to make the ab
The Intel GPIO driver can set up the GPIO pin mapping when the first GPIO
is probed. However, it assumes that the first GPIO to be probed is in the
first GPIO bank. If this is not the case then the init will write to the
wrong registers.
Fix this. Also add a note that this code is deprecated. We s
Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI
without any 16-bit init. This can help during development by allowing U-Boot
to avoid doing all the init required by the platform.
In this case we cannot rely on the GDT settings. U-Boot will hang or crash
if these are wrong
Broadwell uses a binary blob called the memory reference code (MRC) to start
up its SDRAM. This is similar to ivybridge so we can mostly use common code
for running this blob.
Signed-off-by: Simon Glass
---
arch/x86/cpu/broadwell/Makefile| 1 +
arch/x86/cpu/broadwell/sdram.c
This same name is used in USB. Add a prefix to distinguish it.
Signed-off-by: Simon Glass
---
arch/x86/cpu/cpu.c | 4 ++--
arch/x86/cpu/intel_common/cpu_common.c | 4 ++--
arch/x86/include/asm/processor.h | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff -
Two power-on-self-test values are the same. Fix this.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/post.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h
index f49ce99..6b774bd 100644
--- a/arch/x86/include
Hi Masahiro,
On 23 February 2015 at 06:42, Simon Glass wrote:
> Hi Masahiro,
>
> On 23 February 2015 at 05:52, Masahiro Yamada
> wrote:
>> Hi Simon,
>>
>>
>> When I try to run Buildman against a branch named "test",
>> it fails with a weird error message.
>>
>>
>>
>> $ git branch
>> * master
>>
The timeout step is always 50us. By updating apic_wait_timeout() to print
the debug messages we can simplify the code. Also tidy up a few messages and
comments while we are here.
Signed-off-by: Simon Glass
---
arch/x86/cpu/mp_init.c | 79 +-
1 fil
Hi Stephen,
On 4 October 2015 at 19:19, Stephen Warren wrote:
> On 10/04/2015 10:38 AM, Simon Glass wrote:
>> Hi Stephen,
>>
>> On 3 October 2015 at 20:20, Stephen Warren wrote:
>>> On 10/03/2015 08:30 AM, Simon Glass wrote:
Hi Stephen,
On 2 October 2015 at 00:27, Stephen Warren
Hi Joe,
On 7 May 2015 at 03:17, Joe Hershberger wrote:
> Hi Simon,
>
> Is there a way to make buildman compile sandbox with a non-system tool
> chain? I've tried creating an alias from sandbox to i386 and removing
> the "root" entry. It then simply claims not to have a sandbox tool
> chain.
>
> T
Hi Mugunthan,
On 2 March 2016 at 22:06, Mugunthan V N wrote:
> When a platform is converted to support DM and when its scsi
> driver is not converted to support DM, there is a build break as
> multiple definition of scsi_init(). So select CONFIG_DISK only
> when the platform supports CONFIG_DISK.
On 29 February 2016 at 16:48, York Sun wrote:
> FIT image supports load address and entry address. Getting these
> addresses can use a common function.
>
> Signed-off-by: York Sun
>
> ---
>
> Changes in v6:
> Drop patches which convert ulong to phys_addr_t
> Revert to use original ulong
>
> C
Hi Chris,
On 29 February 2016 at 19:29, Chris Zhong wrote:
> Hi Simon
>
>
> On 03/01/2016 10:04 AM, Simon Glass wrote:
>>
>> Hi Chris,
>>
>> On 29 February 2016 at 05:16, Chris Zhong wrote:
>>>
>>> The DMC driver in v3.14 kernel[0] get the ddr setting from PMU_SYS_REG2,
>>> and it expects uboot
On 5 March 2016 at 10:30, Stephen Warren wrote:
> When running sandbox, the following phases occur, each with different
> malloc implementations or behaviors:
>
> 1) Dynamic linker execution, using the dynamic linker's own malloc()
> implementation. This is fully functional.
>
> 2) After U-Boot's
On 29 February 2016 at 16:48, York Sun wrote:
> FIT image supports more than 32 bits in addresses by using #address-cell
> field. Fixing 64-bit support by using this field.
>
> Signed-off-by: York Sun
>
> ---
>
> Changes in v6:
> Revert back to use original "ulong" instead of "phys_addr_t"
>
On 29 February 2016 at 19:51, Masahiro Yamada
wrote:
>
> Simple MFD devices can bind children without special bus configuration.
> Like Linux, let's handle "simple-mfd" in the same way as "simple-bus".
>
> Signed-off-by: Masahiro Yamada
> ---
>
> drivers/core/simple-bus.c | 1 +
> 1 file changed
On 5 March 2016 at 06:32, FUKAUMI Naoki wrote:
> on v2016.03-rc3, size of SPL image compiled by gcc 5.3.0 is too large for
> Firefly-RK3288. (it's fine for Rock2)
>
> $ gcc --version
> gcc (Ubuntu/Linaro 5.3.0-3ubuntu1~14.04) 5.3.0 20151204
> Copyright (C) 2015 Free Software Foundation, Inc.
> Thi
On 5 March 2016 at 10:30, Stephen Warren wrote:
> Following the previous patch, malloc() is never called before gd is set,
> so we can remove the special-case check for this condition.
>
> This reverts commit 854d2b9753e4 "dlmalloc: ensure gd is set for early
> alloc".
>
> Cc: Rabin Vincent
> Sig
On 5 March 2016 at 12:07, Tom Rini wrote:
> - The macro __BIGGEST_ALIGNMENT__ is gcc-specific. If it is not defined
> we'll just assume 16. This is correct for at least the common cases
> and LLVM does not provide an equivalent macro.
> - When linking U-Boot we're passing -T to the linker, a
Hi Stephen,
On 5 March 2016 at 23:26, Stephen Warren wrote:
>
> On 02/05/2016 09:19 PM, Stephen Warren wrote:
>>
>> On 02/05/2016 02:43 PM, Eric Anholt wrote:
>>>
>>> For Raspberry Pi, we had the input clock rate to the pl011 fixed in
>>> the rpi.c file, but it may be changed by firmware due to u
Add a GPIO driver for the GPIO peripheral found on broadwell devices.
Signed-off-by: Simon Glass
---
drivers/gpio/Kconfig| 9 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/intel_broadwell_gpio.c | 198
3 files changed, 208 in
On 2 March 2016 at 04:38, Adam Ford wrote:
> A few boards still use ns16550_platdata structures, but assume the structure
> is going to be in a specific order. By explicitly naming each entry,
> this should also help 'future-proof' in the event the structure changes.
>
> Tested on the Logic PD Tor
Broadwell requires quite a bit of power-management setup. Add code to set
this up correctly.
Signed-off-by: Simon Glass
---
arch/x86/cpu/broadwell/Makefile | 1 +
arch/x86/cpu/broadwell/power_state.c | 89 +
arch/x86/include/asm/arch-broadwell/pm.h | 129
At present the MRC options are private to ivybridge. Other Intel CPUs also
use these settings. Move them to a common place.
Signed-off-by: Simon Glass
---
arch/x86/Kconfig | 39 +++
arch/x86/cpu/ivybridge/Kconfig | 27 +--
Update a few points which have become out-of-date.
Signed-off-by: Simon Glass
---
doc/README.x86 | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/doc/README.x86 b/doc/README.x86
index a3f45c7..b87fec4 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -20,8
Provide a way to determine the HSIO (high-speed I/O) version supported by
the Intel Management Engine (ME) implementation on the platform.
Signed-off-by: Simon Glass
---
arch/x86/cpu/broadwell/Makefile | 1 +
arch/x86/cpu/broadwell/me.c | 57 +
2 fil
It is common with memory-mapped I/O to use the address of a structure member
to access memory, as in:
struct some_regs {
u32 ctrl;
u32 data;
}
struct some_regs *regs = (struct some_regs *)BASE_ADDRESS;
writel(1, ®->ctrl);
writel(2, ®->data);
This does not currently wo
GPIO pins need to be set up on start-up. Add a driver to provide this,
configured from the device tree.
The binding is slightly different from the existing ICH6 binding, since that
is quite verbose. The new binding should be just as extensible.
Signed-off-by: Simon Glass
---
arch/x86/cpu/broad
Each CPU needs to have its microcode loaded. Add support for this so that
all CPUs will have the same version.
Signed-off-by: Simon Glass
---
arch/x86/cpu/cpu.c | 1 +
arch/x86/cpu/intel_common/car.S | 2 ++
arch/x86/cpu/mp_init.c | 6 --
arch/x86/include/asm/microc
Add a driver which sets up the pin configuration on x86 devices with an ICH6
(or later) Platform Controller Hub.
The driver is not in the pinctrl uclass due to some oddities of the way x86
devices work:
- The GPIO controller is not present in I/O space until it is set up
- This is done by writing
Rather than setting up the pin configuration in the GPIO driver, use the
new pinctrl driver to do it.
Signed-off-by: Simon Glass
---
configs/bayleybay_defconfig | 2 +
configs/cougarcanyon2_defconfig | 2 +
configs/crownbay_defconfig | 2 +
configs/galileo_defconfig | 2 +
Adjust the existing implementation to use the new common SDRAM init code.
Signed-off-by: Simon Glass
---
arch/x86/cpu/ivybridge/sdram.c | 394 +
1 file changed, 83 insertions(+), 311 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu
This code is used on several Intel CPUs. Move it into a common location.
Signed-off-by: Simon Glass
---
arch/x86/cpu/intel_common/Makefile | 3 +++
arch/x86/cpu/intel_common/car.S| 2 +-
arch/x86/cpu/{ivybridge => intel_common}/microcode_intel
Add one more step into the init sequence. This fixes the keyboard on samus,
which otherwise does not work.
Signed-off-by: Simon Glass
---
drivers/input/i8042.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c
index 661d7fd..12f8934 100644
-
At present pin configuration on link does not use the standard mechanism,
but some rather ugly custom code. As a first step to resolving this, add the
pin configuration to the device tree.
Four of the GPIOs must be available before relocation (for SDRAM pin
strapping).
Signed-off-by: Simon Glass
At present on x86 machines with use cache-as-RAM, the memory goes away just
before board_init_r() is called. This means that serial drivers are
no-longer unavailable, until initr_dm() it called, etc.
Any attempt to use printf() within this period will cause a hang.
To fix this, mark the serial de
Some of the LPC code is common to several Intel LPC devices. Move it into a
common location.
Signed-off-by: Simon Glass
---
arch/x86/cpu/intel_common/Makefile| 1 +
arch/x86/cpu/intel_common/lpc_common.c| 102 ++
arch/x86/cpu/ivybridge/bd82x6x.c
Two comments are missing a parameter and there is an extra blank line. Also
two of the region access macros are misnamed. Correct these problems.
Signed-off-by: Simon Glass
---
drivers/pci/pci-uclass.c | 1 -
include/pci.h| 6 --
2 files changed, 4 insertions(+), 3 deletions(-)
These two identifiers can be useful for drivers which need to adjust their
behaviour depending on the CPU family or stepping (revision).
Signed-off-by: Simon Glass
---
arch/x86/cpu/cpu.c | 10 ++
arch/x86/include/asm/cpu.h | 14 ++
2 files changed, 24 insertions(+)
The Intel SIPI (start-up inter-processor interrupt) vector is the entry
point for each secondary CPU (also called an AP - applications processor).
The assembler and C code are linked, so add comments to indicate this.
Signed-off-by: Simon Glass
---
arch/x86/cpu/sipi_vector.S | 1 +
arch/x86/in
It is common to read a config register value, clear and set some bits, then
write back the updated value. Add functions to do this in one step, for
convenience.
Signed-off-by: Simon Glass
---
drivers/pci/pci-uclass.c | 57
include/pci.h
Output the pointer returned by each call to malloc(). This can be useful
when debugging memory problems.
Signed-off-by: Simon Glass
---
common/malloc_simple.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/common/malloc_simple.c b/common/malloc_simple.c
index 479a1e4
Some functions do not change the struct gpio_desc parameter. Update these to
use const so this is clear.
Signed-off-by: Simon Glass
---
drivers/gpio/gpio-uclass.c | 10 +-
include/asm-generic/gpio.h | 10 +-
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/driver
This function was removed in the previous clean-up. Drop it from the header
file also.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
b/arch/x86/include/asm/
There are several blocks of registers that are accessed from all over the
code on Intel CPUs. These don't currently have their own driver and it is
not clear whether having a driver makes sense.
An example is the Memory Controller Hub (MCH). We map it to a known location
on some Intel chips (mostl
This does not need to be modified at run-time, so make it const.
Signed-off-by: Simon Glass
---
arch/x86/cpu/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 6c3a748..8800e09 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cp
Enable the microcode feature so that the microcode version is shown with the
'cpu detail' command.
Signed-off-by: Simon Glass
---
arch/x86/cpu/ivybridge/model_206ax.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c
b/arch/x86/cpu/ivybr
This cache-as-RAM (CAR) code is common to several Intel chips. Create a new
intel_common directory and move it in there.
Signed-off-by: Simon Glass
---
arch/x86/cpu/Makefile | 1 +
arch/x86/cpu/intel_common/Makefile | 7 +++
arch/x86/cpu/{ivybridge => in
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